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Электронный компонент: FAN5066

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PRELIMINARY INFORMATION
describes products that are not in full production at the time of printing. Specifications are based on design goals
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
www.fairchildsemi.com
REV. 2.1.4 11/13/01
Features
Output adjustable from 400mV to 3.5V
Synchronous Rectification
Adjustable operation from 80KHz to 1MHz
Integrated Power Good and Enable functions
Overvoltage protection
Overcurrent protection
Drives N-channel MOSFETs
20 pin SOIC or TSSOP package
Applications
Power supply DDR SDRAM VTT
Power Supply HSTL
Power Supply for ASICs
Adjustable ultra-low voltage step-down power supply
Description
The FAN5066 is a synchronous mode DC-DC controller IC
which provides an adjustable output voltage for ultra-low
voltage applications, down to 400mV. The FAN5066 uses a
high level of integration to deliver load currents in excess of
19A from a 5V source with minimal external circuitry.
Synchronous-mode operation offers optimum efficiency over
the entire output voltage range, and the internal oscillator
can be programmed from 80KHz to 1MHz for additional
flexibility in choosing external components. The FAN5066
also offers integrated functions including a four-bit
DAC-controlled reference, Power Good, Output Enable,
over-voltage protection and current limiting.
Block Diagram
DIGITAL
CONTROL
+5V
1
20
16
19 18
17
8
2
3
9
7
12
13
4
5
+
1.24V
REFERENCE
4-BIT
DAC
POWER
GOOD
OSC
PWRGD
VREF
CNTRL
VID1
VID2
VID4
VID3
ENABLE
+
+
+
+5V
VO
FAN5066
+12V
FAN5066
Ultra Low Voltage Synchronous DC-DC Controller
FAN5066
PRODUCT SPECIFICATION
2
REV. 2.1.4 11/13/01
Pin Assignments
Pin Definitions
Pin Number Pin Name
Pin Function Description
1
CEXT
Oscillator Capacitor Connection
. Connecting an external capacitor to this pin sets
the internal oscillator frequency. Layout of this pin is critical to system performance.
See Application Information for details.
2
ENABLE
Output Enable
. A logic LOW on this pin will disable the output. An internal pull-up
resistor allows for either open collector or TTL compatibility.
3
PWRGD
Power Good Flag
. An open collector output that will be at logic LOW if the output
voltage is not within
12% of the nominal output voltage setpoint.
4
IFB
High Side Current Feedback
. Pins 4 and 5 are used as the inputs for the current
feedback control loop. Layout of these traces is critical to system performance. See
Application Information for details.
5
VFB
Voltage Feedback
. Pin 5 is used as the input for the voltage feedback control loop and
as the low side current feedback input. See Application Information for details regarding
correct layout.
6
VCCA
Analog VCC
. Connect to system 5V supply and decouple with a 0.1
F ceramic
capacitor.
7
VCCP
Power VCC for low side FET driver
. Connect to system 5V supply and place a 1
F
ceramic capacitor for decoupling and local charge storage.
8
VID4
VID4 Input
. A logic 1 on this open collector/TTL input will enable the VID3VID0 inputs
to set the output from 2.1V to 3.5V, and a logic 0 will set the output from 1.3V to 2.05V,
as shown in Table 1. Pullup resistors are internal to the controller.
9
LODRV
Low Side FET Driver
. Connect this pin to the gate of an N-channel MOSFET for
synchronous operation. The trace from this pin to the MOSFET gate should be < 0.5".
10, 11
GNDP
Power Ground
. Return pin for high currents flowing in pins 7 and 13 (VCCP and
VCCQP). Connect to a low impedance ground.
12
HIDRV
High Side FET Driver
. Connect this pin to the gate of an N-channel MOSFET. The
trace from this pin to the MOSFET gate should be < 0.5".
13
VCCQP
Power VCC
. For high side FET driver. VCCQP must be connected to a voltage of at
least VCCA + V
GS,ON
(MOSFET), and place a 1
F ceramic capacitor for decoupling
and local charge storage. See Application Information for details
14
GNDD
Digital Ground
. Return path for digital logic. Connect to a low impedance system
ground plane to minimize ground loops.
15
GNDA
Analog Ground
. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
16
CNTRL
Voltage Control
. The voltage forced on this pin determines the output voltage of the
converter.
17-19
VID1-VID3
Voltage Identification Code Inputs
. These open collector/TTL compatible inputs will
program the output voltage of the reference over the ranges specified in Table 1.
Pull-up resistors are internal to the controller.
20
VREF
Reference Voltage Test Point
. This pin provides access to the DAC output and should
be decoupled to ground using 0.1F capacitor.
1
2
3
4
5
6
8
7
VREF
VID1
VID2
VID3
CNTRL
GNDA
VCCQP
GNDD
20
19
18
17
16
15
13
9
12
10
11
14
CEXT
ENABLE
PWRGD
IFB
FAN5066
VFB
VCCA
VID4
VCCP
GNDP
HIDRV
GNDP
LODRV
PRODUCT SPECIFICATION
FAN5066
REV. 2.1.4 11/13/01
3
Absolute Maximum Ratings
Operating Conditions
Supply Voltages, VCCA, VCCP, VCCQP to GND
13V
Supply Voltage VCCQP, Charge Pump (V
IN
+VCCA)
18V
Voltage Identification Code Inputs, VID3-VID0
13V
VREF Output Current
3mA
Junction Temperature, T
J
150
C
Storage Temperature
-65 to 150
C
Lead Soldering Temperature, 10 seconds
300
C
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage, VCCA, VCCP
4.75
5
5.25
V
Input Logic HIGH
2.0
V
Input Logic LOW
0.8
V
Ambient Operating Temp
0
70
C
Output Driver Supply, VCCQP
8.5
12
V
Electrical Specifications
(V
CCA
= 5V, V
CNTRL
= 900mV, f
osc
= 300 KHz, and T
A
= +25
C using circuit in Figure 1, unless otherwise noted)
The
denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
Initial Voltage Setpoint
I
LOAD
= 0.8A, V
CTRL
= 1.25V
V
CTRL
= 900mV
1.237
891
1.250
900
1.263
909
V
mV
Output Temperature Drift
T
A
= 0 to 70
C V
OUT
= 1.25V
V
OUT
= 900mV
+6
+4
mV
mV
Load Regulation
I
LOAD
= 0.8A to 3A
-20
mV
Line Regulation
V
IN
= 4.75V to 5.25V
2
mV
Output Ripple
20MHz BW, I
LOAD
= 3A
13
mVpk
DAC Output Voltage
See Table 1
1.3
3.4
V
DAC Accuracy
-3
+3
%
Short Circuit Detect Threshold
90
120
150
mV
Output Driver Rise and Fall Time
See Figure 3
80
nsec
Output Driver Deadtime 1
See Figure 3
5
%/f
OSC
Output Driver Deadtime 2
See Figure 3
80
nsec
Turn-on Response Time
I
LOAD
= 0A to 3A
10
msec
Oscillator Range
80
1000
KHz
Oscillator Frequency
C
EXT
= 100 pF
270
300
330
KHz
PWRGD threshold
Logic High
Logic Low
93
88
107
112
%V
OUT
%V
OUT
PWRGD Minimum Operating
Voltage
1.0
V
Max Duty Cycle
90
95
%
Control Pin Input Current
V
CTRL
= 400mV to 3.5V
235
A
FAN5066
PRODUCT SPECIFICATION
4
REV. 2.1.4 11/13/01
Table 1. DAC Output Voltage Programming Codes
Note:
1. 0 = processor pin is tied to GND.
1 = processor pin is open.
VID4
VID3
VID2
VID1
VREF
0
1
1
1
1.30V
0
1
1
0
1.40V
0
1
0
1
1.50V
0
1
0
0
1.60V
0
0
1
1
1.70V
0
0
1
0
1.80V
0
0
0
1
1.90V
0
0
0
0
2.00V
1
1
1
1
No Output
1
1
1
0
2.2V
1
1
0
1
2.4V
1
1
0
0
2.6V
1
0
1
1
2.8V
1
0
1
0
3.0V
1
0
0
1
3.2V
1
0
0
0
3.4V
PRODUCT SPECIFICATION
FAN5066
REV. 2.1.4 11/13/01
5
Typical Operating Characteristics
(VCCA, VCCD = 5V, f
OSC
= 280 KHz, and T
A
= +25
C using circuit in Figure 1, unless otherwise noted)
Output Current (A)
Output Current (A)
V
OUT
(V)
Output Voltage vs. Output Current,
R
SENSE
= 6m
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 1 2 3 4 5
Output Current (A)
V
OUT
(V)
18
39
75
150
300
560
C
EXT
(pf)
Oscillator Frequency vs. C
EXT
50
250
450
650
850
1050
1250
Frequency (KHz)
80
70
60
50
40
30
20

0.1 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
Efficiency vs. Output Current
Efficiency (%)
Load Regulation VOUT = 0.9V
0.895
0.890
0.885
0.880
0.875
0.870
0 0.5 1 1.5 2 2.5 3