www.fairchildsemi.com
AthlonTM and HammerTM are registered trademarks of AMD
. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.7 2/18/03
Block Diagram
22
VID0
11
10
14
13
17
16
24
-
+
OSC
Digital
Control
Power
Good
5-Bit
DAC
VID1
VID2
VID3
VID4
1 2 3 4 5
+12V
PWRGD
-
+
ENABLE/SS
VO
AGND
7
DROOP/E*
18
6
+12V
15
5V Reg
BYPASS
23
R
T
+12V
+12V
12
8
9
21
+12V
Digital
Control
-
+
-
+
-
+
19
ILIM
20
BOOT A
BOOT B
GNDA
Current
Limit
UVL O
FAN5098
Two Phase Interleaved Synchronous Buck Converter
for AMD
HammerTM
Features
Programmable output from 800mV to 1.550V in 25mV
steps using an integrated 5-bit DAC
Two interleaved synchronous phases for maximum
performance
100nsec transient response time
Built-in current sharing between phases
Remote sense
Programmable Active Droop
(Voltage Positioning)
Programmable switching frequency from 100KHz to
1MHz per phase
Adaptive delay gate switching
Integrated high-current gate drivers
Integrated Power Good, OV, UV, Enable/Soft Start
functions
Drives N-channel MOSFETs
Operation optimized for 12V operation
High efficiency mode (E*) at light load
Overcurrent protection using MOSFET sensing
24 pin TSSOP package
Applications
VRM/VRD for 64-Bit AthlonTM and OpteronTM CPU's
VRM/VRD for Advanced CPU's
Programmable step-down power supply
Description
The FAN5098 is a synchronous two-phase DC-DC controller
IC which provides a highly accurate, programmable output
voltage for the AMD
HammerTM processor. Two inter-
leaved synchronous buck regulator phases with built-in cur-
rent sharing operate 180 out of phase to provide the fast
transient response needed to satisfy high current applications
while minimizing external components.
The FAN5098 features Programmable Active Droop
for
transient response with minimum output capacitance. It has
integrated high-current gate drivers, with adaptive delay gate
switching, eliminating the need for external drive devices.
The FAN5098 uses a 5-bit D/A converter to program the out-
put voltage from 800mV to 1.550V in 25mV steps with an
accuracy of 1%. The FAN5098 uses a high level of integra-
tion to deliver load currents in excess of 50A from a 12V
source with minimal external circuitry.
The FAN5098 also offers integrated functions including
Power Good, Output Enable/Soft Start, under-voltage lock-
out, over-voltage protection, and adjustable current limiting
with independent current sense on each phase. It is available
in a 24 pin TSSOP package.
FAN5098
PRODUCT SPECIFICATION
2
REV. 1.0.7 2/18/03
Pin Assignments
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1-5
VID0-4
Voltage Identification Code Inputs.
Open collector/TTL compatible inputs will
program the output voltage over the ranges specified in Table 1. Internally Pulled-
Up.
6
BYPASS
5V Rail.
Bypass this pin with a 0.1
F ceramic capacitor to AGND.
7
AGND
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
8
LDRVB
Low Side FET Driver for B.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5
"
.
9
PGNDB
Power Ground B.
Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
10
SWB
High side driver source and low side driver drain switching node B.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
11
HDRVB
High Side FET Driver B.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5
"
.
12
BOOTB
Bootstrap B.
Input supply for high-side MOSFET.
13
BOOTA
Bootstrap A.
Input supply for high-side MOSFET.
14
HDRVA
High Side FET Driver A.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should optimally be <0.5
"
.
15
SWA
High side driver source and low side driver drain switching node A.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
16
PGNDA
Power Ground A.
Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
17
LDRVA
Low Side FET Driver for A.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should optimally be <0.5
"
.
18
VCC
VCC.
Internal IC supply. Connect to system 12V supply, and decouple with a 10
resistor and 1
F ceramic capacitor.
19
PWRGD
Power Good Flag.
An open collector output that will be logic LOW if the output
voltage is less than 350mV less than the nominal output voltage setpoint. Power
Good is prevented from going low until the output voltage is out of spec for
500sec.
FAN5098
VID0
VID1
VID2
VID3
VID4
AGND
BYPASS
LDRVB
PGNDB
SWB
HDRVB
BOOTB
VFB
RT
ENABLE/SS
DROOP/E*
ILIM
PWRGD
VCC
LDRVA
PGNDA
SWA
HDRVA
BOOTA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PRODUCT SPECIFICATION
FAN5098
REV. 1.0.7 2/18/03
3
Absolute Maximum Ratings
(Absolute Maximum Ratings are the values beyond which the device
may be damaged or have it's useful life impaired. Functional operation under these conditions is not implied.)
Thermal Ratings
Recommended Operating Conditions (See Figure 2)
20
ILIM
Current Limit.
A resistor from this pin to ground sets the over current trip level.
21
DROOP/E*
Droop Control/Energy Star Mode Control.
A resistor from this pin to ground
sets the amount of droop by controlling the gain of the current sense amplifier.
When this pin is pulled high to BYPASS, the phase A drivers are turned off for
Energy-star operation.
22
ENABLE/SS
Output Enable/Softstart.
A logic LOW on this pin will disable the output. An
10A internal current source allows for open collector control. This pin also
doubles as soft start.
23
RT
Frequency Set.
A resistor from this pin to ground sets the switching frequency.
24
VFB
Voltage Feedback.
Connect to the desired regulation point at the output of the
converter.
Parameter
Min.
Max.
Unit
Supply Voltage VCC
15
V
Supply Voltages BOOT to PGND
24
V
BOOT to SW
24
V
Voltage Identification Code Inputs, VID0-VID4
6
V
VFB, ENABLE/SS, PWRGD, DROOP/E*
6
V
SWA, SWB to AGND (<1s)
-3
15
V
PGNDA, PGNDB to AGND
-0.5
0.5
V
Gate Drive Current, peak pulse
3
A
Junction Temperature, T
J
-55
150
C
Storage Temperature
-65
150
C
Parameter
Min.
Typ.
Max.
Unit
Lead Soldering Temperature, 10 seconds
300
C
Power Dissipation, P
D
650
mW
Thermal Resistance Junction-to-Case,
JC
16
C/W
Thremal Resistance Junction-to-Ambient,
JA
84
C/W
Parameter
Conditions
Min.
Max.
Units
Output Driver Supply, BOOTA, B
16
22
V
Ambient Operating Temperature
0
70
C
Supply Voltage V
CC
10.8
13.2
V
Pin Number
Pin Name
Pin Function Description
FAN5098
PRODUCT SPECIFICATION
4
REV. 1.0.7 2/18/03
Electrical Specifications
(V
CC
= 12V, VID = [00100] = 1.450V, and T
A
= +25C using circuit in Figure 2, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Notes:
1. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5m
trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal
performance. Nominal output is offset +25mV vs. VID table.
2. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with AMD
specification of V
DAC
50mV.
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Supply
UVLO Hysteresis
1.0
V
12V UVLO
Rising Edge
8.5
9.6
10.4
V
12V Supply Current
PWM Output Open
20
mA
Internal Voltage Regulator
BYPASS Voltage
4.75
5
5.25
V
BYPASS Capacitor
100
nF
VREF and DAC
Output Voltage
See Table 1
0.800
1.550
V
Initial Voltage Setpoint
1
I
LOAD
= 0A, VID = [00100]
1.466
1.475
1.489
V
Output Temperature Drift
T
A
= 0 to 70C
5
mV
Line Regulation
V
CC
= 11.4V to 12.6V
130
V
Droop
2
I
LOAD
= 52A, R
DROOP
= 4.99k
23
mV
Programmable Droop Range
0
1.25
m
Response Time
V
out
= 10mV
100
nsec
Current Mismatch
R
DS,on
(A) = R
DS,on
(B),
I
LOAD
= 52A Droop = 1m
5
%
VID Inputs
Input LOW current, VID pins
V
VID
= 0.4V
-60
A
VID V
IH
2.0
V
VID V
IL
0.8
V
No CPU VID Latency
VID = [11111] to PWM low
200
ns
Oscillator
Oscillator Frequency
RT = 54.9k
440
500
560
kHz
Oscillator Range
RT = 137.5k
to 13.75 k
200
2000
kHz
Maximum Duty Cycle
RT = 137.5k
90
%
Minimum LDRV on-time
RT = 13.75k
330
nsec
Gate Drive
Gate Drive On-Resistance
1.0
Output Driver Rise & Fall Time
See Figure 1, C
L
= 3000pF
20
nsec
Enable/Soft Start
Soft Start Current
10
A
Enable Threshold
ON
OFF
1.0
0.4
V
Power Good
PWRGD Threshold
Logic LOW, V
VID
V
PWRGD
300
350
367
mV
PWRGD Output Voltage
I
sink
= 4mA
0.4
V
PWRGD Delay
High
Low
500
sec
PWRGD Delay
Low
High
5
20
ms
OVP and OTP
Output Overvoltage Detect
2.1
2.3
V
Over Temperature Shutdown
130
140
150
C
Over Temperature Hysteresis
40
C
PRODUCT SPECIFICATION
FAN5098
REV. 1.0.7 2/18/03
5
Gate Drive Test Circuit
Figure 1. Output Drive Timing Diagram
Table 1. Output Voltage Programming Codes
Note: Nominal output is typically offset +25mV from VID table.
VID4
VID3
VID2
VID1
VID0
V
OUT
to CPU
1
1
1
1
1
OFF
1
1
1
1
0
0.800V
1
1
1
0
1
0.825V
1
1
1
0
0
0.850V
1
1
0
1
1
0.875V
1
1
0
1
0
0.900V
1
1
0
0
1
0.925V
1
1
0
0
0
0.950V
1
0
1
1
1
0.975V
1
0
1
1
0
1.000V
1
0
1
0
1
1.025V
1
0
1
0
0
1.050V
1
0
0
1
1
1.075V
1
0
0
1
0
1.100V
1
0
0
0
1
1.125V
1
0
0
0
0
1.150V
0
1
1
1
1
1.175V
0
1
1
1
0
1.200V
0
1
1
0
1
1.225V
0
1
1
0
0
1.250V
0
1
0
1
1
1.275V
0
1
0
1
0
1.300V
0
1
0
0
1
1.325V
0
1
0
0
0
1.350V
0
0
1
1
1
1.375V
0
0
1
1
0
1.400V
0
0
1
0
1
1.425V
0
0
1
0
0
1.450V
0
0
0
1
1
1.475V
0
0
0
1
0
1.500V
0
0
0
0
1
1.525V
0
0
0
0
0
1.550V
tR
tF
tDT
tDT
HDRV
LDRV
1.2V
2V
10%
3000pF
V
OUT
2V
90%
90%
2.5V
10%
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