www.fairchildsemi.com
Pentium is a registered trademark of Intel Corporation. Athlon is a registered trademark of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
REV. 1.0.1 2/4/02
Block Diagram
2 3
22
VID0
11
10
14
13
17
16
24
-
+
-
+
OSC
Digital
Control
Power
Good
5-Bit
DAC
VID1
VID2
VID3
VID4
1
4
5
+12V
PWRGD
-
+
ENABLE/SS
VO
GNDA
7
DROOP/E*
18
6
+12V
15
5V Reg
Bypass
23
+12V
+12V +5V
+12V +5V
+12V
12
8
9
21
+12V
Digital
Control
-
+
-
+
19
ILIM
20
FAN5193
Two Phase Interleaved Synchronous Buck
Converter
Features
Programmable output from 1.10V to 1.85V in 25mV steps
using an integrated 5-bit DAC
Two interleaved synchronous phases for maximum
performance
100nsec response time
Built-in current sharing between phases
Remote sense
Programmable Active Droop
(Voltage Positioning)
Programmable frequency from 200KHz to 2MHz
Adaptive delay gate switching
Integrated high-current gate drivers
Integrated Power Good, OV, UVLO, Enable/Soft Start
functions
Drives N-channel MOSFETs
Operation optimized for 12V operation
High efficiency mode (E*) at light load
Overcurrent protection using MOSFET sensing
24 pin TSSOP package
Applications
Power supply for Pentium
IV
Power supply for Athlon
VRM for Pentium IV processor
Programmable step-down power supply
Description
The FAN5193 is a synchronous multi-phase DC-DC control-
ler IC which provides a highly accurate, programmable out-
put voltage for all high-performance processors. Two
interleaved synchronous buck regulator phases with built-in
current sharing operate 180 out of phase to provide the fast
transient response needed to satisfy high current applications
while minimizing external components. The FAN5193 fea-
tures remote voltage sensing and Programmable Active
Droop
for 100nsec converter transient response with mini-
mum output capacitance. It has integrated high-current gate
drivers, with adaptive delay gate switching, eliminating the
need for external drive devices. The FAN5193 uses a 5-bit D/
A converter to program the output voltage from 1.10V to
1.85V in 25mV steps with an accuracy of 0.5%. The
FAN5193 uses a high level of integration to deliver load cur-
rents in excess of 50A from a 12V source with minimal
external circuitry. The FAN5193 also offers integrated func-
tions including Power Good, Output Enable/Soft Start,
under-voltage lockout,
over-voltage protection, and adjustable current limiting with
independent current sense on each phase. It is available in a
24 pin TSSOP package.
FAN5193
PRODUCT SPECIFICATION
2
REV. 1.0.1 2/4/02
Pin Assignments
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1-5
VID0-4
Voltage Identification Code Inputs.
These open collector/TTL compatible
inputs will program the output voltage over the ranges specified in Table 1.
6
BYPASS
5V Rail.
Bypass this pin with a 1
F ceramic capacitor to AGND.
7
AGND
Analog Ground.
Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
8
LDRVB
Low Side FET Driver for B.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should be <0.5
"
.
9
PGNDB
Power Ground B.
Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
10
SWB
High side driver source and low side driver drain switching node B.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
11
HDRVB
High Side FET Driver B.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should be <0.5
"
.
12
BOOTB
Bootstrap B.
Input supply for high-side MOSFET.
13
BOOTA
Bootstrap A.
Input supply for high-side MOSFET.
14
HDRVA
High Side FET Driver A.
Connect this pin to the gate of an N-channel MOSFET.
The trace from this pin to the MOSFET gate should be <0.5
"
.
15
SWA
High side driver source and low side driver drain switching node A.
Gate
drive return for high side MOSFET, and negative input for low-side MOSFET
current sense.
16
PGNDA
Power Ground A.
Return pin for high currents flowing in low-side MOSFET.
Connect directly to low-side MOSFET source.
17
LDRVA
Low Side FET Driver for A.
Connect this pin to the gate of an N-channel
MOSFET for synchronous operation. The trace from this pin to the MOSFET gate
should be <0.5
"
.
18
VCC
VCC.
Internal IC supply. Connect to system 12V supply, and decouple with a
0.1
F ceramic capacitor.
19
PWRGD
Power Good Flag.
An open collector output that will be logic LOW if the output
voltage is not within +10/-15% of the nominal output voltage setpoint.
20
ILIM
Current Limit.
A resistor from this pin to ground sets the over current trip level.
FAN5093
VID0
VID1
VID2
VID3
VID4
AGND
BYPASS
LDRVB
PGNDB
SWB
HDRVB
BOOTB
VFB
RT
ENABLE/SS
DROOP/E*
ILIM
PWRGD
VCC
LDRVA
PGNDA
SWA
HDRVA
BOOTA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PRODUCT SPECIFICATION
FAN5193
REV. 1.0.1 2/4/02
3
Absolute Maximum Ratings
Recommended Operating Conditions
21
DROOP/E*
Droop Control/Energy Star Mode Control.
A resistor from this pin to ground
sets the amount of droop by controlling the gain of the current sense amplifier.
When this pin is pulled high to BYPASS, the phase A drivers are turned off for
Energy-star operation.
22
ENABLE/SS
Output Enable/Softstart.
A logic LOW on this pin will disable the output. An
internal current source allows for open collector control. This pin also doubles as
soft start.
23
RT
Frequency Set.
A resistor from this pin to ground sets the switching frequency.
24
VFB
Voltage Feedback.
Connect to the desired regulation point at the output of the
converter.
Parameter
Min.
Typ.
Max.
Unit
Supply Voltage VCC
15
V
Supply Voltages BOOTA, BOOTB
22
V
Voltage Identification Code Inputs, VID0-VID4
6
V
VFB, ENABLE/SS, PWRGD, DROOP/E*
6
V
SWA, SWB
-3
15
V
PGNDA, PGNDB to AGND
-0.5
0.5
V
Gate Drive Current, peak pulse
3
A
Junction Temperature, T
J
-55
150
C
Storage Temperature
-65
150
C
Lead Soldering Temperature, 10 seconds
300
C
Power Dissipation, P
D
950
mW
Thermal Resistance Junction-to-Case,
JC
13
C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Output Driver Supply, BOOT
16
17
V
Input Logic HIGH
2.4
V
Input Logic LOW
0.8
V
Ambient Operating Temperature
0
70
C
Pin Number
Pin Name
Pin Function Description
FAN5193
PRODUCT SPECIFICATION
4
REV. 1.0.1 2/4/02
Electrical Specifications
(V
CC
= 12V,V
OUT
= 1.500V, and T
A
= +25C using circuit in Figure 1, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Parameter
Conditions
Min.
Typ.
Max.
Units
Output Voltage
See Table 1
1.100
1.850
V
Output Current
40
A
Internal Reference Voltage
1.4925
1.5000
1.5075
V
Initial Voltage Setpoint
I
LOAD
= 5A
1.485
1.500
1.515
V
Output Temperature Drift
T
A
= 0 to 70C
+5
mV
Line Regulation
V
CC
= 11.4V to 12.6V
+130
V
Droop
3
I
LOAD
= 0.8A to I
max
-90
-100
-110
mV
Programmable Droop Range
-10
0
%Vout
Total Output Variation,
Steady State
1
I
LOAD
= 0.8A to I
max
1.430
1.570
V
Total Output Variation, Transient
2
I
LOAD
= 0.8A to I
max
1.430
1.570
V
Response Time
V
out
= 10mV
100
nsec
Gate Drive On-Resistance
2.0
Upper Drive Low Voltage
V
HDRV
V
SW
at I
sink
= 10A
0.2
V
Upper Drive High Voltage
V
BOOT
V
HDRV
at I
source
= 10A
0.5
V
Lower Drive Low Voltage
I
sink
= 10A
0.2
V
Lower Drive High Voltage
V
CC
V
LDRV
at I
source
= 10A
0.5
V
Output Driver Rise & Fall Time
See Figure 3
20
nsec
Current Mismatch
R
DS,on
(A) = R
DS,on
(B), I
LOAD
= I
max
5
%
Output Overvoltage Detect
2.1
2.3
V
Efficiency
I
LOAD
= I
max
I
LOAD
= 2A (E*-mode)
85
70
%
Oscillator Frequency
RT = 41.2K
450
600
750
KHz
Oscillator Range
RT = 125K
to 12.5 K
200
2000
KHz
Maximum Duty Cycle
RT = 125K
90
%
Minimum LDRV on-time
RT = 12.5K
330
nsec
Input LOW current, VID pins
V
VID
= 0.4V
50
A
Soft Start Current
10
A
Enable Threshold
ON
OFF
0A
1.0
V
BYPASS Voltage
4.75
5
5.25
V
BYPASS Capacitor
100
nF
PWRGD Threshold
Logic LOW, minimum
Logic LOW, maximum
85
108
88
111
92
115
%V
out
PWRGD Hysteresis
20
mV
PWRGD Output Voltage
I
sink
= 4mA
0.4
V
PWRGD Delay
High
Low
500
sec
12V UVLO
8.5
9.5
10.5
V
UVLO Hysteresis
0.5
V
12V Supply Current
HDRV and LDRV Open
5
mA
Over Temperature Shutdown
150
C
Over Temperature Hysteresis
25
C
PRODUCT SPECIFICATION
FAN5193
REV. 1.0.1 2/4/02
5
Notes:
1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Output Ripple and Output Temperature Drift and is
measured at the converter's VFB sense point.
2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than
0.5m
trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal
performance.
3. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with Intel's
VRM 9.0 specification of +70, -70mV.
Table 1. Output Voltage Programming Codes
Note:
1. 0 = VID pin is tied to GND.
1 = VID pin is pulled up to 5V.
VID4
VID3
VID2
VID1
VID0
V
OUT
to CPU
1
1
1
1
1
OFF
1
1
1
1
0
1.100V
1
1
1
0
1
1.125V
1
1
1
0
0
1.150V
1
1
0
1
1
1.175V
1
1
0
1
0
1.200V
1
1
0
0
1
1.225V
1
1
0
0
0
1.250V
1
0
1
1
1
1.275V
1
0
1
1
0
1.300V
1
0
1
0
1
1.325V
1
0
1
0
0
1.350V
1
0
0
1
1
1.375V
1
0
0
1
0
1.400V
1
0
0
0
1
1.425V
1
0
0
0
0
1.450V
0
1
1
1
1
1.475V
0
1
1
1
0
1.500V
0
1
1
0
1
1.525V
0
1
1
0
0
1.550V
0
1
0
1
1
1.575V
0
1
0
1
0
1.600V
0
1
0
0
1
1.625V
0
1
0
0
0
1.650V
0
0
1
1
1
1.675V
0
0
1
1
0
1.700V
0
0
1
0
1
1.725V
0
0
1
0
0
1.750V
0
0
0
1
1
1.775V
0
0
0
1
0
1.800V
0
0
0
0
1
1.825V
0
0
0
0
0
1.850V
PDF 
ZIP