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Электронный компонент: FAN53168MTC

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www.fairchildsemi.com
REV. 1.0.0 6/9/03
Features
Precision Multi-Phase DC-DC Core Voltage Regulation
10mV Output Voltage Accuracy Over Temperature
Differential Remote Voltage Sensing
Selectable 2, 3, or 4 Phase Operation
Up to 1MHz per Phase Operation (4MHz ripple
Frequency)
Lossless Inductor Current Sensing for Loadline
Compensation
External Temperature Compensation
Accurate Load-Line Programming (Meets Intel
VRM/VRD10 CPU Specifications)
Accurate Channel-Current Balancing for Thermal
Optimization and Layout Compensation
Convenient 12V Supply Biasing
6-bit Voltage Identification (VID) Input
.8375V to 1.600V in 12.5mV Steps
Dynamic VID Capability with Fault-Blanking for
glitch-less Output voltage Changes
Adjustable Over Current Protection with Programmable
Latch-Off Delay
Over-Voltage Protection - Internal OVP Crowbar
Protection
Applications
Computer DC/DC Converter VRM/VRD10.0
Computer DC/DC Converter VRM/VRD9.X
High Current, Low Voltage DC/DC Rail
General Description
The FAN53168 is a multi-phase DC-DC controller for
implementing high-current, low-voltage, CPU core power
regulation circuits. It is part of a chipset that includes
external MOSFET drivers and power MOSFETS. The
FAN53168 drives up to 4 synchronous-rectified buck
channels in parallel. The multi-phase buck converter
architecture uses interleaved switching to multiply ripple
frequency by the number of phases and reduce input and
output ripple currents. Lower ripple results in fewer compo-
nents, lower component cost, reduced power dissipation, and
smaller board area.
The FAN53168 features a high bandwidth control loop to
provide optimal response to load transients. The FAN53168
senses current using lossless techniques: Phase current is
measured through each of the output inductors. This current
information is summed, averaged and used to set the loadline
of the output via programmable "droop". The droop is tem-
perature compensated to achieve precise loadline character-
istics over the entire operating range. Additionally,
individual phase current is measured using the R
DS-ON
of the
low-side MOSFET's. This information is used to dynami-
cally balance/steer per-phase current. The phase currents are
also summed and averaged for over-current detection.
Dynamic-VID technology allows on-the-fly VID changes
with controlled, glitch-less output. Additionally, short-circuit
protection, adjustable current limiting, over-voltage protec-
tion and power-good circuitry combine to ensure reliable and
safe operation. The operating temperature range is 0
o
C to
+85
o
C and the operating voltage is a single +12V supply,
simplifying design. The FAN53168 is available in a TSSOP-
28 package.
System Block Diagram
FAN53168
FAN53418
V
IN
FAN53418
V
IN
1
2
3
4
V
OUT
FAN53168
6-Bit VID Controlled 2-4 Phase DC-DC Controller
FAN53168
PRODUCT SPECIFICATION
2
REV. 1.0.0 6/9/03
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired.
Functional operation under these conditions is not implied.
Thermal Information
Recommended Operating Conditions
(See Figure 1)
Note:
1.
JA
is defined as 2 oz., 4 layer copper PCB with 1 in
2
thermal pad
Parameter
Min.
Max.
Units
Supply Voltage: VCC to GND
-0.3
+15
V
Voltage on FBRTN pin
-0.3
+0.3
V
Voltage on SW1-SW4
-5
+25
V
Voltage on VID [5:0], EN, DELAY, ILIMIT, CSCOMP, RT, PWM[4:1], COMP
-0.3
+5.5
V
Voltage on any other pin
-0.3
VCC+0.3
V
Parameter
Min.
Typ.
Max.
Units
Operating Junction Temperature (T
J
)
+125
C
Storage Temperature
-65
+150
C
Lead Soldering Temperature, 10 seconds
+300
C
Vapor Phase, 60 seconds
+215
C
Infrared, 15 seconds
+220
C
Power Dissipation (P
D
) @ T
A
= 25C
1
W
Thermal Resistance (
JA
)*
100
C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage VCC
VCC to GND
10.8
12
13.2
V
Ambient Operating Temperature
0
+85
C
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
3
Pin Configuration
Pin Definitions
Pin
Number Pin Name
Pin Function Description
16
VID[4:0],
VID5
VID Inputs.
Determines the output voltage via the internal DAC. These inputs are
compliant to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups so leaving them open results in logic high. Leaving VID[4:0] open results
in a "No CPU" condition disabling the PWM outputs.
7
FBRTN
Feedback Return.
Error Amp and DAC reference point.
8
FB
Feedback Input.
Inverting input for Error Amp this pin is used for external compensation.
Can also be used to introduce DC offset voltage to the output.
9
COMP
Error Amp Output.
This pin is used for external compensation.
10
PWRGD
Power Good Output.
This is an open-drain output that asserts when the output voltage is
within the specified tolerance. It is expected to be pulled up to an external voltage rail.
11
EN
Output Enable.
This is a dual-function pin. It allows for an external open-drain drain logic
signal to enable the output PWM.
12
DELAY
Soft-start and Current Limit Delay.
An external resistor and capacitor sets the soft-start
ramp rate and the over-current latch off delay.
13
RT
Switching Frequency Adjust.
This pin adjusts the output PWM switching frequency via
an external resistor.
14
RAMPADJ
PWM Current Ramp Adjust.
An external resistor to Vcc will adjust the amplitude of the
internal PWM ramp.
15
ILIMIT
Current Limit Adjust.
An external resistor sets the current limit threshold for the regulator
circuit. This pin is internally pulled low when EN is low or the UVLO circuit is active.
16
CSREF
Current Sense Return.
Inverting input of the current sense amp. Sense point for the
output voltage used for OVP, and PWRGD.
17
CSSUM
Current Sense Summing node.
Non-inverting input of the current sense amp.
18
CSCOMP
Current Sense Compensation node.
Output of the current sense amplifier. This pin is
used for droop compensation, a current loop reponse.
19
GND
Analog Chip Ground.
Signal ground for the chip
2023
SW[4:1]
Phase Current Sense/Balance inputs.
Phase-to-phase current sense and balancing
inputs. Unused phases should be left open.
2427
PWM[4:1]
PWM Outputs.
CMOS outputs for driving external gate drivers such as the FAN53418.
Unused phases should be grounded.
28
VCC
Chip Power.
Bias supply for the chip. Connect directly to a +12V supply. Bypass with a
1
F MLCC capacitor.
DELAY
VID4
VID3
VID2
VID1
VID0
VID5
COMP
CSCOMP
PWRGD
EN
CSSUM
RT
VCC
SW2
SW3
PWM3
PWM4
PWM1
GND
FBRTN
ILIMIT
FB
CSREF
RAMPADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FAN53168
TSSOP-28
SW1
PWM2
SW4
FAN53168
PRODUCT SPECIFICATION
4
REV. 1.0.0 6/9/03
Electrical Specifications
1
(Vcc = 12V, T
A
= 0
C to +85
C and FBRTN = GND, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design NOT tested in production.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Error Amplifier
Output Voltage Range
V
COMP
0.5
3.5
V
Accuracy
V
FB
Relative to Nominal DAC Output,
Referenced to FBRTN, CSSUM =
CSCOMP, Figure 3
-10
+10
mV
Line Regulation
V
FB
VCC = 10V to 14V
0.05
%
Input Bias Current
I
FB
13
15
17
A
FBRTN Current
I
FBRTN
90
120
A
Output Current
I
O(ERR)
FB forced to V
OUT
-3%
500
A
Gain Bandwidth Product
GBW
(ERR)
COMP = FB
20
MHz
Slew Rate
C
COMP
= 10pF
50
V/
s
VID Inputs
Input Low Voltage
V
IL(VID)
0.4
V
Input High Voltage
V
IH(VID)
0.8
V
Input Current, VID Low
I
IL(VID)
VID(X) = 0V
-30
-20
A
Input Current, VID High
I
IH(VID)
VID(X) = 1.25V
15
25
A
Pull-up Resistance
R
VID
60
k
Internal Pull-up Voltage
0.825
1.00
V
VID Transition Delay
Time
2
VID Code Change to FB Change
400
ns
"No CPU" Detection
Turn-off Delay Time
2
VID Code Change to 11111 to PWM
going low
400
ns
Oscillator
Frequency
2
f
OSC
250
4000
kHz
Frequency Variation
f
PHASE
T
A
= +25C, R
T
= 250k
, 4-Phase
T
A
= +25C, R
T
= 115k
, 4-Phase
T
A
= +25C, R
T
= 75k
, 4-Phase
155
200
400
600
245
kHz
kHz
kHz
Output Voltage
V
RT
R
T
= 100k
to GND
1.9
2.0
2.1
V
RAMPADJ Output Voltage V
RAMPADJ
RAMPADJ-FB
-50
+50
mV
RAMPADJ Input Current
Range
I
RAMPADJ
0
100
A
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
5
Electrical Specifications
1
(Vcc = 12V, T
A
= 0
C to +85C and FBRTN = GND, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design NOT tested in production.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Current Sense Amplifier
Offset Voltage
V
OS(CSA)
CSSUM-CSREF, Test Circuit 1
-1.5
+1.5
mV
Input Bias Current
I
BIAS(CSA)
-50
+50
nA
Gain Bandwidth Product
GBW
(ERR)
COMP = FB
20
MHz
Slew Rate
C
COMP
= 10pF
50
V/
s
Input Common Mode
Range
CSSUM and CSREF
0
3
V
Positioning Accuracy
V
FB
COMP = FB, Test Circuit 2
-83
-80
-77
mV
Output Voltage Range
I
CSCOMP
= 100
A
0.05
3.3
V
Output Current
I
O(ERR)
FB forced to V
OUT
3%
500
A
Current Balance Circuit
Common Mode Range
V
SW(X)CM
-600
+200
mV
Input Resistance
R
SW(X)
SW(X) = 0V
20
30
40
k
Input Current
I
SW(X)
SW(X) = 0V
4
7
10
A
Input Current Matching
I
SW(X)
SW(X) = 0V
-5
+5
%
Current Limit Comparator
ILIMIT Output Voltage
Normal Mode
In Shutdown
V
ILIMIT(NM)
V
ILIMIT(SD)
EN > 0.8V, R
ILIMIT
= 250k
EN < 0.4V, I
ILIMIT
= -100
A
2.9
3
3.1
400
V
mV
Output Current, Normal
Mode
I
ILIMIT(NM)
EN > 0.8V, R
ILIMIT
= 250k
12
A
Maximum Output Current
EN > 0.8V
60
A
Current Limit Threshold
Voltage
V
CL
V
CSREF
-V
CSCOMP
, R
ILIMIT
= 250k
105
125
145
mV
Current Limit Setting Ratio
V
CL
/I
ILIMIT
10.4
mV/
A
Latch-off Delay Threshold
V
DELAY
In Current Limit
1.7
1.8
1.9
V
Latch-off Delay Time
t
DELAY
R
DELAY
= 250k
, C
DELAY
= 4.7nF
600
s
Soft Start
Output Current, Softstart
Mode
I
DELAY(SS)
During Start-up, DELAY < 2.8 V
15
20
25
A
Soft Start Delay Time
T
DELAY(SS)
R
DELAY
= 250k
, C
DELAY
= 4.7nF,
VID[5:0] = 011111
350
s
Enable Input
Input Low Voltage
V
IL(EN)
0.4
V
Input High Voltage
V
IH(EN)
0.8
V
Input Current, EN Low
I
IL(EN)
EN = 0V
-1
1
A
Input Current, EN High
I
IH(EN)
EN = 1.25V
10
25
A
FAN53168
PRODUCT SPECIFICATION
6
REV. 1.0.0 6/9/03
Electrical Specifications
1
(Vcc = 12V, T
A
= 0
C to +85C and FBRTN = GND, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design NOT tested in production.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Power Good Comparator
Undervoltage Threshold
V
PWRGD(UV)
Relative to Nominal DAC Output
-325
-250
-200
mV
Overvoltage Threshold
V
PWRGD(OV)
Relative to Nominal DAC Output
90
150
200
mV
Output Low Voltage
V
OL(PWRGD)
I
PWRGD(SINK)
= 4mA
225
400
mV
Power Good Delay Time
VID Code Changing
VID Code Static
100
250
200
s
ns
Crowbar Trip Point
V
CROWBAR
Relative to Nominal DAC Output
90
150
200
mV
Crowbar Reset Point
Relative to FBRTN
450
550
650
mV
Crowbar Delay Time
VID Code Changing
VID Code Static
t
CROWBAR
Overvoltage to PWM Going Low
100
250
400
s
ns
PWM Outputs
Output Voltage Low
V
OL(PWM)
I
PWM(SINK)
= 400
A
160
500
mV
Output Voltage High
V
OH(PWM)
I
PWM(SOURCE)
= 400
A
4
5
V
Input Supply
DC Supply Current
EN = Logic High
5
8
mA
UVLO Threshold
V
UVLO
Vcc Rising (Vcc = 12V input)
6.5
6.9
7.3
V
UVLO Hyteresis
0.7
0.9
1.1
V
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
7
Internal Block Diagram
Phase
Current
Balancing
Circuit
VID
DAC
REF
Current
Limit
Circuit
Oscillator
UVLO
SHUTDOWN
& BIAS
11
Delay
28
19
14
13
Soft
Start
2/3/4 Phase Driver
Logic
EN
RESET
RESET
RESET
RESET
SET
CURRENT
LIMIT
CROWBAR
12
CMP
CMP
CMP
CMP
CMP
CMP
CSA
Error
Amp
24
25
26
27
20
21
22
23
-
15
7
6
5
4
3
2
1
18
16
17
10
EN
DAC
+150mV
DAC
-250mV
8
9
DELAY
VID4
VID3
VID2
VID1
VID0
VID5
COMP
PWRGD
EN
RT
FBRTN
FB
RAMPADJ
CSCOMP
CSSUM
VCC
SW2
SW3
PWM3
PWM4
PWM1
GND
ILIMIT
CSREF
SW1
PWM2
SW4
CSREF
FAN53168
PRODUCT SPECIFICATION
8
REV. 1.0.0 6/9/03
Typical Characteristics
TPC 1. Master Clock Frequency
TPC 2. Supply Current vs. Master Clock Frequency
4
0
50
100
150
RT VALUE k
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPH
200
250
300
3
2
MASTER CLOCK FREQUENCY
MHz
1
0
5.3
0
0.5
1.0
1.5
MASTER CLOCK FREQUENCY MHz
2.0
2.5
3.0
3.5
4.0
5.0
5.1
5.2
4.8
4.9
SUUPLY CURRENT
mA
4.7
4.6
T
A
= 25
C
4-PHASE OPERATION
Test Circuits
Test Circuit 1 Current Sense Amplifier V
OS
Test Circuit 2 Output Voltage Positioning
Test Circuit 3 Closed Loop Output Voltage Accuracy
VCC
28
18
19
17
16
CSREF
CSSUM
CSCOMP
GND
CSA
100nF
39k
1k
1V
+12V
40
1V
CSCOMP
V
OS
=
VCC
28
18
19
17
16
CSREF
CSSUM
CSCOMP
GND
CSA
100nF
200k
1V
+12V
9
8
10k
FB
COMP
200k
V
mV
V
mV
V
FB
FB
FB
V
0
80
=
=
=
VID4
VID0
VID1
VID2
VID3
VID5
FAN53168
VCC
1
VID4
8
11
10
9
12
14
13
6
5
4
7
3
2
28
21
18
19
20
17
15
16
23
24
25
22
26
27
RAMPADJ
RT
DELAY
EN
PWRGD
COMP
FB
FBRTN
VID5
VID0
VID1
VID2
VID3
ILIMIT
CSREF
CSSUM
CSCOMP
GND
SW4
SW3
SW2
SW1
PWM4
PWM3
PWM2
PWM1
250k
100nF
4.7nF
250k
20k
1
F
100nF
+12V
1k
1.25V
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
9
Application Circuit
+1
2V
U1 FAN53418
4
6
2
3
8
1
5
7
DR
VH
VC
C
PG
ND
B
S
T
SW
DR
V
L
PW
M
OD
U4 FAN53168
VC
C
1V
I
D
4
8
11
10
9
12
14
13
6
5
4
7
3
2
28
21
18
19
20
17
15
16
23
24
25
22
26
27
RAMPAD
J
RT
DEL
AY
EN
PW
RG
D
COM
P
FB
FB
RTN
VID
5
VID
0
VID
1
VID
2
VID
3
IL
IM
IT
CS
RE
F
CS
S
U
M
CSC
O
M
P
GND
SW
4
SW
3
SW
2
SW
1
PW
M
4
PW
M
3
PW
M
2
PW
M
1
D1
Q4
L1
Q5
Q1
C
X
V
cc C
O
R
E
0.
8
375
V
-

1.
600
V
60A
D
C
/
7
4 A
P
eak
C
IN
+
12V
C
DLY
R
TH
*
R
T
R
DLY
C
FB
R
A
C
A
R
B
C
B
C
CS
R
CS
1
R
SW
1
R
SW
3
R
SW
2
R
CS
2
R
PH
1
R
PH
2
R
PH
3
C1
C4
C8
R1
9
C1
2
4
6
2
3
8
1
5
7
DR
VH
VC
C
PG
ND
B
S
T
SW
DR
V
L
PW
M
OD
D2
Q6
L2
Q7
Q2
+
12V
C2
C5
C9
R2
0
C1
3
4
6
2
3
8
1
5
7
DR
VH
VC
C
PG
ND
B
S
T
SW
DR
V
L
PW
M
OD
D3
Q8
L3
Q9
Q3
+
12V
C3
C6
C1
0
R2
1
C1
4
R
LI
M
C7
R
R
R1
R5
L4
V
IN
V
IN
V
IN
PW
RG
D
EN
C
Z
R4
U2 FAN53418
U3 FAN53418
Figure 1. Typical Application
3-phase, 65A (DC), 74A (Peak) VRD/VRM10 Design
FAN53168
PRODUCT SPECIFICATION
10
REV. 1.0.0 6/9/03
Bill of Materials
Table 1. FAN53168 VRM/VRD10 Application Bill of Materials for Figure 1
Reference
Qty
Description
Manufacturer/Number
U4
1
VRM10, Multi-Phase Controller
Fairchild FAN53168
U1-3
3
Sync MOSFET Driver, 12V/12V
Fairchild FAN53418
Q1-3
3
N-MOSFET, 30V, 50A, 8m
Fairchild FDD6696
Q4-9
6
N-MOSFET, 30V, 75A, 5m
Fairchild FDD6682
D1-3
3
Diode, 100V, 200mA, SOD123
Fairchild MMSD4148
L1-3
3
Inductor, 550nH, 28A, 2.4m
Micrometals T50-2, 10T, 16AWG
L4
1
Inductor, 630nH, 15A, 1.7m
Inter-Technical AK1418160052A-R63M
R1
1
10
, 5%
R
R
R
DLY
, R
T
3
301k
, 1%
R5
1
15.0k
, 1%
R4, R
PH1-3
4
100k
, 1%
R
A
, R
CS2
2
24.9k
, 1%
R
B
1
1.33k
, 1%
R
SW1-3
3
0
, 5%
R
CS1
1
37.4k
, 1%
R
LIM
1
200k
, 1%
R19-21
3
1.5
, 5%
R
TH
1
NTC Thermistor, 100k
, 5%
Panasonic ERT-J1V V104J
C1-7
7
1.0f, 25V, 10% X7R
C8-10
3
0.1f, 50V, 10% X7R
C12-14, C
CS
4
4700pF, 25V, 10% X7R
C
DLY
1
0.047f, 25V, 10% X7R
C
B
1
2200pF, 25V, 10% X7R
C
A
1
470pF, 50V, 10% X7R
C
FB
1
100pF, 50V, 5% NPO
C
X
8
820F, 2.5V, 20% 7m
, POLY
Fujitsu FP-2R5RE821M
C
Z
22
10F, 6.3V, 20% X5R
C
IN
6
470f, 16V, 20%, 36m
, Alum-Electrolytic
Rubycon 16MBZ470M
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
11
Table 2. VID Codes
VID4
VID3
VID2
VID1
VID0
VID5
V
OUT
(nominal)
1
1
1
1
1
X
No CPU
0
1
0
1
0
0
0.8375 V
0
1
0
0
1
1
0.850 V
0
1
0
0
1
0
0.8625 V
0
1
0
0
0
1
0.875 V
0
1
0
0
0
0
0.8875 V
0
0
1
1
1
1
0.900 V
0
0
1
1
1
0
0.9125 V
0
0
1
1
0
1
0.925 V
0
0
1
1
0
0
0.9375 V
0
0
1
0
1
1
0.950 V
0
0
1
0
1
0
0.9625 V
0
0
1
0
0
1
0.975 V
0
0
1
0
0
0
0.9875 V
0
0
0
1
1
1
1.000 V
0
0
0
1
1
0
1.0125 V
0
0
0
1
0
1
1.025 V
0
0
0
1
0
0
1.0375 V
0
0
0
0
1
1
1.050 V
0
0
0
0
1
0
1.0625 V
0
0
0
0
0
1
1.075 V
0
0
0
0
0
0
1.0875 V
1
1
1
1
0
1
1.100 V
1
1
1
1
0
0
1.1125 V
1
1
1
0
1
1
1.125 V
1
1
1
0
1
0
1.1375 V
1
1
1
0
0
1
1.150 V
1
1
1
0
0
0
1.1625 V
1
1
0
1
1
1
1.175 V
1
1
0
1
1
0
1.1875 V
1
1
0
1
0
1
1.200 V
1
1
0
1
0
0
1.2125 V
1
1
0
0
1
1
1.225 V
1
1
0
0
1
0
1.2375 V
1
1
0
0
0
1
1.250 V
1
1
0
0
0
0
1.2625 V
1
0
1
1
1
1
1.275 V
1
0
1
1
1
0
1.2875 V
1
0
1
1
0
1
1.300 V
1
0
1
1
0
0
1.3125 V
1
0
1
0
1
1
1.325 V
FAN53168
PRODUCT SPECIFICATION
12
REV. 1.0.0 6/9/03
1
0
1
0
1
0
1.3375 V
1
0
1
0
0
1
1.350 V
1
0
1
0
0
0
1.3625 V
1
0
0
1
1
1
1.375 V
1
0
0
1
1
0
1.3875 V
1
0
0
1
0
1
1.400 V
1
0
0
1
0
0
1.4125 V
1
0
0
0
1
1
1.425 V
1
0
0
0
1
0
1.4375 V
1
0
0
0
0
1
1.450 V
1
0
0
0
0
0
1.4625 V
0
1
1
1
1
1
1.475 V
0
1
1
1
1
0
1.4875 V
0
1
1
1
0
1
1.500 V
0
1
1
1
0
0
1.5125 V
0
1
1
0
1
1
1.525 V
0
1
1
0
1
0
1.5375 V
0
1
1
0
0
1
1.550 V
0
1
1
0
0
0
1.5625 V
0
1
0
1
1
1
1.575 V
0
1
0
1
1
0
1.5875 V
0
1
0
1
0
1
1.600 V
Table 2. VID Codes
(continued)
VID4
VID3
VID2
VID1
VID0
VID5
V
OUT
(nominal)
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
13
General Description and Applications Information
Theory of Operation
The FAN53168 combines a multi-mode, fixed frequency
PWM control with multi-phase logic outputs for use in 2, 3
and 4 phase synchronous buck CPU core supply power con-
verters. The internal 6-bit VID DAC conforms to Intel's
VRD/VRM 10 specifications. Multi-phase operation is
important for producing the high currents and low voltages
demanded by today's microprocessors. Handling the high
currents in a single-phase converter would place high ther-
mal demands on the components in the system such as the
inductors and MOSFETs.
The multi-mode control of the FAN53168 ensures a stable,
high performance topology for:
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
Minimizing thermal switching losses due to lower
frequency operation
Tight load line regulation and accuracy
High current output from having up to 4 phase operation
Reduced output ripple due to multi-phase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
Flexibility in operation for tailoring design to low cost or
high performance
Number of Phases
The number of operational phases and their phase relation-
ship is determined by internal circuitry which monitors the
PWM outputs. Normally, the FAN53168 operates as a 4-
phase PWM controller. Grounding the PWM4 pin programs
3-phase operation, and grounding the PWM3 and PWM4
pins programs 2-phase operation.
When the FAN53168 is enabled, the controller outputs a
voltage on PWM3 and PWM4 that is approximately 550 mV.
An internal comparator checks each pin's voltage versus a
threshold of 400mV. If the pin is grounded, then it will be
below the threshold and the phase will be disabled. The out-
put impedance of the PWM pin is approximately 5k
. Any
external pull-down resistance connected to the PWM pin
should not be less than 25k
to ensure proper operation. The
phase detection is made during the first 2 clock cycles of the
internal oscillator. After this time, if the PWM output was
not grounded, then it will switch between 0V and 5V. If the
PWM output was grounded, then it will remain off.
The PWM outputs become logic-level devices once normal
operation starts. The detection is normal and is intended for
driving external gate drivers, such as the FAN53418. Since
each phase is monitored independently, operation approach-
ing 100% duty cycle is possible. Also, more than one output
can be on at a time for overlapping phases.
Master Clock Frequency
The clock frequency of the FAN53168 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in TPC 1. To determine the frequency per
phase, the clock is divided by the number of phases in use.
If PWM4 is grounded, then divide the master clock by 3 for
the frequency of the remaining phases. If PWM3 and 4 are
grounded, then divide by 2. If all phases are in use, divide
by 4.
Output Voltage Differential Sensing
The FAN53168 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error
amplifier to maintain a worst-case specification of 10 mV
differential sensing error with a VID input of 1.6000 V over
its full operating output voltage and temperature range. The
output voltage is sensed between the FB and FBRTN pins.
FB should be connected through a resistor to the regulation
point, usually the remote sense pin of the microprocessor.
FBRTN should be connected directly to the remote sense
ground point. The internal VID DAC and precision reference
are referenced to FBRTN, which has a minimal current of
90A to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
Output Current Sensing
The FAN53168 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detec-
tion. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method then peak current detection
or sampling the current across a sense element such as the
low side MOSFET. This amplifier can be configured several
ways depending on the objectives of the system:
Output inductor ESR sensing without thermistor for
lowest cost
Output inductor ESR sensing with thermistor for
improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF
pin, which is connected to the output voltage. The inputs to
the amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback
resistor between CSCOMP and CSSUM sets the gain of the
amplifier, and a filter capacitor is placed in parallel with this
resistor. The gain of the amplifier is programmable by adjust-
ing the feedback resistor to set the load line required by the
microprocessor. The current information is then given as the
difference of CSREF CSCOMP. This difference signal is
used internally to offset the VID DAC for voltage positioning
and as a differential input for the current limit comparator.
FAN53168
PRODUCT SPECIFICATION
14
REV. 1.0.0 6/9/03
To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage.
Also, the sensing gain is determined by external resistors so
that it can be made extremely accurate.
Active Impedance Control Mode
For controlling the dynamic output voltage droop as a func-
tion of output current, a signal proportional to the total out-
put current at the CSCOMP pin can be scaled to be equal to
the droop impedance of the regulator times the output cur-
rent. This droop voltage is then used to set the input control
voltage to the system. The droop voltage is subtracted from
the DAC reference input voltage directly to tell the error
amplifier where the output voltage should be. This differs
from previous implementations and allows enhanced feed-
forward response.
Current Control Mode and Thermal Balance
The FAN53168 has individual inputs for each phase which
are used for monitoring the current in each phase. This infor-
mation is combined with an internal ramp to create a current
balancing feedback system that has been optimized for initial
current balance accuracy and dynamic thermal balancing
during operation. This current balance information is inde-
pendent of the average output current information used for
positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It is also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal
PWM ramp. Detailed information about programming the
ramp is given in the applications section.
External resistors can be placed in series with individual
phases to create an intentional current imbalance if desired,
such as when one phase may have better cooling and can
support higher currents. Resistors R
SW1
through R
SW4
(see
the typical application circuit in Figure 1) can be used for
adjusting thermal balance. It is best to have the ability to add
these resistors during the initial design, so make sure place-
holders are provided in the layout.
To increase the current in any given phase, make R
SW
for
that phase larger (make R
SW
= 0 for the hottest phase and do
not change during balancing). Increasing R
SW
to only 500
will make a substantial increase in phase current. Increase
each R
SW
value by small amounts to achieve balance, start-
ing with the coolest phase first.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used
for the voltage-mode control loop. The control input voltage
to the positive input is set via the VID 6-bit logic code
according to the voltages listed in Table 1. This voltage is
also offset by the droop voltage for active positioning of the
output voltage as a function of current, commonly known as
active voltage positioning. The output of the amplifier is the
COMP pin, which sets the termination voltage for the inter-
nal PWM ramps.
The negative input (FB) is tied to the output sense location
with a resistor R
B
and is used for sensing and controlling the
output voltage at this point. A current source from the FB pin
flowing through R
B
is used for setting the no-load offset
voltage from the VID voltage. The no-load voltage will be
negative with respect to the VID DAC. The main loop com-
pensation is incorporated in the feedback network between
FB and COMP.
Soft-start
The power-on ramp up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current
limit latch off time as explained in the following section. In
UVLO or when EN is a logic low, the DELAY pin is held at
ground. After the UVLO threshold is reached and EN is a
logic high, the DELAY cap is charged up with an internal
20A current source. The output voltage follows the ramp-
ing voltage on the DELAY pin, limiting the inrush current.
The soft-start time depends on the value of VID DAC and
C
DLY
, with a secondary effect from R
DLY
. Refer to the appli-
cations section for detailed information on setting C
DLY
.
When the PWRGD threshold is reached, the soft-start cycle
is stopped and the DELAY pin is pulled up to 3V. This
ensures that the output voltage is at the VID voltage when
the PWRGD signals to the system that the output voltage is
good. If EN is taken low or VCC drops below UVLO, the
DELAY cap is reset to ground to be ready for another soft
start cycle. Figure 2 shows a typical start-up sequence for the
FAN53168.
Current Limit, Short Circuit and Latch-off
Protection
The FAN53168 compares a programmable current limit set
point to the voltage from the output of the current senseam-
plifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the volt-
age on ILIMIT is 3V. The current through the external resis-
tor is internally scaled to give a current limit threshold of
10.4mV/A. If the difference in voltage between CSREF
and CSCOMP rises above the current limit threshold, the
internal current limit amplifier will control the internal
COMP voltage to maintain the average output current at
the limit.
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
15
Figure 2. Start-Up Waveforms, Circuit of Figure 1
Channel 1 PWRGD
Channel 2 V
OUT
Channel 3 HS MOSFET V
GS
Channel 4 LS MOSFET V
GS
After the limit is reached, the 3V pull-up on the DELAY pin
is disconnected, and the external delay capacitor is dis-
charged through the external resistor. A comparator monitors
the DELAY voltage and shuts off the controller when the
voltage drops below 1.8V. The current limit latch off delay
time is therefore set by the RC time constant discharging
from 3V to 1.8V. The applications section discusses the
selection of C
DLY
and R
DLY
.
Because the controller continues to cycle the phases during
the latch-off delay time, if the short is removed before the
1.8V threshold is reached, the controller will return to nor-
mal operation. The recovery characteristic depends on the
state of PWRGD. If the output voltage is within the PWRGD
window, the controller resumes normal operation. However,
if short circuit has caused the output voltage to drop below
the PWRGD threshold, then a soft-start cycle is initiated.
The latch-off function can be reset by either removing and reap-
plying VCC to the FAN53168, or by pulling the EN pin low for
a short time. To disable the short circuit latchoff function, the
external resistor to ground should be left open, and a large
(greater than 1M
) resistor should be connected from VCC to
DELAY. This prevents the DELAY capacitor from discharging
so the 1.8V threshold is never reached. The resistor will have an
impact on the soft-start time because the current through it will
add to the internal 20A current source.
During start-up when the output voltage is below 200mV, a
secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit controls the internal COMP
voltage to the PWM comparators to 2V. This will limit the
voltage drop across the low side MOSFETs through the
current balance circuitry.
Figure 3. Overcurrent Latch Off Waveform,
Circuit of Figure 1
Channel 1 PWRGD
Channel 2 V
OUT
Channel 3 CSCOMP
Channel 4 HS MOSFET V
GS
There is also an inherent per phase current limit that will
protect individual phases in the case where one or more
phases may stop functioning because of a faulty component.
This limit is based on the maximum normal-mode COMP
voltage.
Dynamic VID
The FAN53168 incorporates the ability to dynamically
change the VID input while the controller is running. This
allows the output voltage to change while the supply is run-
ning and supplying current to the load. This is commonly
referred to as VID-on-the-fly (OTF). A VID-OTF can occur
under either light load or heavy load conditions. The proces-
sor signals the controller by changing the VID inputs in mul-
tiple steps from the start code to the finish code. This change
can be either positive or negative.
When a VID input changes state, the FAN53168 detects the
change and ignores the DAC inputs for a minimum of 400ns.
This time is to prevent a false code due to logic skew while
the six VID inputs are changing. Additionally, the first VID
change initiates the PWRGD and CROWBAR blanking
functions for a minimum of 250s to prevent a false
PWRGD or CROWBAR event. Each VID change will
reset the internal timer. Figure 4 shows VID on-the-fly
performance when the output voltage is stepping up and the
output current is switching between minimum and maximum
values, which is the worst-case situation.
FAN53168
PRODUCT SPECIFICATION
16
REV. 1.0.0 6/9/03
Figure 4. VID On-the-Fly Waveforms, Circuit of Figure 1,
VID Change = 5mV, 5s, 50 steps,
I
OUT
Change = 5A to 65A
Power Good Monitoring
The Power Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the nominal limits
specified in the specifications above based on the VID volt-
age setting. PWRGD will go low if the output voltage is out-
side of this specified range. PWRGD is blanked during a
VID OTF event for a period of 250s to prevent false signals
during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output voltage exceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 450mV.
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high side MOSFET, this
action will current limit the input supply or blow its fuse,
protecting the microprocessor from destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the FAN53168 to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN53168 is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be con-
nected to the OD# pins of the FAN53418 drivers. Because
ILIMIT is grounded, this disables the drivers such that both
DRVH and DRVL are grounded. This feature is important to
prevent discharging of the output capacitors when the
controller is shut off. If the driver outputs were not disabled,
then a negative voltage could be generated on the output due
to the high current discharge of the output capacitors through
the inductors.
APPLICATION INFORMATION
The design parameters for a typical Intel VRD10-compliant
CPU application are as follows:
Input voltage (V
IN
) = 12 V
VID setting voltage (V
VID
) = 1.500 V
Duty cycle (D) = 0.125
Nominal output voltage at no load (V
ONL
) = 1.480 V
Nominal output voltage at 65 A load (V
OFL
) = 1.3955 V
Static output voltage drop based on a 1.3 m
load line
(R
O
) from no load to full load
(V
D
) = V
ONL
V
OFL
= 1.480 V 1.3955 V = 84.5 mV
Maximum Output Current (I
O
) = 65 A
Maximum Output Current Step (
I
O
) = 60A
Number of Phases (n) = 3
Switching frequency per phase (f
SW
) = 228 kHz
Setting the Clock Frequency
The FAN53168 uses a fixed-frequency control architecture.
The frequency is set by an external timing resistor (R
T
).
The clock frequency and the number of phases determine the
switching frequency per phase, which relates directly to
switching losses and the sizes of the inductors and input
and output capacitors. With n = 3 for three phases, a clock
frequency of 684kHz sets the switching frequency of each
phase, f
SW
, to 228kHz, which represents a practical trade-off
between the switching losses and the sizes of the output filter
components. TPC 1 shows that to achieve a 684kHz oscilla-
tor frequency, the correct value for R
T
is 301k
. Alterna-
tively, the value for R
T
can be calculated using:
where 5.83pF and 1.5M
are internal IC component
values. For good initial accuracy and frequency stability,
it is recommended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay Times
Because the soft-start and current limit latch off delay
functions share the DELAY pin, these two parameters must
be considered together. The first step is to set C
DLY
for the
soft-start ramp. This ramp is generated with a 20A internal
current source. The value of R
DLY
will have a second order
impact on the soft-start time because it sinks part of the
current source to ground. However, as long as R
DLY
is kept
greater than 200k
, this effect is minor. The value for C
DLY
can be approximated using:
R
T
1
n
f
SW
5.83pF
(
)
1
1.5M
------------------
--------------------------------------------------------------------------
=
(1)
C
DLY
20
A
V
VID
2
R
DLY
-----------------------
t
SS
V
VID
------------
=
(2)
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
17
Where t
SS
is the desired soft-start time. Assuming an R
DLY
of
301k
and a desired soft-start time of 3ms, C
DLY
is 35nF. A close
standard value for C
DLY
is 47nF. Once C
DLY
has been chosen,
R
DLY
can be calculated for the current limit latch-off time using:
If the result for R
DLY
is less than 200k
, then a smaller soft-
start time should be considered by recalculating the equation
for C
DLY
or a longer latch-off time should be used. In no
case should R
DLY
be less than 200k
. In this example, a
delay time of 8ms gives R
DLY
= 334k
. A close standard 1%
value is 301k
.
Inductor Selection
The choice of inductance for the inductor determines the
ripple current in the inductor. Less inductance leads to more
ripple current, which increases the output ripple voltage and
conduction losses in the MOSFETs, but allows using
smaller-size inductors and, for a specified peak-to-peak
transient deviation, less total output capacitance. Conversely,
a higher inductance means lower ripple current and reduced
conduction losses, but requires larger-size inductors and
more output capacitance for the same peak-to-peak transient
deviation. In any multi-phase converter, a practical value for
the peak-to-peak inductor ripple current is less than 50% of
the maximum DC current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator
frequency, and peak-to-peak ripple current in the inductor.
Equation 5 can be used to determine the minimum induc-
tance based on a given output ripple voltage:
Solving Equation 5 for a 10 mV
p-p
output ripple voltage
yields:
If the ripple voltage ends up less than that designed for, the
inductor can be made smaller until the ripple value is met.
This will allow optimal transient response and minimum
output decoupling.
The smallest possible inductor should be used to minimize
the number of output capacitors. Choosing a 650nH inductor
is a good choice for a starting point and gives a calculated
ripple current of 8.86A. The inductor should not saturate at
the peak current of 26.1A and should be able to handle the
sum of the power dissipation caused by the average current
of 21.7A in the winding and core loss.
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
will cause excessive power losses, while too small a value
will lead to increased measurement error. A good rule of
thumb is to have the DCR be about 1 to 1.5 times the droop
resistance (R
O
). For our example, we are using an inductor
with a DCR of 1.6 m
.
Designing an Inductor
Once the inductance and DCR are known, the next step is
either to design an inductor or find a standard inductor that
comes as close as possible to meeting the overall design
goals. It is also important to have the inductance and DCR
tolerance specified to keep the accuracy of the system
controlled. Using 15% for the inductance and 8% for the
DCR (at room temperature) are reasonable tolerances that
most manufacturers can meet.
The first decision in designing the inductor is to choose the
core material. There are several possibilities for providing
low core loss at high frequencies. Two examples are the
powder cores (e.g., Kool-M
from Magnetics, Inc. or
Micrometals) and the gapped soft ferrite cores (e.g., 3F3
or 3F4 from Philips). Low frequency powdered iron cores
should be avoided due to their high core loss, especially
when the inductor value is relatively low and the ripple
current is high.
The best choice for a core geometry is a closed-loop types,
such as pot cores, PQ, U, and E cores, or toroids. A good
compromise between price and performance are cores with a
toroidal shape.
There are many useful references for quickly designing a
power inductor, such as:
Magnetics Design References
1.
Magnetic Designer Software
Intusoft (www.intusoft.com)
2.
Designing Magnetic Components for High-Frequency
DC-DC Converters, by William T. McLyman, Kg Mag-
netics, Inc. ISBN 1883107008
Selecting a Standard Inductor
The companies listed below can provide design consultation
and deliver power inductors optimized for high power appli-
cations upon request.
Power Inductor Manufacturers
Coilcraft
(847) 639-6400
www.coilcraft.com
Coiltronics
(561) 752-5000
www.coiltronics.com
R
DLY
1.96
t
DELAY
C
DLY
------------------------------------
=
(3)
I
R
V
O
1
D
(
)
f
SW
L
--------------------------------
=
(4)
L
V
VID
R
O
1
n
D
(
)
(
)
f
SW
V
RIPPLE
------------------------------------------------------------------
(5)
L
1.5V
1.3m
1
0.375
(
)
228kHz
10mV
-------------------------------------------------------------------------
534nH
=
FAN53168
PRODUCT SPECIFICATION
18
REV. 1.0.0 6/9/03
Sumida Electric Company
(510) 668-0660
www.sumida.com
Vishay Intertechnology
(402) 563-6866
www.vishay.com
Output Droop Resistance
The design requires that the regulator output voltage
measured at the CPU pins drops when the output current
increases. The specified voltage drop corresponds to a DC
output resistance (R
O
).
The output current is measured by summing together the
voltage across each inductor and then passing the signal
through a low-pass filter. This summer-filter is the CS
amplifier configured with resistors R
PH(X)
(summers), and
R
CS
and C
CS
(filter). The output resistance of the regulator is
set by the following equations, where R
L
is the DCR of the
output inductors:
One has the flexibility of choosing either R
CS
or R
PH(X)
. It is
best to select R
CS
equal to 100k
, and then solve for R
PH(X)
by rearranging Equation 6.
Next, use Equation 7 to solve for C
CS
:
It is best to have a dual location for C
CS
in the layout so
standard values can be used in parallel to get as close to the
value desired. For this example, choosing C
CS
to be 4.7nF is
a good choice. For best accuracy, C
CS
should be a 5% or
10% NPO capacitor. A close standard 1% value for R
PH(X)
is
100k
.
Inductor DCR Temperature Correction
With the inductor's DCR being used as the sense element,
and copper wire being the source of the DCR, one needs to
compensate for temperature changes of the inductor's wind-
ing. Fortunately, copper has a well-known temperature
coefficient (TC) of 0.39%/C.
If R
CS
is designed to have an opposite and equal percentage
change in resistance to that of the wire, it will cancel the
temperature variation of the inductor's DCR. Due to the
nonlinear nature of NTC thermistors, resistors R
CS1
and
R
CS2
are needed (see Figure 5) to linearize the NTC and
produce the desired temperature tracking.
Figure 5. Temperature Compensation Circuit
The following procedure and expressions will yield values to
use for R
CS1
, R
CS2
, and R
TH
(the thermistor value at 25C)
for a given R
CS
value.
1.
Select an NTC to be used based on type and value. Since
we do not have a value yet, start with a thermistor with a
value close to R
CS
. The NTC should also have an initial
tolerance of better than 5%.
2.
Based on the type of NTC, find its relative resistance
value at two temperatures. The temperatures to use that
work well are 50C and 90C. We will call these resis-
tance values A (A is R
TH(50C)
/R
TH(25C)
) and B (B is
R
TH(90C)
/R
TH(25C)
). Note that the NTC's relative value
is always 1 at 25C.
3.
Next, find the relative value of R
CS
required for each of
these temperatures. This is based on the percentage
change needed, which we will initially make 0.39%/C.
We will call these r
1
and r
2
where:
TC = 0.0039
T
1
= 50C
T
2
= 90C
4.
Compute the relative values for R
CS1
, R
CS2
, and R
TH
using:
R
O
R
CS
R
PH X
( )
------------------
R
L
=
(6)
C
CS
L
R
L
R
CS
------------------------
=
(7)
R
PH X
( )
R
L
R
O
--------
R
CS
=
R
PH X
( )
1.6m
1.3m
------------------
100k
123k
=
=
C
CS
650nH
1.6m
100k
-------------------------------------------
4.06nF
=
=
18
17
16
CSREF
CSSUM
CSCOMP
CSA
C
CS
1.8nF
R
CS1
R
CS2
R
TH
R
PH1
R
PH3
R
PH2
Keep this path as
short as possible
and well away from
Switch Node lines
Place as close as
possible to nearest
inductor or low-side
MOSFET
To Switch Nodes
To V
OUT
sense
r
1
1
1
TC
T
1
25
(
)
+
(
)
-----------------------------------------------------
=
r
2
1
1
TC
T
2
25
(
)
+
(
)
-----------------------------------------------------
=
r
CS2
A
B
(
) r
1
r
2
A
1
B
(
)
r
2
B
1
A
(
) r
1
+
A
1
B
(
)
r
1
B
1
A
(
)
r
2
A
B
(
)
------------------------------------------------------------------------------------------------------------------------------------
=
r
CS1
1
A
(
)
1
1
r
CS2
---------------------
A
r
1
r
CS2
----------------------
--------------------------------------------------
=
(8)
r
TH
1
1
1
r
CS2
---------------------
1
r
CS1
------------
---------------------------------------
=
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
19
5.
Calculate R
TH
= r
TH
x R
CS
, then select the closest value
of thermistor available. Also compute a scaling factor k
based on the ratio of the actual thermistor value used
relative to the computed one:
6.
Finally, calculate values for R
CS1
and R
CS2
using the
following:
For this example, R
CS
has been chosen to be 100k
, so we
start with a thermistor value of 100k
. Looking through
available 0603 size thermistors, we find a Panasonic ERT-
J1VV104J NTC thermistor with A = 0.2954 and B =
0.05684. From these we compute R
CS1
= 0.3304, R
CS2
=
0.7426 and R
TH
= 1.165. Solving for R
TH
yields 116.5 k
, so
we choose 100k
, making k = 0.8585. Finally, we find R
CS1
and R
CS2
to be 28.4k
and 77.9k. Choosing the
closest 1% resistor values yields a choice of 35.7k
and
73.2k
.
Output Offset
Intel's specification requires that at no load the nominal
output voltage of the regulator be offset to a lower value than
the nominal voltage corresponding to the VID code. The
offset is set by a constant current source flowing out of the
FB pin (I
FB
) and flowing through R
B
. The value of R
B
can be
found using Equation 11:
The closest standard 1% resistor value is 1.33 k
.
C
OUT
Selection
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
The first thing is to select the total amount of ceramic capac-
itance. This is based on the number and type of capacitor to
be used. The best location for ceramics is inside the socket,
with 12 to 18 of size 1206 being the physical limit. Others
can be placed along the outer edge of the socket as well.
Combined ceramic values of 200
F-300F are recom-
mended, usually made up of multiple 10F or 22F
capacitors. Select the number of ceramics and find the total
ceramic capacitance (C
Z
).
Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
X
) when one considers the VID on-the-
fly voltage stepping of the output (voltage step V
V
in time
t
V
with error V
ERR
) and a lower limit based on meeting the
critical capacitance for load release for a given maximum
load step
I
O
:
where
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (R
X
) should be
less than two times the droop resistance, R
O
. If the C
X(MIN)
is larger than C
X(MAX)
, the system will not meet the VID on-
the-fly specification and may require the use of a smaller
inductor or more phases (and may have to increase the
switching frequency to keep the output ripple the same).
For our example, 22 10F 1206 MLC capacitors
(C
Z
= 220F) were used. The VID on-the-fly step change
is 250mV in 150s with a setting error of 2.5mV. Solving
for the bulk capacitance yields:
where K = 4.6
Using eight 820F A1-Polys with a typical ESR of 8m
,
each yields C
X
= 6.56mF with an R
X
= 1.0m
. One last
check should be made to ensure that the ESL of the bulk
capacitors (L
X
) is low enough to limit the initial high-
frequency transient spike. This can be tested using:
In this example, L
X
is 375pH for the eight A1-Poly capaci-
tors, which satisfies this limitation. If the L
X
of the chosen
bulk capacitor bank is too large, the number of MLC
k
R
TH ACTUAL
(
)
R
TH CALCULATED
(
)
-------------------------------------------------
=
(9)
R
CS1
R
CS
k
r
CS1
=
(10)
R
CS2
R
CS
1
k
(
)
k
r
CS2
(
)
+
(
)
=
R
B
V
VID
V
ONL
I
FB
---------------------------------
=
(11)
R
B
1.5V
1.480V
15
A
--------------------------------------
1.33k
=
=
C
X MIN
(
)
L
I
O
n
R
O
V
VID
------------------------------------
C
Z
(12)
C
X MAX
(
)
L
nK
2
R
O
2
-------------------
V
V
V
VID
------------
1
t
V
V
VID
V
V
------------
nKR
O
L
----------------
2
+
1
C
Z
(13)
K
1n
V
VERR
V
V
------------------
=
C
X MAX
(
)
650nH
250mV
3
4.6
2
1.3m
(
)
2
1.5V
------------------------------------------------------------------------
1
150
s 1.5V
3
4.6
1.3m
250mV
650nH
-------------------------------------------------------------------------------------
2
+
1
220F
23.9mF
=
C
X MIN
(
)
650nH
60A
3
1.3m
1.5V
-----------------------------------------------
200
F
6.45mF
=
L
X
C
Z
R
O
2
(14)
L
X
220
F
1.3m
(
)
2
372pH
=
FAN53168
PRODUCT SPECIFICATION
20
REV. 1.0.0 6/9/03
capacitors must be increased. One should note for this multi-
mode control technique, "all-ceramic" designs can be used
as long as the conditions of Equations 11, 12 and 13 are
satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are V
GS(TH)
, Q
G
, C
ISS
, C
RSS
and R
DS(ON)
.
The minimum gate drive voltage (the supply voltage to the
FAN53418) dictates whether standard threshold or logic-
level threshold MOSFETs must be used. With V
GATE
~10V,
logic-level threshold MOSFETs (V
GS(TH)
< 2.5V) are
recommended. The maximum output current I
O
determines
the R
DS(ON)
requirement for the low-side (synchronous)
MOSFETs. With the FAN53168, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (n
SF
). With conduction losses being dominant,
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
R
) and average total output current
(I
O
):
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can find
the required R
DS(ON)
for the MOSFET. For D-PAK
MOSFETs up to an ambient temperature of 50C, a safe
limit for P
SF
is 1W-1.5W at 125C junction temperature.
Thus, for our example (65A maximum), we find R
DS(SF)
(per MOSFET) < 8.7m
. This R
DS(SF)
is also at a junction
temperature of about 125C, so we need to make sure we
account for this when making this selection. For our
example, we selected two lower side MOSFETs at 8.6m
each at room temperature, which gives 8.4m
at high
temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio of
the feedback to input needs to be small (less than 10% is
recommended) to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN53418). The
output impedance of the driver is about 2
and the typical
MOSFET input gate resistances are about 1
2, so a total
gate capacitance of less than 6000pF should be adhered to.
Since there are two MOSFETs in parallel, we should limit
the input capacitance for each synchronous MOSFET to
3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where n
MF
is the total number of
main MOSFETs:
Here, R
G
is the total gate resistance (2
for the FAN53418
and about 1
for typical high speed switching MOSFETs,
making R
G
= 3
) and C
ISS
is the input capacitance of the
main MOSFET. It is interesting to note that adding more
main MOSFETs (n
MF
) does not really help the switching
loss per MOSFET since the additional gate capacitance
slows down switching. The best way to reduce switching
loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where R
DS(MF)
is the ON-resistance of the
MOSFET:
Typically, for main MOSFETs, one wants the highest speed
(low C
ISS
) device, but these usually have higher ON-resis-
tance. One must select a device that meets the total power
dissipation (about 1.5 W for a single D-PAK) when combin-
ing the switching and conduction losses.
For our example, we have selected a Fairchild FD6696 as the
main MOSFET (three total; n
MF
= 3), with a C
iss
= 2058 pF
(max) and R
DS(MF)
= 15m
(max at T
J
= 125C) and a
Fairchild FDD6682 as the synchronous MOSFET (six total;
n
SF
= 6), with C
iss
= 2880pF (max) and R
DS(SF)
= 11.9m
(max at T
J
= 125C). The synchronous MOSFET C
iss
is less
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at I
O
= 65 A and I
R
= 8.86A
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last thing to look at is the power dissipation in the driver
for each phase. This is best described in terms of the Q
G
for
the MOSFETs and is given by the following, where Q
GMF
is
the total gate charge for each main MOSFET and Q
GSF
is the
total gate charge for each synchronous MOSFET:
P
SF
1
D
(
)
I
O
n
SF
---------
2
1
12
------
n
I
R
n
SF
--------------
2
+
R
DS SF
(
)
=
(15)
P
S MF
(
)
2
f
SW
V
CC
I
O
n
MF
-----------------------
R
G
n
MF
n
----------
C
ISS
=
(16)
P
C MF
(
)
D
I
O
n
MF
----------
2
1
12
------
n
I
R
n
MF
--------------
2
+
R
DS MF
(
)
=
(17)
P
DRV
f
SW
2
n
------------
n
MF
Q
GMF
n
SF
Q
GSF
+
(
) I
CC
+
V
CC
=
(18)
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
21
Also shown is the standby dissipation factor (I
CC
times the
V
CC
) for the driver. For the FAN53418, the maximum dissi-
pation should be less than 400 mW. For our example, with
I
CC
= 7 mA, Q
GMF
= 24nC (max) and Q
GSF
= 31nC (max),
we find 202 mW in each driver, which is below the 400 mW
dissipation limit. See the FAN53418 data sheet for more
details.
Ramp Resistor Selection
The ramp resistor (R
R
) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
and transient response. The following expression is used for
determining the optimum value:
where A
R
is the internal ramp amplifier gain, A
D
is the
current balancing amplifier gain, R
DS
is the total low-side
MOSFET ON-resistance, and C
R
is the internal ramp
capacitor value. A close standard 1% resistor value is 301k
.
The internal ramp voltage magnitude can be calculated
using:
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrifice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
For this example, the overall ramp signal is found to be
0.974 V.
Current Limit Set Point
To select the current limit set point, we need to find the resis-
tor value for R
LIM
. The current limit threshold for the
FAN53168 is set with a 3V source (V
LIM
) across R
LIM
with
a gain of 10.4mV/
A (A
LIM
). R
LIM
can be found using the
following:
For values of R
LIM
greater than 500k
, the current limit may
be lower than expected, so some adjustment of R
LIM
may be
needed. Here, I
LIM
is the average current limit for the output
of the supply. For our example, choosing 120A for I
LIM
, we
find R
LIM
to be 200k
, for which we chose 200k as the
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
For the FAN53168, the maximum COMP voltage
(V
COMP(MAX)
) is 3.3 V, the COMP pin bias voltage (V
BIAS
)
is 1.2V, and the current balancing amplifier gain (A
D
) is 5.
Using V
R
of 0.765V, and R
DS(MAX)
of 5.95m
(low-side
ON-resistance at 125C), we find a per-phase limit of
40.44A.
This limit can be adjusted by changing the ramp voltage V
R
.
But make sure not to set the per-phase limit lower than the
average per-phase current (I
LIM
/n).
There is also a per phase initial duty cycle limit determined
by:
For this example, the maximum duty cycle is found to be
0.2696.
Feedback Loop Compensation Design
Optimized compensation of the FAN53168 allows the best
possible response of the regulator's output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including DC, and equal to the
droop resistance (R
O
). With the resistive output impedance,
the output voltage will droop in proportion with the load
current at any load current slew rate; this ensures the optimal
positioning and allows the minimization of the output
decoupling.
R
R
A
R
L
3
A
D
R
DS
C
R
-------------------------------------------------
=
(19)
R
R
0.2
650nH
3
5
5.95m
5pF
----------------------------------------------------------
291k
=
=
V
R
A
R
1
D
(
)
V
VID
R
R
C
R
f
SW
---------------------------------------------------
=
(20)
V
R
0.2
1
0.125
(
)
1.5V
301k
5pF
228kHz
---------------------------------------------------------------
0.765V
=
=
V
RT
V
R
1
2
1
n
D
(
)
n
f
SW
C
X
R
O
-----------------------------------------------
--------------------------------------------------------------
=
(21)
R
LIM
A
LIM
V
LIM
I
LIM
R
O
-------------------------------
=
(22)
I
PHLIM
V
COMP MAX
(
)
V
R
V
BIAS
A
D
R
DS MAX
(
)
---------------------------------------------------------------------
I
R
2
-----
(23)
D
MAX
D
V
COMP MAX
(
)
V
BIAS
V
RT
--------------------------------------------------------
=
(24)
FAN53168
PRODUCT SPECIFICATION
22
REV. 1.0.0 6/9/03
With the multimode feedback structure of the FAN53168,
one needs to set the feedback compensation to make the
converter's output impedance working in parallel with the
output decoupling meet this goal. There are several poles and
zeros created by the output inductor and decoupling capaci-
tors (output filter) that need to be compensated for.
A type-three compensator on the voltage feedback is
adequate for proper compensation of the output filter. The
expressions given in Equations 2529 are intended to yield
an optimal starting point for the design; some adjustments
may be necessary to account for PCB and component para-
sitic effects (see the Tuning Procedure for the FAN53168
section).
The first step is to compute the time constants for all of the
poles and zeros in the system:
where, for the FAN53168, R' is the PCB resistance from the
bulk capacitors to the ceramics and where R
DS
is approxi-
mately the total low-side MOSFET ON resistance per phase
at 25C. For this example, A
D
is 5, V
RT
equals 0.974V, R' is
approximately 0.6m
(assuming a 4-layer motherboard) and
L
X
is 375pH for the eight Al-Poly capacitors.
The compensation values can then be solved for using the
following:
Choosing the closest standard values for these components
yields: C
A
= 390pF, R
A
= 16.9k
, C
B
= 1.5nF,
and C
FB
= 33pF.
C
IN
Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of
the high-side MOSFET is approximately a square wave with
a duty ratio equal to n (V
OUT
/V
IN
) and an amplitude of one-
nth of the maximum output current. To prevent large voltage
transients, a low ESR input capacitor sized for the maximum
rms current must be used. The maximum rms capacitor
current is given by:
Figure 6. Typical Transient Response for Design Example
R
E
n
R
O
A
D
R
DS
R
L
V
RT
V
VID
----------------------
2
L
1 n
D
(
) V
RT
n
C
X
R
O
V
VID
--------------------------------------------------------
+
+
+
=
(25)
R
E
3
1.3m
5 5.95m
1.6m
0.974V
1.5V
--------------------------------------------
+
+
+
=
2
650nH
1
0.375
(
)
0.974V
3
6.56mF
1.3m
1.5V
-----------------------------------------------------------------------------------------
55.3m
=
T
A
C
X
R
O
R'
(
)
L
X
R
O
--------
R
O
R'
R
X
-------------------
+
=
(26)
T
A
6.56mF
1.3
0.6m
(
)
375pH
1.3m
------------------
+
=
1.3m
0.6m
1.0m
-------------------------------------------
4.79
s
=
T
B
R
X
R'
R
O
+
(
) C
X
=
(27)
T
B
1.0m
0.6m 1.3m
+
(
) 6.56mF
1.97
s
=
=
T
C
V
RT
L
A
D
R
DS
2
f
SW
-------------------------
V
VID
R
E
---------------------------------------------------------
=
(28)
T
C
0.974V
650nH
5
6.95m
2
228kHz
-------------------------------
1.5V
55.3m
---------------------------------------------------------------------------------------
6.86
s
=
=
T
D
C
X
C
Z
R
2
O
C
X
R
O
R'
(
) C
Z
R
O
+
------------------------------------------------------------------
=
(29)
T
D
6.56mF
220
F
1.3m
(
)
2
6.56mF
1.3m
0.6m
(
)
220
F 1.3m
+
----------------------------------------------------------------------------------------------------------------------------
500ns
=
=
C
A
n
R
O
T
A
R
E
R
B
-------------------------------
=
(30)
C
A
3
1.3m
4.79
s
55.3m
1.33k
-----------------------------------------------------
253pF
=
=
R
A
T
C
C
A
-------
6.86
s
253pF
------------------
27.1k
=
=
=
(31)
C
B
T
B
R
B
-------
1.97
s
1.33k
-------------------
1.48nF
=
=
=
(32)
C
FB
T
D
R
A
-------
500ns
27.1k
-------------------
18.5pF
=
=
=
(33)
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
23
Note that the capacitor manufacturer's ripple current ratings
are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a
capacitor rated at a higher temperature than required. Several
capacitors may be placed in parallel to meet size or height
requirements in the design. In this example, the input capaci-
tor bank is formed by three 2200
F, 16V Nichicon capaci-
tors with a ripple current rating of 3.5 A each.
To reduce the input-current di/dt to below the recommended
maximum of 0.1A/s, an additional small inductor (L > 1H
@ 15A) should be inserted between the converter and the
supply bus. That inductor also acts as a filter between the
converter and the primary power source.
TUNING PROCEDURE FOR THE FAN53168
1.
Build circuit based on compensation values computed
from design spreadsheet.
2.
Hook up dc load to circuit, turn on and verify opera-
tion.Also check for jitter at no-load and full-load.
DC Loadline Setting
3.
Measure output voltage at no-load (V
NL
). Verify it is
within tolerance.
Figure 7. Efficiency vs. Output Current (Circuit of Figure 1)
4.
Measure output voltage at full-load cold (V
FLCOLD
).
Let board soak for ~10 minutes at full-load and measure
output (V
FLHOT
). If there is a change of more than a
couple of millivolts, adjust R
CS1
and R
CS2
using
Equations 35 and 37.
5.
Repeat Step 4 until cold and hot voltage measurements
remain the same.
6.
Measure output voltage from no-load to full-load using
5A steps. Compute the loadline slope for each change
and then average to get overall loadline slope (R
OMEAS
).
7.
If R
OMEAS
is off from R
O
by more than 0.05 mW, use
the following to adjust the R
PH
values:
8.
Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9.
Once complete with dc loadline adjustment, do not
change R
PH
, R
CS1
, R
CS2
, or R
TH
for rest of procedure.
10. Measure output ripple at no-load and full-load with
scope and make sure it is within spec.
AC Loadline Setting
11. Remove dc load from circuit and hook up dynamic load.
12. Hook up scope to output voltage and set to dc coupling
with time scale at 100
s/div.
13. Set dynamic load for a transient step of about 40A at
1kHz with 50% duty cycle.
14. Measure output waveform (may have to use dc offset on
scope to see waveform). Try to use vertical scale of 100
mV/div or finer.
15. You will see a waveform that looks something like
Figure 8. Use the horizontal cursors to measure V
ACDRP
and V
DCDRP
as shown. DO NOT MEASURE THE
UNDERSHOOT OR OVERSHOOT THAT HAPPENS
IMMEDIATELY AFTER THE STEP.
I
CRMS
D
I
O
1
n
D
-------------
1
=
(34)
I
CRMS
0.125
65A
1
3
0.125
------------------------
1
10.5A
=
=
R
CS2 NEW
(
)
R
CS2 OLD
(
)
V
NL
V
FLCOLD
(
)
V
NL
V
FLHOT
(
)
---------------------------------------------
=
(35)
100
0
10
20
30
OUTPUT CURRENT A
EFFICIENCY
%
40
50
60
80
60
40
20
0
R
PH NEW
(
)
R
PH OLD
(
)
R
OMEAS
R
O
----------------------
=
(36)
1
R
CS OLD
(
)
R
TH 25
C
(
)
+
R
CS1 OLD
(
)
R
TH 25
C
(
)
R
CS2 OLD
(
)
R
CS2 NEW
(
)
(
)
R
CS1 OLD
(
)
R
TH 25
C
(
)
(
)
+
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1
R
TH 25
C
(
)
------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
R
CS NEW
(
)
=
(37)
FAN53168
PRODUCT SPECIFICATION
24
REV. 1.0.0 6/9/03
Figure 8. AC Loadline Waveform
16. If the V
ACDRP
and V
DCDRP
are different by more than a
couple of millivolts, use Equation 38 to adjust C
CS
. You
may need to parallel different values to get the right one
since there are limited standard capacitor values avail-
able (it is a good idea to have locations for two capaci-
tors in the layout for this).
17. Repeat Steps 11 to 13 and repeat adjustments if neces-
sary. Once complete, do not change C
CS
for the rest of
the procedure.
18. Set dynamic load step to maximum step size (do not use
a step size larger than needed) and verify that the output
waveform is square (which means V
ACDRP and
V
DCDRP
are equal). NOTE: MAKE SURE LOAD STEP SLEW
RATE AND TURN-ON ARE SET FOR A SLEW RATE
OF ~150250A/s (for example, a load step of 50A
should take 200 ns300 ns) WITH NO OVERSHOOT.
Some dynamic loads will have an excessive turn-on
overshoot if a minimum current is not set properly (this
is an issue if using a VTT tool).
Initial Transient Setting
19. With dynamic load still set at maximum step size,
expand scope time scale to see 2s/div to 5s/div. You
will see a waveform that may have two overshoots and
one minor undershoot (see Figure 9). Here, V
DROOP
is
the final desired value.
Figure 9. Transient Setting Waveform
20. If both overshoots are larger than desired, try making the
following adjustments in this order. (NOTE: If these
adjustments do not change the response, you are limited
by the output decoupling.) Check the output response
each time you make a change as well as the switching
nodes (to make sure it is still stable).
a. Make ramp resistor larger by 25% (R
RAMP
).
b. For V
TRAN1
, increase C
B
or increase switching
frequency.
c. For V
TRAN2
, increase R
A
and decrease C
A
by 25%.
21. For load release (see Figure 10), if V
TRANREL
is larger
than V
TRAN1
(see Figure 9), you do not have enough
output capacitance. You will either need more capaci-
tance or to make the inductor values smaller (if you
change inductors, you need to start the design over using
the spreadsheet and this tuning procedure).
Figure 10. Transient Setting Waveform
C
CS NEW
(
)
C
CS OLD
(
)
V
ACDRP
V
DCDRP
----------------------
=
(38)
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
25
Since the FAN53168 turns off all of the phases (switches
inductors to ground), there is no ripple voltage present dur-
ing load release. Thus, you do not have to add headroom for
ripple, allowing your load release V
TRANREL
to be larger
than V
TRAN1
by that amount and still be meeting spec.
If V
TRAN1
and V
TRANREL
are less than the desired final
droop, this implies that capacitors can be removed. When
removing capacitors, make sure to check the output ripple
voltage as well to make sure it is still within spec.
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal per-
formance of a switching regulator in a PC system. Key lay-
out issues are illustrated in Figure 11.
General Recommendations
For good results, at least a four-layer PCB is
recommended. This should allow the needed versatility
for control circuitry interconnections with optimal
placement, power planes for ground, input, and output
power, and wide interconnection traces in the rest of the
power delivery current paths. Keep in mind that each
square unit of 1 ounce copper trace has a resistance of
~0.53 m
at room temperature.
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.
If critical signal lines (including the output voltage sense
lines of the FAN53168) must cross through power
circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
An analog ground plane should be used around and under
the FAN53168 for referencing the components associated
with the controller to. This plane should be tied to the
nearest output decoupling capacitor ground and should
not tie to any other power circuitry to prevent power
currents from flowing in it.
The components around the FAN53168 should be located
close to the controller with short traces. The most
important traces to keep short and away from other traces
are the FB and CSSUM pins. Refer to Figure 11 for more
details on layout for the CSSUM node.
The output capacitors should be connected as closely as
possible to the load (or connector) that receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic.
Avoid crossing any signal lines over the switching power
path loop, described next.
Power Circuitry
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to
minimize radiated switching noise energy (i.e., EMI) and
conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire
PC system as well as noise related operational problems
in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors and the power MOSFETs including
all interconnecting PCB traces and planes. The use of
short and wide interconnection traces is especially critical
in this path for two reasons: it minimizes the inductance in
the switching loop, which can cause high-energy ringing,
and it accommodates the high current demand with
minimal voltage loss.
Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
for this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air. Make a mirror image of any
pad being used to heatsink the MOSFETs on the opposite
side of the PCB to achieve the best thermal dissipation to
the air around the board. To further improve thermal
performance, the largest possible pad area should be used.
Figure 11. Layout Recommendations
The output power path should also be routed to
encompass a short distance. The output power path is
formed by the current path through the inductor, the
output capacitors, and the load.
For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.
FAN53168
PRODUCT SPECIFICATION
26
REV. 1.0.0 6/9/03
Signal Circuitry
The output voltage is sensed and regulated between the
FB pin and the FBRTN pin (which connects to the signal
ground at the load). In order to avoid differential mode
noise pickup in the sensed signal, the loop area should be
small. Thus the FB and FBRTN traces should be routed
adjacent to each other atop the power ground plane back
to the controller.
The feedback traces from the switch nodes should be
connected as close as possible to the inductor. The CSREF
signal should be connected to the output voltage at the
nearest inductor to the controller.
PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
27
Mechanical Dimensions
TSSOP-28
9.7
0.1
15
B
0.1 C
PIN # 1 IDENT
1
14
ALL Lead Tips
0.2
LAND PATTERN RECOMMENDATION
0.65
0.42
B
C
A
A
4.4
0.1
1.78
4.16
7.72
0.51 TYP
28
3.2
6.4
1.2 MAX
ALL LEAD TIPS
0.65
0.190.30
0.13
0.90
See Detail A
0.090.20
0.10
0.05
0
8
R0.31
R0.16
.025
GAGE PLANE
SEATING PLANE
DETAIL A
0.61
0.1
DIMENSIONS ARE IN MILLIMETERS
NOTES:
A. Conforms to JEDEC registration MO-153, variation AB,
Ref. Note 6, dated 7/93.
B. Dimensions are in millimeters.
C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions.
D Dimensions and Tolerances per ANSI Y14.5M, 1982
1.00
12.00
Top & Bottom
+0.15
0.10
B
C
A
C
FAN53168
PRODUCT SPECIFICATION
6/9/03 0.0m 005
Stock#DS300053168
2003 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
Part Number
Temperature Range
Package
FAN53168MTC
0C to +85C
TSSOP-28