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Электронный компонент: FAN53180MTC

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www.fairchildsemi.com
REV. 1.0.0 6/10/03
Features
Precision Multi-Phase DC-DC Core Voltage Regulation
14.5mV Output Voltage Accuracy Over Temperature
Differential Remote Voltage Sensing
Selectable 2, 3, or 4 Phase Operation
Up to 1MHz per Phase Operation (4MHz ripple
Frequency)
Lossless Inductor Current Sensing for Loadline
Compensation
External Temperature Compensation
Accurate Load-Line Programming (Meets Intel VRM/
VRD10 CPU Specifications)
Accurate Channel-Current Balancing for Thermal
Optimization and Layout Compensation
Convenient 12V Supply Biasing
6-bit Voltage Identification (VID) Input
0.8375V to 1.600V in 12.5mV Steps
Dynamic VID Capability with Fault-Blanking for
glitch-less Output voltage Changes
Adjustable Over Current Protection with Programmable
Latch-Off Delay
Over-Voltage Protection -- Internal OVP Crowbar
Protection
Applications
Computer DC/DC Converter VRM/VRD10.0
Computer DC/DC Converter VRM/VRD9.X
High Current, Low Voltage DC/DC Rail
General Description
The FAN53180 is a multi-phase DC-DC controller for
implementing high-current, low-voltage, CPU core power
regulation circuits. It is part of a chipset that includes
external MOSFET drivers and power MOSFETS. The
FAN53180 drives up to 4 synchronous-rectified buck
channels in parallel. The multi-phase buck converter
architecture uses interleaved switching to multiply ripple
frequency by the number of phases and reduce input and
output ripple currents. Lower ripple results in fewer com-
ponents, lower component cost, reduced power dissipation,
and smaller board area.
The FAN53180 features a high bandwidth control loop to
provide optimal response to load transients. The FAN53180
senses current using lossless techniques: Phase current is
measured through each of the output inductors. This current
information is summed, averaged and used to set the loadline
of the output via programmable "droop". The droop is
temperature compensated to achieve precise loadline
characteristics over the entire operating range. Additionally,
individual phase current is measured using the R
DS-ON
of the
low-side MOSFET's. This information is used to dynami-
cally balance/steer per-phase current. The phase currents are
also summed and averaged for over-current detection.
Dynamic-VID technology allows on-the-fly VID changes
with controlled, glitch-less output. Additionally, short-circuit
protection, adjustable current limiting, over-voltage protec-
tion and power-good circuitry combine to ensure reliable and
safe operation. The operating temperature range is 0C to
+85C and the operating voltage is a single +12V supply,
simplifying design. The FAN53180 is available in a
TSSOP-28 package.
System Block Diagram
FAN53180
FAN53418
V
IN
FAN53418
V
IN
1
2
3
4
V
OUT
FAN53180
6-Bit VID Controlled 2-4 Phase DC-DC Controller
FAN53180
PRODUCT SPECIFICATION
2
REV. 1.0.0 6/10/03
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired.
Functional operation under these conditions is not implied.
Thermal Information
Recommended Operating Conditions
(See Figure 1)
Note:
1.
JA
is defined as 2 oz., 4 layer copper PCB with 1 in
2
thermal pad.
Parameter
Min.
Max.
Units
Supply Voltage: VCC to GND
-0.3
+15
V
Voltage on FBRTN pin
-0.3
+0.3
V
Voltage on SW1SW4
-5
+25
V
Voltage on VID [5:0], EN, DELAY, ILIMIT, CSCOMP, RT, PWM[4:1], COMP
-0.3
+5.5
V
Voltage on any other pin
-0.3
VCC+0.3
V
Parameter
Min.
Typ.
Max.
Units
Operating Junction Temperature (T
J
)
+125
C
Storage Temperature
65
+150
C
Lead Soldering Temperature, 10 seconds
+300
C
Vapor Phase, 60 seconds
+215
C
Infrared, 15 seconds
+220
C
Power Dissipation (P
D
) @ T
A
=25C
1
W
Thermal Resistance (
JA
)*
100
C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage VCC
VCC to GND
10.8
12
13.2
V
Ambient Operating Temperature
0
+85
C
PRODUCT SPECIFICATION
FAN53180
REV. 1.0.0 6/10/03
3
Pin Configuration
Pin Definitions
Pin
Number Pin Name
Pin Function Description
16
VID[4:0],
VID5
VID Inputs.
Determines the output voltage via the internal DAC. These inputs are
compliant to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups so leaving them open results in logic high. Leaving VID[4:0] open results
in a "No CPU" condition disabling the PWM outputs.
7
FBRTN
Feedback Return.
Error Amp and DAC reference point.
8
FB
Feedback Input.
Inverting input for Error Amp this pin is used for external compensation.
Can also be used to introduce DC offset voltage to the output.
9
COMP
Error Amp Output.
This pin is used for external compensation.
10
PWRGD
Power Good Output.
This is an open-drain output that asserts when the output voltage is
within the specified tolerance. It is expected to be pulled up to an external voltage rail.
11
EN
Output Enable.
This is a dual-function pin. It allows for an external open-drain drain logic
signal to enable the output PWM.
12
DELAY
Soft-start and Current Limit Delay.
An external resistor and capacitor sets the soft-start
ramp rate and the over-current latch off delay.
13
RT
Switching Frequency Adjust.
This pin adjusts the output PWM switching frequency via
an external resistor.
14
RAMPADJ
PWM Current Ramp Adjust.
An external resistor to Vcc will adjust the amplitude of the
internal PWM ramp.
15
ILIMIT
Current Limit Adjust.
An external resistor sets the current limit threshold for the regulator
circuit. This pin is internally pulled low when EN is low or the UVLO circuit is active.
16
CSREF
Current Sense Return.
Inverting input of the current sense amp. Sense point for the
output voltage used for OVP, and PWRGD.
17
CSSUM
Current Sense Summing node.
Non-inverting input of the current sense amp.
18
CSCOMP
Current Sense Compensation node.
Output of the current sense amplifier. This pin is
used for droop compensation, a current loop reponse.
19
GND
Analog Chip Ground.
Signal ground for the chip
2023
SW[4:1]
Phase Current Sense/Balance inputs.
Phase-to-phase current sense and balancing
inputs. Unused phases should be left open.
2427
PWM[4:1]
PWM Outputs.
CMOS outputs for driving external gate drivers such as the FAN53418.
Unused phases should be grounded.
28
VCC
Chip Power.
Bias supply for the chip. Connect directly to a +12V supply. Bypass with a
1
F MLCC capacitor.
DELAY
VID4
VID3
VID2
VID1
VID0
VID5
COMP
CSCOMP
PWRGD
EN
CSSUM
RT
VCC
SW2
SW3
PWM3
PWM4
PWM1
GND
FBRTN
ILIMIT
FB
CSREF
RAMPADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FAN53180
TSSOP-28
SW1
PWM2
SW4
FAN53180
PRODUCT SPECIFICATION
4
REV. 1.0.0 6/10/03
Electrical Specifications
1
(Vcc = 12V, T
A
= 0
C to +85
C and FBRTN = GND, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
2. Guaranteed by design NOT tested in production.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Error Amplifier
Output Voltage Range
V
COMP
0.5
3.5
V
Accuracy
V
FB
Relative to Nominal DAC Output,
Referenced to FBRTN, CSSUM =
CSCOMP, Figure 3
-14.5
+14.5
mV
Line Regulation
V
FB
VCC = 10V to 14V
0.05
%
Input Bias Current
I
FB
13
15
17
A
FBRTN Current
I
FBRTN
90
120
A
Output Current
I
O(ERR)
FB forced to V
OUT
3%
500
A
Gain Bandwidth Product
GBW
(ERR)
COMP = FB
20
MHz
Slew Rate
C
COMP
= 10pF
50
V/
s
VID Inputs
Input Low Voltage
V
IL(VID)
0.4
V
Input High Voltage
V
IH(VID)
0.8
V
Input Current, VID Low
I
IL(VID)
VID(X) = 0V
-30
-20
A
Input Current, VID High
I
IH(VID)
VID(X) = 1.25V
15
25
A
Pull-up Resistance
R
VID
60
k
Internal Pull-up Voltage
0.825
1.00
V
VID Transition Delay
Time
2
VID Code Change to FB Change
400
ns
"No CPU" Detection
Turn-off Delay Time
2
VID Code Change to 11111 to PWM
going low
400
ns
Oscillator
Frequency
2
f
OSC
250
4000
kHz
Frequency Variation
f
PHASE
T
A
= +25C, R
T
= 250k
, 4-Phase
T
A
= +25C, R
T
= 115k
, 4-Phase
T
A
= +25C, R
T
= 75k
, 4-Phase
155
200
400
600
245
kHz
kHz
kHz
Output Voltage
V
RT
R
T
= 100k
to GND
1.9
2.0
2.1
V
RAMPADJ Output Voltage V
RAMPADJ
RAMPADJ-FB
-50
+50
mV
RAMPADJ Input Current
Range
I
RAMPADJ
0
100
A
PRODUCT SPECIFICATION
FAN53180
REV. 1.0.0 6/10/03
5
Electrical Specifications
1
(Vcc = 12V, T
A
= 0
C to +85C and FBRTN = GND, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
2. Guaranteed by design NOT tested in production.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Current Sense Amplifier
Offset Voltage
V
OS(CSA)
CSSUM-CSREF, Test Circuit 1
-3
+3
mV
Input Bias Current
I
BIAS(CSA)
-50
+50
nA
Gain Bandwidth Product
GBW
(ERR)
COMP = FB
20
MHz
Slew Rate
C
COMP
= 10pF
50
V/
s
Input Common Mode
Range
CSSUM and CSREF
0
3
V
Positioning Accuracy
V
FB
COMP = FB, Test Circuit 2
-83
-80
-77
mV
Output Voltage Range
I
CSCOMP
= 100
A
0.05
3.3
V
Output Current
I
O(ERR)
FB forced to V
OUT
3%
500
A
Current Balance Circuit
Common Mode Range
V
SW(X)CM
-600
+200
mV
Input Resistance
R
SW(X)
SW(X) = 0V
20
30
40
k
Input Current
I
SW(X)
SW(X) = 0V
4
7
10
A
Input Current Matching
I
SW(X)
SW(X) = 0V
-5
+5
%
Current Limit Comparator
ILIMIT Output Voltage
Normal Mode
In Shutdown
V
ILIMIT(NM)
V
ILIMIT(SD)
EN > 0.8V, R
ILIMIT
= 250k
EN < 0.4V, I
ILIMIT
= -100
A
2.9
3
3.1
400
V
mV
Output Current, Normal
Mode
I
ILIMIT(NM)
EN > 0.8V, R
ILIMIT
= 250k
12
A
Maximum Output Current
EN > 0.8V
60
A
Current Limit Threshold
Voltage
V
CL
V
CSREF
V
CSCOMP
, R
ILIMIT
= 250k
105
125
145
mV
Current Limit Setting Ratio
V
CL
/I
ILIMIT
10.4
mV/
A
Latch-off Delay Threshold
V
DELAY
In Current Limit
1.7
1.8
1.9
V
Latch-off Delay Time
t
DELAY
R
DELAY
= 250k
, C
DELAY
= 4.7nF
600
s
Soft Start
Output Current, Softstart
Mode
I
DELAY(SS)
During Start-up, DELAY < 2.8 V
15
20
25
A
Soft Start Delay Time
T
DELAY(SS)
R
DELAY
= 250k
, C
DELAY
= 4.7nF,
VID[5:0] = 011111
350
s
Enable Input
Input Low Voltage
V
IL(EN)
0.4
V
Input High Voltage
V
IH(EN)
0.8
V
Input Current, EN Low
I
IL(EN)
EN = 0V
-1
1
A
Input Current, EN High
I
IH(EN)
EN = 1.25V
10
25
A