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Электронный компонент: FAN53418M

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www.fairchildsemi.com
REV. 1.0.0 6/11/03
Features
Drives N-channel High-Side and Low-Side MOSFETs in
a synchronous buck configuration
Internal Adaptive "Shoot-Through" Protection
High Switching Frequency (> 500kHz)
30ns Output Rise/Fall Times w/3000pF load
20ns Propagation Delay
12V High-Side and 12V Low-Side Drive
OD input for Output Disable allows for synchronization
with PWM controller
SOIC-8 Package
Applications
Multi-phase VRM/VRD regulators for Microprocessor
Power
High Current/High Frequency DC/DC Converters
High Power Modular Power Supplies
General Description
The FAN53418 is a high frequency, dual MOSFET driver
specifically designed to drive two power N-Channel
MOSFETs in a synchronous rectified buck converter.
These drivers combined with a FAN53168 Multi-Phase Buck
PWM controller and power MOSFETs form a complete core
voltage regulator solution for advanced microprocessors.
The FAN53418 drives both the upper and lower gates in a
synchronous rectifier to +12V. The upper gate drive imple-
ments bootstrapping with only an external capacitor and
diode required. This reduces implementation complexity
and allows the use of higher performance, cost effective,
N-Channel MOSFETs.
The output drivers in the FAN53418 have the capacity to
efficiently switch power MOSFETs at frequencies over
500kHz. Each driver is capable of driving a 3000pF load
with a ~20ns propagation delay and ~30ns transition time.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously. Addition-
ally an Output Disable function is included to synchronize
the driver with the PWM controller. The FAN53418 is
rated for operation from 0C to +85C and is available in a
low-cost SOIC-8 package.
FAN53418
Synchronous DC-DC MOSFET Driver
Basic Application
Figure 1. Basic Application Circuit
FAN54318
1
2
4
3
8
7
5
6
DRVH
BST
IN
SW
PGND
DRVL
VCC
OD
D1
CBST
Q2
C VCC
L1
C VIN
Q1
+12V
FAN53418
2
REV. 1.0.0 6/11/03
Pin Configuration
Pin Description
Internal Block Diagram
Pin Number
Pin Name
Pin Function Description
1
BST
Bootstrap Supply Input
. Provides voltage supply to high-side MOSFET driver.
Connect to bootstrap capacitor (typically 100nF to 1F). See Applications
Section for detailed information.
2
IN
PWM Signal Input
. This pin accepts a digital logic-level PWM switching signal
from the controller.
3
OD
Output Disable
. When low, this pin disables PWM switching and pulls DRVH
and DRVL low.
4
VCC
Power Input
. +12V chip bias power. Bypass with a 1F ceramic capacitor.
5
DRVL
Low Side Gate Drive Output
. Connect to the gate of low-side power
MOSFET(s).
6
PGND
Power Ground
. Power ground connect close to low-side MOSFET to minimize
ground loops.
7
SW
Switch Node Input
. Connect to switching node between HS and LS MOSFETs.
It is necessary for adaptive shoot-thru protection. Also it provides return for
high-side bootstrapped driver.
8
DRVH
High Side Gate Drive Output
. Connect to the gate of high-side power
MOSFET(s).
IN
OD
VCC
BST
DRVH
SW
DRVL
PGND
1
2
3
4
8
7
6
5
FAN53418
SOIC-8
3
Delay
DRVH
DRVL
SW
BST
VCC
IN
+1V
+1V
6
5
7
8
1
4
2
PGND
OD
1k
FAN53418
REV. 1.0.0 6/11/03
3
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Thermal Information
Recommended Operating Conditions
See Figure 1
Note:
1.
JA
is defined as 2 oz., 4 layer copper PCB with 1 in
2
thermal pad.
Parameter
Min.
Max.
Units
Supply Voltage: V
CC
to PGND
-0.3
+15
V
SW to PGND
-5
+15
V
BST to SW Voltage: V
BST
V
SW
-0.3
+15
V
BST Voltage: V
BST
PGND
-0.3
V
CC
+ 15
V
DRVH
V
SW
0.3
V
BST
+ 0.3
V
DRVL (<200ns duration)
-2
V
CC
+ 0.3
V
Voltage on any other pin
-0.3
V
CC
+ 0.3
V
Parameter
Min.
Typ.
Max.
Units
Operating Junction Temperature (T
J
)
0
+150
C
Storage Temperature
65
+150
C
Lead Soldering Temperature, 10 seconds
+300
C
Vapor Phase, 60 seconds
+215
C
Infrared, 15 seconds
+220
C
Power Dissipation (P
D
) @ T
A
= 25C
1052
mW
Thermal Resistance (
JA
)*
95
C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage V
CC
V
CC
to GND
10.8
12
13.2
V
Ambient Operating Temperature
0
+85
C
Operating Junction Temperature (T
J
)
0
+150
C
FAN53418
4
REV. 1.0.0 6/11/03
Electrical Specifications
(Vcc = 12V, and T
A
= 0C to +85C, V
BST
= 4V to 26V, unless otherwise noted.)
The denotes specifications which apply over the full operating temperature range.
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
2. AC Specifications guaranteed by design/characterization NOT tested in production.
3. For propagation delays "t
pdh
" refers to low-to-high signal transition and "t
pdl
" refers to high-to-low signal transition.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Supply
Supply Voltage Range
V
CC
4.15
13.2
V
Supply Current
I
SYS
BST = 12V, IN = 0V
3
6
mA
OD Input
Input High Voltage
V
IH(OD)
2.8
V
Input Low Voltage
V
IL(OD)
0.8
V
Input Current
I
IL(OD)
-1
+1
A
Propagation Delay Time
2
t
pdl(OD)
t
pdh(OD)
See Figure 2
See Figure 2

15
20
30
40
ns
ns
PWM Input
Input High Voltage
V
IH(PWM)
3.5
V
Input Low Voltage
V
IL(PWM)
0.8
V
Input Current
I
IL(PWM)
-1
+1
A
High-Side Driver
Output Resistance,
Sourcing Current
V
BST
V
SW
= 12V
1.8
3.0
Output Resistance,
Sinking Current
V
BST
V
SW
= 12V
1.0
2.5
Transition Times
2
t
rDRVH
See Figure 3, V
BST
V
SW
= 12V,
C
LOAD
=3nF
35
45
ns
t
fDRVH
See Figure 3, V
BST
V
SW
= 12V,
C
LOAD
=3nF
20
30
ns
Propagation Delay
2,3
t
pdhDRVH
t
pdlDRVH
See Figure 3, V
BST
V
SW
= 12V
See Figure 3, V
BST
V
SW
= 12V

40
20
65
35
ns
ns
Low-Side Driver
Output Resistance,
Sourcing Current
1.8
3.0
Output Resistance,
Sinking Current
1.0
2.5
Transition Times
2
t
rDRVL
t
fDRVL
See Figure 3, C
LOAD
= 3nF
See Figure 3, C
LOAD
= 3nF

25
21
35
30
ns
ns
Propagation Delay
2,3
t
pdhDRVL
t
pdlDRVL
See Figure 3
See Figure 3
30
10
60
20
ns
ns
FAN53418
REV. 1.0.0 6/11/03
5
Timing Characteristics
Figure 2. Output Disable Timing
Figure 3. Non-overlap Timing Diagram (Timing is referenced to the 90% and 10% points unless otherwise noted)
OD
HDRV/LDRV
VIL(OD)
VIH(OD)
tpdl(OD)
tpdh(OD)
90%
10%
DRVL
IN
DRVH-SW
SW
1V
tf(DRVL)
tr(DRVH)
tpdl(DRVH)
tpdh(DRVH)
tf(DRVH)
tr(DRVL)
tpdh(DRVH)
tpdl(DRVL)
VTH
VTH