2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
HUFA75332G3, HUFA75332P3, HUFA75332S3S
60A, 55V, 0.019 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75332.
Features
60A, 55V
Simulation Models
- Temperature Compensated PSPICE
and SABERTM
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334, "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUFA75332G3
TO-247
75332G
HUFA75332P3
TO-220AB
75332P
HUFA75332S3S
TO-263AB
75332S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUFA75332S3ST.
D
G
S
JEDEC STYLE TO-247
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data Sheet
June 2002
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . V
DSS
55
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . V
DGR
55
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
20
V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
60
Figure 4
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
0.97
W
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V (Figure 11)
55
-
-
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 50V, V
GS
= 0V
-
-
1
A
V
DS
= 45V, V
GS
= 0V, T
C
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
=
20V
-
-
100
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A (Figure 10)
2
-
4
V
Drain to Source On Resistance
r
DS(ON)
I
D
= 60A, V
GS
= 10V (Figure 9)
-
0.016
0.019
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
R
JC
(Figure 3)
-
-
1.03
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-247
-
-
30
o
C/W
TO-220, TO-263
-
-
62
o
C/W
SWITCHING SPECIFICATIONS (V
GS
= 10V)
Turn-On Time
t
ON
V
DD
= 30V, I
D
60A,
R
L
= 0.50
, V
GS
=
10V,
R
GS
= 6.8
-
-
100
ns
Turn-On Delay Time
t
d(ON)
-
12
-
ns
Rise Time
t
r
-
55
-
ns
Turn-Off Delay Time
t
d(OFF)
-
11
-
ns
Fall Time
t
f
-
25
-
ns
Turn-Off Time
t
OFF
-
-
55
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 20V
V
DD
= 30V,
I
D
60A,
R
L
= 0.50
I
g(REF)
= 1.0mA
(Figure 13)
-
70
85
nC
Gate Charge at 10V
Q
g(10)
V
GS
= 0V to 10V
-
40
50
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 2V
-
2.5
3.0
nC
Gate to Source Gate Charge
Q
gs
-
6
-
nC
Reverse Transfer Capacitance
Q
gd
-
15
-
nC
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
1300
-
pF
Output Capacitance
C
OSS
-
480
-
pF
Reverse Transfer Capacitance
C
RSS
-
115
-
pF
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 60A
-
-
1.25
V
Reverse Recovery Time
t
rr
I
SD
= 60A, dI
SD
/dt = 100A/
s
-
-
75
ns
Reverse Recovered Charge
Q
RR
I
SD
= 60A, dI
SD
/dt = 100A/
s
-
-
140
nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
T
C
, CASE TEMPERATURE (
o
C)
P
O
W
E
R DIS
S
IP
A
T
IO
N M
U
L
T
IP
L
I
E
R
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
175
I
D
,
DRAI
N CURR
E
N
T
(
A
)
T
C
, CASE TEMPERATURE (
o
C)
20
40
60
80
50
75
100
125
150
175
0
25
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-5
0.1
1
2
0.01
Z
JC
, NO
RM
AL
IZ
E
D
T
H
E
R
M
A
L
IM
P
E
D
ANCE
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
Typical Performance Curves
(Continued)
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
50
100
1000
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
I
DM
, P
E
AK CURRE
NT
(
A
)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
100
500
10
100
1
1
200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAI
N CURRE
NT
(
A
)
T
J
= MAX RATED
T
C
= 25
o
C
100
s
10ms
1ms
V
DSS(MAX)
= 55V
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
STARTING TJ = 25oC
10
100
0.001
0.01
0.1
1
10
500
t
AV
, TIME IN AVALANCHE (ms)
I
AS
,
AV
AL
ANCHE
CUR
RE
NT
(
A
)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0
30
60
90
120
150
0
1.5
3.0
4.5
6.0
7.5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
T
C
= 25
o
C
I
D
, DRAIN CURRE
NT
(
A
)
V
GS
= 5V
V
GS
= 6V
V
GS
= 10V
V
GS
= 7V
V
GS
= 20V
DUTY CYCLE = 0.5% MAX
0
30
60
90
120
150
0
1.5
3.0
4.5
6.0
7.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 15V
175
o
C
-55
o
C
25
o
C
I
D
, DRAIN CURRE
NT
(
A
)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves
(Continued)
1.0
1.5
2.0
2.5
-40
0
40
80
120
160
200
0.5
-80
NO
RM
AL
IZ
E
D
DRAIN T
O
S
O
URCE
T
J
, JUNCTION TEMPERATURE (
o
C)
O
N
RE
S
I
S
T
ANCE
PULSE DURATION = 80
s
V
GS
= 10V, I
D
= 60A
DUTY CYCLE = 0.5% MAX
0.8
1.0
1.2
-40
0
40
80
120
160
200
0.6
-80
NO
RM
AL
IZ
E
D
G
A
T
E
T
J
, JUNCTION TEMPERATURE (
o
C)
T
HRE
S
H
O
L
D V
O
L
T
A
G
E
V
GS
= V
DS
, I
D
= 250
A
1.0
1.1
1.2
-40
0
40
80
120
160
200
0.9
-80
T
J
, JUNCTION TEMPERATURE (
o
C)
NO
RM
AL
IZ
E
D
DRAIN
T
O
S
O
URCE
I
D
= 250
A
BRE
AKDO
W
N
V
O
L
T
A
G
E
0
500
1000
1500
2000
0
10
20
30
40
50
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C, CAP
A
C
IT
ANCE
(
p
F
)
C
ISS
C
OSS
C
RSS
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
2
4
6
8
10
10
20
30
40
50
60
0
0
V
GS
, G
A
T
E
T
O
S
O
URCE
V
O
L
T
A
G
E
(
V
)
V
DD
= 30V
Q
g
, GATE CHARGE (nC)
I
D
= 60A
I
D
= 45A
I
D
= 30A
I
D
= 15A
WAVEFORMS IN
DESCENDING ORDER:
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
G(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
V
GS
= 10V
Q
g(TOT)
V
GS
= 20V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
PSPICE Electrical Model
.SUBCKT HUFA75332 2 1 3 ;
rev 18 June 2002
CA 12 8 1.8e-9
CB 15 14 1.73e-9
CIN 6 8 1.19e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 58.85
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 1e-9
LSOURCE 3 7 1e-9
K1 LSOURCE LGATE 0.0085
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 4.5e-3
RGATE 9 20 1.3
RLDRAIN 2 5 10
RLGATE 1 9 10
RLSOURCE 3 7 10
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.95e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),4.6))}
.MODEL DBODYMOD D (IS = 1.3e-12 RS = 3.0e-3 IKF = 20 XTI = 6 TRS1 = 2.7e-3 TRS2 = 7.0e-7 CJO = 1.7e-9 TT = 4.0e-8 M = 0.45 vj = 0.75)
.MODEL DBREAKMOD D (RS = 1.71e-2 IKF = 1.0e-5 TRS1 = -4.0e-4 TRS2 = -1.55e-5)
.MODEL DPLCAPMOD D (CJO = 1.8e-9 IS = 1e-30 N = 1 M = 0.9 vj = 1.45)
.MODEL MMEDMOD NMOS (VTO = 3.183 KP = 2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.3)
.MODEL MSTROMOD NMOS (VTO = 3.66 KP = 51.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.703 KP = 0.008 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 13)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = 4.5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.16e-2 TC2 = 1.7e-5)
.MODEL RSLCMOD RES (TC1 = 3.96e-3 TC2 = 2.7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -1.0e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.75e-3 TC2 = 5.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8 VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= 0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
SABER Electrical Model
REV 18 June 2002
template hufa75332 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 1.3e-12, xti = 6, cjo = 1.7e-9, tt = 4.0e-8, m = 0.45, vj = 0.75)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.8e-9, is = 1e-30, m = 0.9, vj = 1.45)
m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.703, kp = 8.0e-3, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8, voff = -3)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -8)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0)
c.ca n12 n8 = 1.8e-9
c.cb n15 n14 = 1.73e-9
c.cin n6 n8 = 1.19e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 1.0e-9
l.lsource n3 n7 = 1.0e-9
k.kl i (l.lgate) i (l.lsource) = l (l.lgate), l (l.lsource), 0.0085
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 4.5e-7
res.rdbody n71 n5 = 3.0e-3, tc1 = 2.7e-3, tc2 = 7.0e-7
res.rdbreak n72 n5 = 1.71e-2, tc1 = -4.0e-4, tc2 = -1.55e-5
res.rdrain n50 n16 = 4.5e-3, tc1 = 1.16e-2, tc2 = 1.7e-5
res.rgate n9 n20 = 1.3
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 10
res.rlsource n3 n7 = 10
res.rslc1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.95e-3, tc1 = 1e-3, tc2 = 1e-5
res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 5.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -1.0e-5
spe.ebreak n11 n7 n17 n18 = 58.85
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4.6))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17
18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUFA75332G3, HUFA75332P3, HUFA75332S3S
2002 Fairchild Semiconductor Corporation
HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
SPICE Thermal Model
REV 18June
2002
HUFA75332
CTHERM1 th 6 4.00e-3
CTHERM2 6 5 7.00e-3
CTHERM3 5 4 7.50e-3
CTHERM4 4 3 8.00e-3
CTHERM5 3 2 1.85e-2
CTHERM6 2 tl 12.55
RTHERM1 th 6 7.09e-3
RTHERM2 6 5 1.77e-2
RTHERM3 5 4 4.97e-2
RTHERM4 4 3 2.79e-1
RTHERM5 3 2 4.21e-1
RTHERM6 2 tl 5.58e-2
SABER Thermal Model
SABER thermal model HUFA75332
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.00e-3
ctherm.ctherm2 6 5 = 7.00e-3
ctherm.ctherm3 5 4 = 7.50e-3
ctherm.ctherm4 4 3 = 8.00e-3
ctherm.ctherm5 3 2 = 1.85e-2
ctherm.ctherm6 2 tl = 12.55
rtherm.rtherm1 th 6 = 7.09e-3
rtherm.rtherm2 6 5 = 1.77e-2
rtherm.rtherm3 5 4 = 4.97e-2
rtherm.rtherm4 4 3 = 2.79e-1
rtherm.rtherm5 3 2 = 4.21e-1
rtherm.rtherm6 2 tl = 5.58e-2
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
HUFA75332G3, HUFA75332P3, HUFA75332S3S
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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