2003 Fairchild Semiconductor Corporation
DS006330
www.fairchildsemi.com
December 1986
Revised July 2003
DM74AS873
Dual
4-
Bit
D-
T
y
pe T
r
anspare
n
t
Latch
es wi
th
3-ST
A
T
E Out
puts
DM74AS873
Dual 4-Bit D-Type Transparent Latches
with 3-STATE Outputs
General Description
These dual 4-bit registers feature totem-pole 3-STATE out-
puts designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driv-
ing the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The eight latches of the DM74AS873 are transparent D-
type latches meaning that while the enable (G) is HIGH the
Q outputs will follow the data (D) inputs. When the enable
is taken LOW the output will be latched at the level of the
data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all out-
puts are on the other side.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
3-STATE buffer-type outputs drive bus lines directly
s
Space Saving 300 Mil Wide Package
s
Bus structured pinout
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Order Number
Package Number
Package Description
DM74AS873NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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2
DM
74AS873
Function Table
L
=
LOW State
H
=
HIGH State
X
=
Don't Care
Z
=
High Impedance State
Q
0
=
Previous Condition of Q
Logic Diagram
Inputs
Output
CLR
D
EN
OC
Q
X
X
X
H
Z
L
X
X
L
L
H
H
H
L
H
H
L
H
L
L
H
X
L
L
Q
0
3
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DM74AS873
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: The (
) arrow indicates the negative edge of the enable is used for reference.
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C.
Note 3: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit current, I
OS
.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
47.0
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
48
mA
t
W
Pulse Width
Enable HIGH
5.5
ns
Clear LOW
3.5
t
SU
Data Setup Time (Note 2)
2
ns
t
H
Data Hold Time (Note 2)
3
ns
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
4.5V, V
IL
=
Max
2.4
3.3
V
Output Voltage
I
OH
=
Max
I
OH
=
-
2 mA, V
CC
=
4.5V to 5.5V
V
CC
-
2
V
V
OL
LOW Level
V
CC
=
4.5V, V
IH
=
2V
0.35
0.5
V
Output Voltage
I
OL
=
Max
I
I
Input Current at Max
V
CC
=
5.5V, V
IH
=
7V
0.1
mA
Input Voltage
I
IH
HIGH Level Input Current
V
CC
=
5.5V, V
IH
=
2.7V
20
A
I
IL
LOW Level Input Current
V
CC
=
5.5V, V
IL
=
0.4V
-
0.5
mA
I
O
(Note 3)
Output Drive Current
V
CC
=
5.5V, V
O
=
2.25V
-
30
-
112
mA
I
OZH
OFF-State Output Current,
V
CC
=
5.5V, V
IH
=
2V
50
A
HIGH Level Voltage Applied
V
O
=
2.7V
I
OZL
OFF-State Output Current,
V
CC
=
5.5V, V
IH
=
2V
-
50
A
LOW Level Voltage Applied
V
O
=
0.4V
I
CC
Supply Current
V
CC
=
5.5V
Outputs HIGH
68
110
mA
Outputs Open
Outputs LOW
67
109
mA
Outputs Disabled
80
129
mA
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4
DM
74AS873
Switching Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C.
Symbol
Parameter
Conditions
From
To
Min
Max
Units
t
PLH
Propagation Delay Time
V
CC
=
4.5V to 5.5V
Data
Any Q
3
6.5
ns
LOW-to-HIGH Level Output
R
L
=
500
t
PHL
Propagation Delay Time
C
L
=
50 pF
Data
Any Q
3
6
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Enable
Any Q
6
11.5
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Enable
Any Q
4
7.5
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time
Output Control
Any Q
2
6.5
ns
to HIGH Level Output
t
PZL
Output Enable Time
Output Control
Any Q
4
9.5
ns
to LOW Level Output
t
PHZ
Output Disable Time
Output Control
Any Q
2
6.5
ns
from HIGH Level Output
t
PLZ
Output Disable Time
Output Control
Any Q
2
7.5
ns
from LOW Level Output
t
PHL
Propagation Delay Time
Clear
Any Q
3
8.5
ns
HIGH-to-LOW Level Output
5
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DM74AS873
Dual
4-
Bit
D-
T
y
pe T
r
anspare
n
t
Latch
es wi
th
3-ST
A
T
E Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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