www.fairchildsemi.com
REV. 1.02 11/24/99
Features
8-bit resolution
80, 50, and 30 megapixels per second
0.5 LSB linearity error
Sync, blank, and white controls
Independent sync current output
1.0V p-p video into 37.5
or 75
load
Enhancemenet of ADV7120
Internal bandgap voltage reference
Double-buffered data for low distortion
Power-down sleep mode
Double-buffered data for low distortion
TTL-compatible inputs
Low glitch energy
Single +5 Volt power supply
Applications
Video signal conversion
RGB
YC
B
C
R
Composite, Y, C
Multimedia systems
Image processing
True-color graphics systems
Broadcast television equipment
High-Definition Television (HDTV) equipment
Direct digital synthesis
Description
The TMC3503 is a high-speed triple 8-bit D/A converter
especially suited for video and graphics applications.
It offers 8-bit resolution, TTL-compatible inputs, low power
consumption, a power-down sleep mode, and requires only a
single +5 Volt power supply. It has single-ended current
outputs, SYNC and BLANK control inputs, and a separate
current source for adding sync pulses to any D/A converter
output. WHITE and SLEEP control inputs are available on
PLCC parts. It is ideal for generating analog RGB from
digital RGB and driving computer display and video moni-
tors. Three speed grades are available: 30, 50, and 80 Msps.
The TMC3503 triple D/A converter is available in a 44-lead
plastic J-leaded PLCC. It is also available in a 48-lead plastic
LQFP package. It is fabricated on a sub-micron CMOS
process with performance guaranteed from 0C to 70C.
Block Diagram
8 bit D/A
Converter
SYNC
8
SYNC
CLOCK
SLEEP [PLCC only]
IO
S
G
7-0
COMP
65-3503-01
+1.235V
Ref
IO
G
BLANK
8 bit D/A
Converter
8
B
7-0
IO
B
8 bit D/A
Converter
8
R
7-0
IO
R
R
REF
V
REF
WHITE [PLCC only]
[LQFP only]
TMC3503
Triple Video D/A Converter
8 bit, 80 Msps, 5V
TMC3503
PRODUCT SPECIFICATION
2
REV. 1.02 11/24/99
Functional Description
The TMC3503 is a low-cost triple 8-bit CMOS D/A con-
verter designed to directly drive computer CRT displays at
pixel rates up to 80 Msps. It comprises three identical 8-bit
D/A converters with registered data inputs, common clock,
and internal voltage reference. An independent current
source allows sync to be added to any D/A converter output.
Digital Inputs
All digital inputs are TTL-compatible. Data are registered on
the rising edge of the CLK signal. The analog output
changes t
DO
after the rising edge of CLK. There is one stage
of pipeline delay on the chip. The guaranteed clock rates of
the TMC3503 are 80, 50, and 30 MHz.
SYNC and BLANK
SYNC and BLANK inputs control the output level
(Figure 1 and Table 1) of the D/A converters during CRT
retrace intervals. BLANK forces the D/A outputs to the
blanking level while SYNC turns off a separate current
source which is brought off the chip through the IO
S
pin.
Figure 1. Nominal Output Levels
IO
S
may be connected to any one D/A output, or used inde-
pendently. It is commonly tied to the green D/A converter for
"Sync on Green" operation. This connection adds a 40 IRE
sync pulse to the D/A output and brings that D/A output to
0.0 Volts during the sync tip. SYNC and BLANK are regis-
tered on the rising edge of CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = LOW, data
inputs and the pedestal are disabled.
WHITE
The WHITE control drives all three D/As to full-scale, over-
riding the data inputs. It is overridden by the BLANK input,
and is independent of SYNC.
data: 660 mV max.
65-3503-02
pedestal: 54 mV
sync: 286 mV
SLEEP
The SLEEP control, when HIGH, places the TMC3503 in a
power-down state. This function operates asynchronously.
D/A Outputs
Each D/A output is a current source. To obtain a voltage out-
put, a resistor must be connected to ground. Output voltage
depends upon this external resistor, the reference voltage,
and the value of the gain-setting resistor connected between
R
REF
and GND.
Normally, a source termination resistor of 75 Ohms is con-
nected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm coaxial cable may then be con-
nected with another 75 Ohm termination resistor at the far
end of the cable. This "double termination" presents the D/A
converter with a net resistive load of 37.5 Ohms.
The TMC3503 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
desired range, the value of the resistor on R
REF
should be
increased.
Voltage Reference
The TMC3503 has an internal bandgap voltage reference of
+1.235 Volts. An external voltage reference may be con-
nected to the V
REF
pin, overriding the internal voltage refer-
ence. All three D/A converters are driven from the same
reference.
A 0.1F capacitor must be connected between the COMP
pin and V
DD
to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
The TMC3503 D/A converter requires a single +5.0 Volt
power supply. The analog (V
DD
) power supply voltage
should be decoupled to GND to reduce power supply
induced noise. 0.1F decoupling capacitors should be placed
as close as possible to the power pins.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distor-
tion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
PRODUCT SPECIFICATION
TMC3503
REV. 1.02 11/24/99
3
Table 1. Output Voltage versus Input Code, SYNC, BLANK, and WHITE
V
REF
= 1.235 V, R
REF
= 590
, R
L
= 37.5
Pin Assignments
Notes (LQFP Package Only):
1. Pin functions White and Sleep are not available.
2. IO
S
function is tied internally to IO
G
pin.
RGB7-0
(MSB...LSB)
All D/As
D/A with IOS Connected
SYNC
BLANK
WHITE
V
OUT
SYNC
BLANK
WHITE
V
OUT
XXXX XXXX
X
1
1
0.714
1
1
1
1.000
1111 1111
X
1
0
0.714
1
1
0
1.000
1111 1110
X
1
0
0.711
1
1
0
0.997
1111 1101
X
1
0
0.709
1
1
0
0.995
0000 0000
X
1
0
0.385
1
1
0
0.671
1111 1111
X
1
0
0.383
1
1
0
0.669
0000 0010
X
1
0
0.059
1
1
0
0.345
0000 0001
X
1
0
0.057
1
1
0
0.343
0000 0000
X
1
0
0.054
1
1
0
0.340
XXXX XXXX
X
0
X
0.000
1
0
X
0.286
XXXX XXXX
X
0
X
0.000
0
0
X
0.000
65-3503-03
G
0
G
1
G
2
G
3
G
4
G
5
G
6
G
7
BLANK
SYNC
V
DD
R
REF
V
REF
COMP
IO
R
IO
G
IO
S
V
DD
V
DD
V
DD
IO
B
GND
GND
GND
GND
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
CLK
WHITE
SLEEP
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
TMC3503
PLCC Package
65-3503-06
GND
G
0
G
1
G
2
G
3
G
4
G
5
G
6
G
7
BLANK
V
DD
R
0
GND
NC
R
REF
V
REF
COMP
IO
G
IO
R
OV
DD
V
DD
IO
B
GND
GND
NC
GND R
7
R
6
R
5
R
4
R
3
R
2
R
1
NC
GND
GND
B
0
B
1
B
2
B
3
B
4
B
6
B
5
NC
1
2
3
4
5
6
7
8
9
10
SYNC
11
12
36
35
34
33
32
31
30
29
28
27
CLOCK
26
25
13
14
15
16
17
18
19
20
21
22
B
7
23
24
48
47
46
45
44
43
42
41
40
39
GND
38
37
TMC3503
LQFP Package
TMC3503
PRODUCT SPECIFICATION
4
REV. 1.02 11/24/99
Pin Descriptions
Pin
Name
Pin Number
Value
Pin Function Description
LQFP
PLCC
Clock and Pixel I/O
CLK
26
27
TTL
Clock Input. The clock input is TTL-compatible and all pixel
data is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid reflection
induced jitter, overshoot, and undershoot.
R
7-0
G
7-0
B
7-0
47-40
9-2
23-16
6-1, 44-43
14-7
25-18
TTL
Red, Green, and Blue Pixel Inputs. The R, G, and B digital
inputs are TTL-compatible and registered on the rising edge of
CLK.
Controls
SYNC
11
16
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE
(7.62 mA) current source which forms a sync pulse on any D/A
converter output connected to IO
S
. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during the
blanking interval. If the system does not require sync pulses,
SYNC and IO
S
should be connected to GND.
BLANK
10
15
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored
and the D/A converter outputs are driven to the blanking level.
BLANK is registered on the rising edge of CLK and has the
same two-pipe latency as SYNC and Data.
WHITE
--
26
TTL
Force Full Scale Input. When WHITE is HIGH, pixel inputs are
ignored and the D/A converter outputs are driven to their full-
scale output level. A BLANK input overwrites a WHITE input.
WHITE is register on the rising edge of CLK and has the same
two-pipe latency as SYNC and Data.
SLEEP
--
28
TTL
Power-down Control Input. When HIGH, SLEEP places the D/
A converter in a low-power-dissipation mode. The D/A current
sources and the digital processing are disabled. The last data
loaded into the input and D/A registers is retained. This control is
asynchronous.
Video Outputs
IO
R
IO
G
IO
B
33
32
29
39
38
33
0.714 V
p-p
Red, Green, and Blue Data Outputs. The current source
outputs of the D/A converters are capable of driving RS-343A/
SMPTE-170M compatible levels into doubly-terminated 75 Ohm
lines. Sync pulses may be added to any D/A output.
IO
S
32
(connected
to IO
G
)
37
0.714 V
p-p
SYNC Current Output. When this pin is connected to any of the
D/A converter outputs, a 40 IRE offset is added to the video
level. When the SYNC input is LOW, the current is turned off,
bring the sync tip voltage to 0.0V. If no sync pulse is required,
IO
S
should be grounded. When SYNC is HIGH, the current
flowing out of IO
S
is:
IO
S
= 3.64 (V
REF
/ R
REF
)
Voltage Reference
V
REF
35
41
+1.235 V
Voltage Reference Input/Output. An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt
reference may be applied here which overrides the internal
reference. Decoupling V
REF
to GND with a 0.1F ceramic
capacitor is required.
PRODUCT SPECIFICATION
TMC3503
REV. 1.02 11/24/99
5
Equivalent Circuits
Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit
R
REF
36
42
590
Current-setting Resistor. The full-scale output current of each
D/A converter is determined by the value of the resistor
connected between R
REF
and GND. The nominal value for
R
REF
is found from:
R
REF
= 9.1 (V
REF
/I
FS
)
where I
FS
is the full-scale (white) output current (amps) from the
D/A converter (without sync). Sync is 0.4 I
FS
.
D/A full-scale (white) current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
FS
is the white voltage level and R
L
is the total resistive
load (ohms) on each D/A converter. V
FS
is the blank to full-scale
voltage.
COMP
34
40
0.1 F
Compensation Capacitor. A 0.1 F ceramic capacitor must be
connected between COMP and V
DD
to stabilize internal bias
circuitry.
Power, Ground
V
DD
12, 30, 31 17, 3436
+5 V
Power Supply.
GND
1, 14, 15,
27, 28, 38,
39, 48
2932
0.0V
Ground.
NC
13, 24, 25,
37
--
--
No Connect
Pin
Name
Pin Number
Value
Pin Function Description
LQFP
PLCC
n
p
OUT
GND
27013B
V
DD
V
DD
Digital
Input
V
DD
p
n
27014D
GND
Pin Descriptions
(continued)
TMC3503
PRODUCT SPECIFICATION
6
REV. 1.02 11/24/99
Equivalent Circuits
(continued)
Figure 4. Equivalent Analog Input Circuit
Absolute Maximum Ratings
(beyond which the device may be damaged)
1
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Parameter
Min
Typ
Max
Unit
Power Supply Voltage
V
DD
(Measured to GND)
-0.5
7.0
V
Inputs
Applied Voltage (measured to GND)
2
-0.5
V
DD
+ 0.5
V
Forced Current
3,4
-10.0
10.0
mA
Outputs
Applied Voltage (measured to GND)
2
-0.5
V
DD
+ 0.5
V
Forced Current
3,4
-60.0
60.0
mA
Short Circuit Duration (single output in HIGH state to ground)
infinite
second
Temperature
Operating, Ambient
-20
110
C
Junction
150
C
Lead Soldering (10 seconds)
300
C
Vapor Phase Soldering (1 minute)
220
C
Storage
-65
150
C
p
GND
27012B
R
REF
V
REF
V
DD
p
PRODUCT SPECIFICATION
TMC3503
REV. 1.02 11/24/99
7
Operating Conditions
Electrical Characteristics
Notes:
1. Values shown in Typ column are typical for V
DD
= +5V and T
A
= 25C
2. Minimum/Maximum values with V
DD
= Max and T
A
= Min
3. V
REF
= 1.235V, R
LOAD
= 37.5
, R
REF
= 590
Parameter
Min
Nom
Max
Units
V
DD
Power Supply Voltage
4.75
5.0
5.25
V
f
S
Conversion Rate
TMC3503-30
30
Msps
TMC3503-50
50
Msps
TMC3503-80
80
Msps
t
PWH
CLK Pulsewidth, HIGH
4
ns
t
PWL
CLK Pulsewidth, LOW
4
ns
t
s
Input Data Setup Time
3
ns
t
h
Input Date Hold Time
2
ns
V
REF
Reference Voltage, External
1.0
1.235
1.5
V
C
C
Compensation Capacitor
0.1
F
R
L
Output Load
37.5
V
IH
Input Voltage, Logic HIGH
2.0
V
DD
V
V
IL
Input Voltage, Logic LOW
GND
0.8
V
T
A
Ambient Temperature, Still Air
0
70
C
Parameter
Conditions
3
Min
Typ
1
Max
Units
I
DD
Power Supply Current
2
V
DD
= Max
TMC3503-30
TMC3503-50
TMC3503-80
100
100
125
mA
mA
mA
I
DDS
Power Supply Current,
Sleep Mode
V
DD
= Max
3
mA
PD
Total Power Dissipation
2
V
DD
= Max
TMC3503-30
TMC3503-50
TMC3503-80
525
525
655
mW
mW
mW
R
O
Output Resistance
100
k
C
O
Output Capacitance
I
OUT
= 0mA
30
pF
I
IH
Input Current, HIGH
V
DD
= Max, V
IN
= 2.4V
-1
A
I
IL
Input Current, LOW
V
DD
= Max, V
IN
= 0.4V
1
A
I
REF
V
REF
Input Bias Current
0
100
A
V
REF
Reference Voltage Output
1.235
V
V
OC
Output Compliance
Referred to V
DD
-0.4
0
+1.5
V
C
DI
Digital Input Capacitance
4
10
pF
TMC3503
PRODUCT SPECIFICATION
8
REV. 1.02 11/24/99
Switching Characteristics
Notes:
1. Values shown in Typ column are typical for V
DD
= +5V and T
A
= 25C.
2. V
REF
= 1.235V, R
LOAD
= 37.5
, R
REF
= 590
.
System Performance Characteristics
Notes:
1. Values shown in Typ column are typical for V
DD
= +5V and T
A
= 25C.
2. V
REF
= 1.235V, R
LOAD
= 37.5
, R
REF
= 590
.
Timing Diagram
Parameter
Conditions
2
Min
Typ
1
Max
Units
t
D
Clock to Output Delay
V
DD
= Min
10
15
ns
t
SKEW
Output Skew
1
2
ns
t
R
Output Risetime
10% to 90% of Full Scale
2
3
ns
t
F
Output Falltime
90% to 10% of Full Scale
2
3
ns
t
SET
Output Settling Time
to 3%/FS
15
ns
Parameter
Conditions
2
Min
Typ
1
Max
Units
E
LI
Integral Linearity Error
V
DD
, V
REF
= Nom
0.2
0.3
%/FS
E
LD
Differential Linearity Error
V
DD
, V
REF
= Nom
0.2
0.3
%/FS
E
DM
DAC to DAC Matching
V
DD
, V
REF
= Nom
3
10
%
E
G
Absolute Gain Error
V
DD
, V
REF
= Nom
TBD
%/FS
TC
EG
Gain Error Tempco
V
DD
, V
REF
= Nom
TBD
PPM/C
I
OFF
Output Off Current
V
DD
= Max, R, G, B = 000h
SYNC = BLANK = 0
20
nA
PSRR
Power Supply Rejection
Ratio
0.05
%/%
CLK
PIXEL DATA
& CONTROLS
OUTPUT
65-3503-04
DataN
DataN+1
DataN+2
tPWL
tS
tH
50%
3%/FS
90%
10%
tD
tSET
tF
tR
tPWH
1/fS
PRODUCT SPECIFICATION
TMC3503
REV. 1.02 11/24/99
9
Application Notes
Figure 4 illustrates a typical TMC3503 interface circuit. In
this example, an optional 1.2 Volt bandgap reference is con-
nected to the V
REF
output, overriding the internal voltage
reference source.
Grounding
It is important that the TMC3503 power supply is well-regu-
lated and free of high-frequency noise. Careful power supply
decoupling will ensure the highest quality video signals at
the output of the circuit. The TMC3503 has separate analog
and digital circuits. To keep digital system noise from the
D/A converter, it is recommended that power supply voltages
(V
DD
) come from the system analog power source and all
ground connections (GND) be made to the analog ground
plane. Power supply pins should be individually decoupled
at the pin.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following sug-
gestions when doing the layout:
1.
Keep the critical analog traces (V
REF
, I
REF
, COMP,
IO
S
, IO
R
, IO
G
, IO
B
) as short as possible and as far as
possible from all digital signals. The TMC3503 should
be located near the board edge, close to the analog out-
put connectors.
2.
The power plane for the TMC3503 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the V
DD
pins. If
the power supply for the TMC3503 is the same as that of
the system's digital circuitry, power to the TMC3503
should be decoupled with 0.1F and 0.01F capacitors
and isolated with a ferrite bead.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the TMC3503, the
voltage reference, or the analog outputs. Capacitive cou-
pling of digital power supply noise from this layer to the
TMC3503 and its related analog circuitry can have an
adverse effect on performance.
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Figure 4. Typical Interface Circuit
65-3503-05
R7-0
G7-0
B7-0
+5V
0.1
F
10
F
VDD
GND
TMC3503
Triple 8-bit
D/A Converter
CLK
SYNC
BLANK
RED PIXEL
INPUT
GREEN PIXEL
INPUT
BLUE PIXEL
INPUT
CLOCK
SYNC
BLANK
COMP
VREF
RREF
WHITE
WHITE
SLEEP
SLEEP
+5V
0.1
F
0.1
F
590
3.3k
LM185-1.2
(Optional)
IOR
IOS
IOG
IOB
75
75
75
75
75
75
ZO=75
ZO=75
ZO=75
Red
Green w/Sync
Blue
TMC3503
PRODUCT SPECIFICATION
10
REV. 1.02 11/24/99
Related Products
TMC3003 Triple 10-bit 80 Msps D/A Converter
TMC1175A 40 Msps CMOS 8-bit A/D Converter
TMC1275 40 Msps CMOS 8-bit A/D Converter
TMC22091, TMC22191 Digital Video Encoders
TMC2242A/TMC2243/TMC2246A Video Filters
TMC2249A Digital Mixer
TMC2250A Matrix Multiplier
TMC2272A Colorspace Converter
TMC2302 Image Manipulation Sequencer
TMC2340A Digital Synthesizer
TMC2081 Digital Video Mixer
PRODUCT SPECIFICATION
TMC3503
REV. 1.02 11/24/99
11
Notes:
TMC3503
PRODUCT SPECIFICATION
12
REV. 1.02 11/24/99
Mechanical Dimensions 44-pin PLCC Package
D
e
E
A
.165
.180
4.19
4.57
Symbol
Inches
Min.
Max.
Min.
Max.
Millimeters
Notes
E1
J
D1
A
A1
A2
B
B1
D3/E3
J
C
ccc C
LEAD COPLANARITY
A1
.090
.120
2.29
3.05
A2
.020
.51
--
--
B
.013
.021
.33
.53
D/E
.685
.695
17.40
17.65
D1/E1
.650
.656
16.51
16.66
D3/E3
.500 BSC
12.7 BSC
e
.050 BSC
1.27 BSC
J
.042
.056
1.07
1.42
2
3
ND/NE
11
11
N
44
44
ccc
.004
0.10
--
--
B1
.026
.032
.66
.81
Notes:
1.
2.
3.
All dimensions and tolerances conform to ANSI Y14.5M-1982
Corner and edge chamfer (J) = 45
Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
PRODUCT SPECIFICATION
TMC3503
REV. 1.02 11/24/99
13
Mechanical Dimensions 48-pin LQFP Package
D
E1
E
e
PIN 1
IDENTIFIER
B
Base Plane
Seating Plane
See Lead Detail
C
0.063" Ref (1.60mm)
L
-C-
ccc
C
LEAD COPLANARITY
A2
A
A1
A
.055
.063
1.40
1.60
Symbol
Inches
Min.
Max.
Min.
Max.
Millimeters
Notes
A1
.001
.005
.05
.15
.057
1.45
A2
.053
1.35
B
.006
.010
.17
.27
D/E
D1/E1
.019 BSC
.346
.362
8.8
9.2
.268
.284
6.8
7.2
.50 BSC
e
L
.017
.029
.45
.75
6
4
5
2
7
8
0
7
0
7
N
48
48
12
12
ND
ccc
.004
0.08
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
D1
All dimensions and tolerances conform to ANSI Y14.5M-1982.
Dimensions "D1" and "E1" do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
Pin 1 identifier is optional.
Dimension ND: Number of terminals.
Dimension ND: Number of terminals per package edge.
"L" is the length of terminal for soldering to a substrate.
Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed the
maximum B dimension by more than 0.08mm. Dambar can not be
located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm
pitch packages.
To be determined at seating place --C--
TMC3503
PRODUCT SPECIFICATION
11/24/99 0.0m 005
Stock#DS30003503
1998 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Ordering Information
Product Number
Conversion
Rate (Msps)
Temperature Range
Screening
Package
Package
Marking
TMC3503R2C30
30 Msps
T
A
= 0C to 70C
Commercial
44-Lead PLCC
3503R2C30
TMC3503R2C50
50 Msps
T
A
= 0C to 70C
Commercial
44-Lead PLCC
3503R2C50
TMC3503R2C80
80 Msps
T
A
= 0C to 70C
Commercial
44-Lead PLCC
3503R2C80
TMC3503KRC30
30 Msps
T
A
= 0C to 70C
Commercial
48-Lead LQFP
3503KRC30
TMC3503KRC50
50 Msps
T
A
= 0C to 70C
Commercial
48-Lead LQFP
3503KRC50
TMC3503KRC80
80 Msps
T
A
= 0C to 70C
Commercial
48-Lead LQFP
3503KRC80
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