Preliminary
2005 Fairchild Semiconductor Corporation
DS500923
www.fairchildsemi.com
June 2005
Revised June 2005
USB1
101
USB 2.
0
FS Per
i
pher
al
T
r
a
nsceiv
e
r
(Prel
i
m
i
nary)
USB1101
USB 2.0 FS Peripheral Transceiver (Preliminary)
General Description
The USB1101 provides a USB FS Transceiver functionality
with voltage level translation that is compliant to USB Spec-
ification Rev 2.0. The device allows interfacing of USB
Application specific devices with supply voltages ranging
from 1.65V to 3.6V with the physical layer of Universal
Serial Bus. It is capable of operating at 12Mbits/s (full
speed) data rates and hence is fully compliant to USB
Specification Rev 2.0. It supports the DAT_VP/SE0_VM
interface on the host side but offers reduced pin count and
package size. The USB1101 has host side supply rail for
1.65V to 3.6V.
Features
s
Complies with USB Specification Rev 2.0
s
Supports DAT_VP/SE0_VM host mode
s
Utilizes digital inputs and outputs to transmit and receive
USB cable data
s
Supports full speed (12Mbits/s) data rates
s
Ideal for portable electronic devices
s
MicroPak
technology package (10 pin)
1.6mm x 2.1mm
s
Host side V
CCIO
1.65V to 3.6V
Applications
PDA
PC Peripherals
Cellular Phones
MP3 Players
Digital Cameras
Information Appliance
Ordering Code:
Connection Diagram
(Bottom View)
MicroPak
is a trademark of Fairchild Semiconductor Corporation.
Order
Package
Package
Package Description
Supplied As
Number
Number
Top Mark
USB1101L10X
MAC010A
UB
10-Lead MicroPak, 1.6 mm x 2.1mm 5k Units on Tape and Reel
Preliminary
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2
USB1
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Pin Description
Note 1: OE
H
Note 2: OE
L
Functional Description
The USB1101 transceiver is designed as an Upstream fac-
ing port device to convert CMOS data into USB differential
bus signal levels and to convert USB differential bus signal
to CMOS data. If you wish to use these as downstream
devices, Config must be hard-wired to GND.
To minimize EMI and noise the outputs are edge rate con-
trolled with the rise and fall times controlled and defined for
full speed data rates only (12Mbits/s). The rise and fall
times are balanced between the differential pins to mini-
mize skew.
The USB1101 supports the DAT_VP/SE0_VM format from
the OTG Transceiver Specification using the DAT_SE0
Mode. Table 1 describes the specific pin functionality selec-
tion and Table 2 describes the specific Truth Tables for
Driver, Receiver, and Suspended operating functions.
The USB1101 has the capability of serving Self Powered
power supply configurations only but interfaces to mixed
voltage supply applications.
TABLE 1. Function Select
Note 3: Signal levels is function of connection, Config and/or pull-up/pull-down resistors.
Note 4: For Suspnd
HIGH mode the differential receiver is inactive.
Pin Number
Pin Name
I/O
Pin Description
1
Config
I
USB connect or disconnect software control input. Configures 3.3V to
internal 1.5k
:
resistor on D
when HIGH. If device is used as Downstream
port then this pin is hard-wired to GND.
2
OE
I
Output Enable (active LOW)
When OE
L transmit mode is enabled
When OE
H receive mode (CMOS level is relative to V
CCIO
) is enabled.
3
DAT_VP
I/O
When in transmit mode
(Note 2)
DAT_VP is a single-ended host data input
(CMOS level relative to V
CCIO
).
When in receive mode
(Note 1)
and Suspnd
L DAT_VP is a single ended
data output comprised of the differential input data from the D
/D
inputs
(see Table 2);
When in receive mode
(Note 1)
with Suspnd
H DAT_VP outputs the D
data.
(see Table 1 and Table 2) Output drive is 2mA (min) buffer
4
SE0_VM
I/O
When in transmit mode
(Note 2)
SE0_VM is a data input (CMOS level rela-
tive to V
CCIO
).
When in receive mode
(Note 1)
and Suspnd
L, SE0_VM is used as an out-
put (see Table 2)
(see Table 1 and Table 2). Output drive is 4ma (min) buffer
5
GND
GND
GND
6
Suspnd
I
Enables a low power state (CMOS level is relative to V
CCIO
).
In receive mode
(Note 1)
with Suspnd
L the DAT_VP pin will be a function
of the D
/D
lines.
In receive mode
(Note 1)
with Suspnd
H DAT_VP will have the value of D
such that the device can still monitor out-of-suspend signaling.
7, 8
D
, D
AI/O
Data
, Data
. Differential data bus conforming to the USB standard
9
V
CCIO
Pwr
Supply Voltage for host side digital I/O pins (1.65V to 3.6V)
10
V
CC
Pwr
Supply Voltage Input (3.0V to 3.6V)
Suspnd
OE
D
, D
DAT_VP
SE0_VM
Function
L
L
Transmitting
Host Data Input
SE0_VM Host Input
Normal Driving
L
H
Receiving (Note 3)
D
, D
Diff Output
SE0_VM Output
Receiving
H
L
Transmitting (Note 4)
Host Data Input
SE0_VM Host Input
Driving while Suspended
H
H
Driver is 3-STATE
(Note 4)
DAT_VP Output
SE0_VM Output
Suspended
(Internal Low Power Mode)
Preliminary
3
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USB1
101
TABLE 2. Driver, Receiver, and Suspend Function Select
Note 5: DIFF denotes that the output of the differential receiver is output via DAT_VP when Suspnd
L. This output should also not be gated by the SE0 or
SE1 condition when a skew between D
and D
signals could result in the short SE0 or SE1 conditions. Please refer to Expectation Notes for further infor-
mation.
Note 6: This is the internal single ended output that is output on to DAT_VP when Suspnd
H and in receive mode.
Power Supply Configurations and Options
The modes of power supply operation include:
1. Self Powered Mode:
V
CC
is connected to 3.3V source
(3.0V to 3.6V). This external supply connection pro-
vides the 3.3V for the USB pull-up source, the receiver
input and driver output circuitry.
2. Sharing Mode:
V
CCIO
is connected and V
CC
is
d
0.8V.
In this mode the D
and D
pins are 3-STATE and the
USB1101 allows external signals up to 3.6V to share
the D
and D
bus lines. Internally the circuitry limits
leakage from D
and D
pins (maximum 10
P
A) and
V
CCIO
such that the device is in low power state.
3. Disable Mode:
V
CCIO
is
d
0.5V and V
CC
is connected.
In this mode the D
and D
pins are 3-STATE and the
device is in low power state.
A summary of the Supply Configuration is described in
Table 3.
TABLE 3. Power Supply Configuration Options
Suspnd
L
Transmit Mode
Inputs
Outputs
OE
DAT_VP
SEO_VM
D
D
L
L
L
L
H
Differential Logic 0
L
H
L
H
L
Differential Logic 1
L
L
H
L
L
SE0
L
H
H
L
L
SE0
Suspnd
L
Receive Mode
Inputs
Outputs
OE
D
D
DAT_VP
SEO_VM
H
L
L
DIFF (Note 5)
H
H
H
L
H
L
H
L
H
L
L
H
H
H
DIFF (Note 5)
L
Suspnd
L
Receive Mode
While Suspended
Inputs
Outputs
OE
D
D
DAT_VP
SEO_VM
H
L
L
L (Note 6)
H
H
H
L
H (Note 6)
L
H
L
H
L (Note 6)
L
H
H
H
H (Note 6)
L
Suspnd
H
Transmit Mode
Inputs
Outputs
OE
DAT_VP
SEO_VM
D
D
L
L
L
L
H
Differential Logic 0
L
H
L
H
L
Differential Logic 1
L
L
H
L
L
SE0
L
H
H
L
L
SE0
Pin
Power Supply Mode Configuration
Sharing
Self Powered
Disable
V
CC
d
0.8V or Not Connected
Connected to 3.3V Source
Connected to 3.3V Source
V
CCIO
1.65V to 3.6V Source
1.65V to 3.6V Source
d
0.5V or Not Connected
D
, D
3-STATE
Function of Mode Set Up
3-STATE
DAT_VP,
SE0_VM
H
Function of Mode Set Up
(Invalid)
Preliminary
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4
USB1
101
Absolute Maximum Ratings
(Note 7)
System ESD Testing
Recommended Operating Conditions
Note 7: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics table are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 8: HBM: Mil-Std_883E compliance. Socketed testing of three units per zap voltage (3
pulses and 3
pulses). I
O
v I
O
, I
O
v GND, I
O
v V
CC
, V
CC
v GND.
Note 9: MM: ESD_STM 5.2 compliance. Socketed testing of three units per zap voltage (3
pulses and 3
pulses). I
O
v I
O
, I
O
v GND, I
O
v V
CC
, V
CC
v GND.
Note 10: CDM: ESD_STM 5.3.1 compliance. Devices (3 per level) are charged, entire package, and discharged through a single pin contacted to each indi-
vidual pin on the DUT. NC pins are not stressed. Positive and negative charge is placed on the DUT (sitting atop a metallic plate). Maximum stress voltage
applicable at FSME is 2000V.
Note 11: This test is an extension of HBM Mil_Std 883E. However, this test is confined to the differential pins only.
Note 12: IEC61000-4-2 system level testing: System level testing done on this parts evaluation system boar.
Symbol
Parameter
Conditions
Limits
Units
Min
Max
V
CC
Supply Voltage
0.5
4.6
V
V
CCIO
I/O Supply Voltage
0.5
4.6
V
I
IK
DC Input Current
V
I
0
18.0
mA
V
I
DC Input Voltage
(Note 8)
0.5
V
CCIO
0.5
V
I
OK
DC Output Diode Current
V
O
!
V
CC
or
0
r
18.0
mA
V
O
DC Output Voltage
(Note 8)
0.5
V
CCIO
0.5
V
I
O
DC Output Source or Sink
V
O
0 to V
CC
mA
Current for D
, D
Pins
r
12.0
SE0_VM/DAT_VP
r
12.0
I
CC
, I
GND
DC V
CC
or GND Current
r
100
mA
V
ESD
ESD Immunity Voltage
I
O
, GND, V
CC
2000
TBD
V
HBM (Mil-std. 883E)
Pins (Note 8)
MM (ESD_STM 5.2)
V
CCIO
0.5
200
TBD
V
Pins (Note 9)
CDM (ESD_STM 5.3.1)
I
O
, GND, V
CC
1000
2000
V
Pins (Note 10)
HBM (Mil-std. 883E)
Pins D
, D
(Note 11)
TBD
TBD
V
USB Connector
TBD
TBD
V
T
STO
Storage Temperature Range
40.0
125
q
C
P
TOT
Power Dissipation
I
CC
60.0
mW
System
Parameter
Conditions
Limits
Units
Min
Max
ESDsys
IEC61000-4-2 (Note 12)
USB Connector
TBD
TBD
V
Symbol
Parameter
Conditions
Limits
Units
Min
Max
V
CC
DC Supply Voltage
3.0
3.6
V
V
CCIO
I/O DC Voltage
1.65
3.6
V
V
I
DC Input Voltage Range
0
3.6
V
V
AI/O
DC Input Range for AI/O
Pins D
and D
0
3.6
V
T
AMB
Operating Ambient Temperature
40.0
85.0
q
C
Preliminary
5
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USB1
101
DC Electrical Characteristics (Supply Pins)
Over recommended range of supply voltage and
operating free air temperature (unless otherwise noted): V
CC
3.0V to 3.6V, V
CCIO
1.65V to 3.6V
Note 13: Not tested in production, value based on characterization.
Note 14: Excludes any current from load and V
SW
current to the 1.5k
:
and 15k
:
pull-up/pull-down resistors (200
P
A typ).
Note 15: Minimum value for V
CCTH
2.0V for supply present condition for V
CCIO
1.8V.
Symbol
Parameter
Conditions
Limits
Units
Temperature
40
q
C to
85
q
C
Min
Typ
Max
I
CC
Operating Supply Current (V
CC
)
Transmitting and receiving at 12Mbit/s;
4.0
8.0
mA
C
LOAD
50pF (D
, D
)
I
CC(IDLE)
Supply Current During FS IDLE and
IDLE: V
D
t
2.7, V
D
d
1.3V;
300
P
A
SE0 (V
CC
)
SE0: V
D
d
0.3V, V
D
d
1.3V
(Note 14)
I
CC(DISABLE)
Disabled Supply Current
Suspnd
H or L; OE
H or L;
20.0
P
A
Config
L
D
D
DAT_VP
SE0_VM = H or L
V
CCIO
d
0.3V
I
CC(SUSPNDR)
Suspend V
CC
Supply Current
Suspnd
OE
Config
H
40.0
P
A
(Internal Resistor Pull-up)
D
Open
I
CCIO(STATIC)
I/O Static V
CCIO
Supply Current
IDLE, SE0
20.0
P
A
I
CCIO(SHARING)
I/O Sharing Mode V
CCIO
Supply Current
V
CC
Not Connected or
d
0.5V or 0V
20.0
P
A
I
CCIO(SUSPNDR)
Suspend V
CCIO
Supply Current
Suspnd
Config
HIGH;
20.0
P
A
OE
HIGH or LOW
D
Open
I
D
r
(SHARING)
Sharing Mode Load Current on D
, D
Pins
V
CC
Not Connected or
d
0.8V
10.0
10.0
P
A
Config
LOW; V
D
r
3.6V
V
CCTH
V
CC
Threshold Detection Voltage
3.0
d
V
CC
d
3.6V
V
(Self Powered)
Supply Lost
0.8
Supply Present
2.4
(Note 15)
V
CCHYS
V
CC
Threshold Detection Hysteresis Voltage
V
CCIO
1.8V
450
mV
V
CCIOTH
V
CCIO
Threshold Detection Voltage
3.0V
d
V
CC
d
3.6V
V
Supply Lost
0.5
Supply Present
1.4
V
CCIOHYS
V
CCIO
Threshold Detection Hysterias Voltage V
CC
3.3V
450
mV
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