2005 Fairchild Semiconductor Corporation
DS500905
www.fairchildsemi.com
April 2005
Revised May 2005
USB1
T1
103
Uni
versal
Ser
i
al
B
u
s Per
i
pher
al
T
r
an
sceive
r wi
th
V
o
lt
age
Regul
ator
USB1T1103
Universal Serial Bus Peripheral Transceiver
with Voltage Regulator
General Description
This chip provides a USB Transceiver functionality with a
voltage regulator that is compliant to USB Specification
Rev 2.0. this integrated 5V to 3.3V regulator allows inter-
facing of USB Application specific devices with supply volt-
ages ranging from 1.65V to 3.6V with the physical layer of
Universal Serial Bus. It is capable of operating at 12Mbits/s
(full speed) data rates and hence is fully compliant to USB
Specification Rev 2.0. The Vbusmon terminal allows for
monitoring the Vbus line.
The USB1T1103 also provides exceptional ESD protection
with 15kV contact HBM on D
, D
terminals.
Features
s
Complies with Universal Serial Bus Specification 2.0
s
Integrated 5V to 3.3V voltage regulator for powering
VBus
s
Utilizes digital inputs and outputs to transmit and receive
USB cable data
s
Supports full speed (12Mbits/s) data rates
s
Ideal for portable electronic devices
s
MLP technology package (16 terminal) with HBCC
footprint
s
15kV contact HBM ESD protection on bus terminals
s
Supports disable mode and is functionally equivalent to
Philips ISP1102
Applications
PDA
PC Peripherals
Cellular Phones
MP3 Players
Digital Still Camera
Information Appliance
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Order Number
Package
Number
Package Description
USB1T1103MPX
MLP14D
Pb-Free 14-Terminal Molded Leadless Package (MLP), 2.5mm Square
USB1T1103MHX
MLP16HB
Pb-Free 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
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USB1
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Logic Diagram
Connection Diagrams
MLP16 GND Exposed Diepad
(Bottom View)
MLP14 GND Exposed Diepad
(Bottom View)
3
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USB1
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Terminal Descriptions
Terminal Number
Terminal
Name
I/O
Terminal Description
MLP14
MLP16
1
1
OE
I
Output Enable:
Active LOW enables the transceiver to transmit data on the bus. When not
active the transceiver is in the receive mode (CMOS level is relative to V
CCIO
)
2
2
RCV
O
Receive Data Output:
Non-inverted CMOS level output for USB differential Input (CMOS output level
is relative to V
CCIO
). Driven LOW when SUSPN is HIGH; RCV output is stable
and preserved during SE0 condition.
3
3
V
p
/V
po
I/O
Single-ended D
receiver output V
P
(CMOS level relative to V
CCIO
):
Used for external detection of SE0, error conditions, speed of connected device;
Terminal also acts as drive data input V
po
(see Table 1 and Table 2).
Output drive is 4 mA buffer.
4
4
V
m
/V
mo
I/O
Single-ended D
receiver output V
m
(CMOS level relative to V
CCIO
):
Used for external detection of SE0, error conditions, speed of connected device;
Terminal also acts as drive data input V
mo
(see Table 1 and Table 2).
Output drive is 4 mA buffer.
5
5
SUSPND
I
Suspend:
Enables a low power state (CMOS level is relative to V
CCIO
). While the
SUSPND terminal is active (HIGH) it will drive the RCV terminal to logic "0"
state.
--
6
NC
No Connect
6
7
V
CCIO
Supply Voltage for digital I/O terminals (1.65V to 3.6V):
When not connected the D
and D
terminals are in 3-STATE. This supply bus
is totally independent of V
CC
(5V) and V
REG
(3.3V), and must never exceed the
V
REG
(3.3) voltage. For V
CCIO
disconnected the O
/O
terminals are HIGH
Impedance and the V
PU
(3.3V) is turned off.
7
8
Vbusmon
O
Vbus monitor output (CMOS level relative to V
CCIO
):
When Vbus
!
4.1V then Vbusmon
HIGH and when Vbus
3.6V then
Vbusmon
LOW. If SUSPND
HIGH then Vbusmon is pulled HIGH.
9, 8
10, 9
D
, D
AI/O
Data
, Data
:
Differential data bus conforming to the USB standard. Terminals are HIGH
Impedance for bus powered mode when Vbus
3.6V. For ByPass Mode then
HIGH Impedance when V
REG
/ Vbus
V
REG
minimum.
10
11
NC
No Connect
--
12
NC
No Connect
11
13
V
REG
(3.3V)
Internal Regulator Option:
Regulated supply output voltage (3.0V to 3.6V) during 5V operation;
decoupling capacitor of at least 0.1
P
F is required.
Regulator ByPass Option:
Used as supply voltage input for 3.3V operation.
12
14
V
CC
(5.0V)
Internal Regulator Option:
Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB
line Vbus.
Regulator ByPass Option:
Connected to V
REG
(3.3V)
13
15
V
PU
(3.3V)
Pull-up Supply Voltage (3.3V
r
10%):
Connect an external 1.5k
:
resistor on D
(FS data rate);
Terminal function is controlled by Config input terminal:
Config
LOW
V
PU
(3.3V) is floating (HIGH Impedance) for zero pull-up cur-
rent.
Config
HIGH
V
PU
(3.3V)
3.3V; internally connected to V
REG
(3.3V).
V
PU
is OFF in disable mode.
14
16
Config
I
USB connect or disconnect software control input.
Configures 3.3V to external 1.5k
:
resistor on D
when HIGH.
Exposed
Diepad
Exposed
Diepad
GND
GND
GND supply down bonded to exposed diepad to be connected to the PCB GND.
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USB1
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Functional Description
The USB1T1103 transceiver is designed to convert CMOS
data into USB differential bus signal levels and to convert
USB differential bus signal to CMOS data.
To minimize EMI and noise the outputs are edge rate con-
trolled with the rise and fall times controlled and defined for
full speed data rates only (12Mbits/s). The rise, fall times
are balanced between the differential terminals to minimize
skew.
The USB1T1103 differs from earlier USB Transceiver in
that the V
p
/V
m
and V
po
/V
mo
terminals are now I/O terminals
rather than discrete input and output terminals. Table 1
describes the specific terminal functionality selection. Table
2 and Table 3 describe the specific Truth Tables for Driver
and Receiver operating functions.
The USB1T1103 also has the capability of various power
supply configurations, including a disable mode for V
CCIO
disconnected, to support mixed voltage supply applications
(see Table 4) and Section 2.1 for detailed descriptions.
Functional Tables
TABLE 1. Function Select
Note 1: Signal levels is function of connection and/or pull-up/pull-down resistors.
Note 2: For SUSPND
HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling (K) is detected via
the single-ended receivers of the V
p
/V
po
and V
m
/V
mo
terminals.
TABLE 2. Driver Function (OE
L) using Differential Input Interface
Note 3: SE0
Single Ended Zero
TABLE 3. Receiver Function (OE
H)
X
Don't Care
RCV(0) denotes the signal level on output RCV just prior to the SE0 or SE1 event. This level is stable during the SE0 or SE1 event period.
SUSPND
OE
D
, D
RCV
V
p
/V
po
V
m
/V
mo
Function
L
L
Driving &
Receiving
Active
V
po
Input
V
mo
Input
Normal Driving
(Differential Receiver Active)
L
H
Receiving
(Note 1)
Active
V
p
Output
V
m
Output Receiving
H
L
Driving
Inactive
(Note 2)
V
po
Input
V
mo
Input
Driving during Suspend
(Differential Receiver Inactive)
H
H
3-STATE
(Note 1)
Inactive
(Note 2)
V
p
Output
V
m
Output Low Power State
V
m
/V
mo
V
p
/V
po
Data (D
/ D
)
L
L
SE0 (Note 3)
L
H
Differential Logic 1
H
L
Differential Logic 0
H
H
Illegal State
D
, D
RCV
V
p
/V
po
V
m
/V
mo
Differential Logic 1
H
H
L
Differential Logic 0
L
L
H
SE0
X
L
L
5
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USB1
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Power Supply Configurations and Options
The three modes of power supply operation are:
Normal Mode: Regulated Output and Regulator Bypass
1. Regulated Output: V
CCIO
is connected and V
CC
(5.0)
is connected to 5V (4.0V to 5.5V) and the internal
voltage regulator then produces 3.3V for the USB
connections.
2. Internal Regulator Bypass Mode: V
CCIO
is con-
nected and both V
CC
(5.0) and V
REG
(3.3) are con-
nected to a 3.3V source (3.0V to 3.6V).
In both cases for normal mode the V
CCIO
is an indepen-
dent voltage source (1.65V to 3.6V) that is a function of
the external circuit configuration.
Sharing Mode: V
CCIO
is only supply connected. V
CC
and
V
REG
are not connected. In this mode the D
and D
ter-
minals are 3-STATE and the USB1T1103 allows external
signals up to 3.6V to share the D
and D
bus lines.
Internally the circuitry limits leakage from D
and D
ter-
minals (maximum 10
P
A) and V
CCIO
such that device is
in low power (suspended) state. Terminals Vbusmon
and RCV are forced LOW as an indication of this mode
with Vbusmon being ignored during this state.
Disable Mode: V
CCIO
is not connected. V
CC
is con-
nected, or V
CC
and V
REG
are connected. 0V to 3.3V in
this mode D
and D
are 3-STATE and V
PU
is HIGH
Impedance (switch is turned off). The USB1T1103 allows
external signals up to 3.6V to share the D
and D
bus
lines. Internally the circuitry limits leakage from D
and
D
pins (maximum 10
P
A).
A summary of the Supply Configurations is described in
Table 4.
TABLE 4. Power Supply Configuration Options
Invalid [I] I/O are to be 3-STATE, outputs to be LOW.
Terminals
Power Supply Mode Configuration
Disable
Sharing
Normal (Regulated
Output)
Normal (Regulator
Bypass)
V
CC
(5V)
Connected to 5V
source
Not Connected
or
3.6V
Connected to 5V
Source
Connected to V
REG
(3.3V)
[Max Drop of 0.3V]
(2.7V to 3.6V)
V
REG
(3.3V)
3.3V, 300
P
A
Regulated Output
Not Connected
3.3V, 300
P
A
Regulated Output
Connected to 3.3V
Source
V
CCIO
d
0.5V
1.65V to 3.6V Source
1.65V to 3.6V Source
1.65V to 3.6V Source
V
PU
(3.3V)
3-STATE (off)
3-STATE (Off)
3.3V Available if
Config
HIGH
3.3V Available if
Config
HIGH
D
, D
3-STATE (off)
3-STATE
Function of
Mode Set Up
Function of
Mode Set Up
V
p
/V
po
, V
m
/V
mo
Invalid [I]
L
Function of
Mode Set Up
Function of
Mode Set Up
RCV
Invalid [I]
L
Function of
Mode Set Up
Function of
Mode Set Up
Vbusmon
Invalid [I]
L
Function of
Mode Set Up
Function of
Mode Set Up
OE, SUSPND, Config
Hi-Z
Hi-Z
Function of
Mode Set Up
Function of
Mode Set Up
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