2005 Fairchild Semiconductor Corporation
DS500234
www.fairchildsemi.com
November 1999
Revised March 2005
USB1
T1
1A
Univer
sal
Ser
i
al
Bus
T
r
ans
ceive
r
USB1T11A
Universal Serial Bus Transceiver
General Description
The USB1T11A is a one chip generic USB transceiver. It is
designed to allow 5.0V or 3.3V programmable and stan-
dard logic to interface with the physical layer of the Univer-
sal Serial Bus. It is capable of transmitting and receiving
serial data at both full speed (12Mbit/s) and low speed
(1.5Mbit/s) data rates.
The input and output signals of the USB1T11A conform
with the "Serial Interface Engine". Implementation of the
Serial Interface Engine along with the USB1T11A allows
the designer to make USB compatible devices with off-the-
shelf logic and easily modify and update the application.
Features
s
Complies with Universal Serial Bus specification 1.1
s
Utilizes digital inputs and outputs to transmit and receive
USB cable data
s
Supports 12Mbit/s "Full Speed" and 1.5Mbit/s
"Low Speed" serial data transmission
s
Compatible with the VHDL "Serial Interface Engine"
from USB Implementers' Forum
s
Supports single-ended data interface
s
Single 3.3V supply
s
ESD Performance: Human Body Model
!
9.5 kV on D
, D
pins only
!
4 kV on all other pins
s
16-lead Pb-Free MLP package saves space
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Note 1: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Note 2: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.
The USB-IF Logos are trademarks of Universal Serial Bus Implementers Forum, Inc.
Order Number
Package
Package Description
Number
USB1T11AM
(Note 1)
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
USB1T11AM_NL
(Note 2)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
USB1T11ABQX
MLP16C
Pb-Free 16-Terminal Molded Leadless Package (MLP), JEDEC MO-220, 3mm square
USB1T11AMTC
(Note 1)
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
USB1T11AMTC_NL
(Note 2)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
USB1T11AMTCX_NL
(Note 2)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
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2
USB1
T1
1A
Connection Diagrams
Pin Assignments for SOIC and TSSOP
Pin Assignments for MLP
Logic Diagram
Pin Descriptions
Pin Name
I/O
Description
RCV
O
Receive data. CMOS level output for USB differential input
OE
I
Output Enable. Active LOW, enables the transceiver to transmit data on the bus. When not
active the transceiver is in receive mode.
MODE
I
Mode. When left unconnected, a weak pull-up transistor pulls it to V
CC
and in this GND, the
VMO/FSEO pin takes the function of FSEO (Force SEO).
V
PO
, V
MO
/F
SEO
I
Inputs to differential driver. (Outputs from SIE).
MODE
VPO
VMO/FSEO
RESULT
0
0
0
Logic "0"
0
1
SE0
1
0
Logic "1"
1
1
SEO
1
0
0
SE0
0
1
Logic "0"
1
0
Logic "1"
1
1
Illegal code
V
P
, V
M
O
Gated version of D
and D
. Outputs are logic "0" and logic "1". Used to detect single ended
zero (SE0), error conditions, and interconnect speed. (Input to SIE).
VP
VM
RESULT
0
0
SE0
0
1
Low Speed
1
0
Full Speed
1
1
Error
D
, D
AI/O
Data
, Data
. Differential data bus conforming to the Universal Serial Bus standard.
SUSPND
I
Suspend. Enables a low power state while the USB bus is inactive. While the suspend pin is
active it will drive the RCV pin to a logic "0" state. Both D
and D
are 3-STATE.
SPEED
I
Edge rate control. Logic "1" operates at edge rates for "full speed".
Logic "0" operates edge rates for "low speed".
V
CC
3.0V to 3.6V power supply
GND
Ground reference
3
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USB1
T1
1A
Functional Truth Table
X
Don't Care
Z
3-STATE
U
Undefined State
Input
I/O
Outputs
Mode
VPO
VMO/FSEO
OE
SUSPND
D
D
RCV
V
P
V
M
Result
0
0
0
0
0
0
1
0
0
1
Logic 0
0
0
1
0
0
0
0
U
0
0
SEO
0
1
0
0
0
1
0
1
1
0
Logic 1
0
1
1
0
0
0
0
U
0
0
SEO
1
0
0
0
0
0
0
U
0
0
SEO
1
0
1
0
0
0
1
0
0
1
Logic 0
1
1
0
0
0
1
0
1
1
0
Logic 1
1
1
1
0
0
1
1
U
U
U
Illegal Code
X
X
X
1
0
Z
Z
U
U
U
D
/D
Hi-Z
X
X
X
1
1
Z
Z
U
U
U
D
/D
Hi-Z
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4
USB1
T1
1A
Absolute Maximum Ratings
(Note 3)
Recommended Operating
Conditions
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristic tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 4: The input and output voltage ratings may be exceeded if the input
and output clamp current ratings are observed.
DC Electrical Characteristics
(Digital Pins)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CC
3.0V to 3.6V
DC Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0
50 mA
Input Voltage (V
I
)
(Note 4)
0.5V to
5.5V
Input Voltage (V
I/O
)
0.5V to V
CC
0.5V
Output Diode Current (I
OK
)
V
O
!
V
CC
or V
O
0
r
50 mA
Output Voltage (V
O
)
(Note 4)
0.5V to V
CC
0.5V
Output Source or Sink Current (I
O
)
VP.VM, RCV pins
V
O
0 to V
CC
r
15 mA
Output Source or Sink Current (I
O
)
D
/D
pins
V
O
0 to V
CC
r
50 mA
V
CC
or GND Current (I
CC
, I
GND
)
r
100 mA
Storage Temperature (T
STO
)
60
q
C to
150
q
C
Supply Voltage V
CC
3.0V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Input Range for AI/O (V
AI/O
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Ambient Temperature
in free air (T
amb
)
40
q
C to
85
q
C
Symbol
Parameter
Test Conditions
Limits
Unit
Temp
40
q
C to
85
q
C
Min
Typ
Max
INPUT LEVELS:
V
IL
LOW Level Input Voltage
0.8
V
V
IH
HIGH Level Input Voltage
2.0
V
OUTPUT LEVELS:
V
OL
LOW Level Output Voltage
I
OL
4 mA
0.4
V
I
OL
20
P
A
0.1
V
OH
HIGH Level Output Voltage
I
OH
4 mA
2.4
V
I
OH
20
P
A
V
CC
0.1
LEAKAGE CURRENT:
I
L
Input Leakage Current
V
CC
3.0 to 3.6
r
5
P
A
I
CCFS
Supply Current (Full Speed)
V
CC
3.0 to 3.6
5
mA
I
CCLS
Supply Current (Low Speed)
V
CC
3.0 to 3.6
5
mA
I
CCQ
Quiescent Current
V
CC
3.0 to 3.6
5
mA
V
IN
V
CC
or GND
I
CCS
Supply Current in Suspend
V
CC
3.0 to 3.6; Mode
V
CC
10
P
A
5
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USB1
T1
1A
DC Electrical Characteristics
(D
/D
Pins)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CC
3.0V to 3.6V
Note 5: Excludes external resistor. In order to comply with USB Specification 1.1, external series resistors of 24
:
r
1% each on D
and D
are recom-
mended. This specification is guaranteed by design and statistical process distribution.
Note 6: This specification is guaranteed by design and statistical process distribution.
AC Electrical Characteristics
(D
/D
Pins, Full Speed)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CC
3.0V to 3.6V
C
L
50 pF; R
L
1.5 k
:
on D
to V
CC
Symbol
Parameter
Test Conditions
Limits
Units
Temp
40
q
C to
85
q
C
Min
Typ
Max
INPUT LEVELS:
V
DI
Differential Input Sensitivity
|(D
) (D
)|
0.2
V
V
CM
Differential Common Mode Range
Includes V
DI
Range
0.8
2.5
V
V
SE
Single Ended Receiver Threshold
0.8
2.0
V
OUTPUT LEVELS:
V
OL
Static Output LOW Voltage
R
L
of 1.5 k
:
to 3.6V
0.3
V
V
OH
Static Output HIGH Voltage
R
L
of 15 k
:
to GND
2.8
3.6
V
V
CR
Differential Crossover
1.3
2.0
V
LEAKAGE CURRENT:
I
OZ
High Z State Data Line Leakage Current 0V
V
IN
3.3V
r
5
P
A
CAPACITANCE:
C
IN
(Note 6)
Transceiver Capacitance
Pin to GND
10
pF
Capacitance Match
10
%
OUTPUT RESISTANCE:
Z
DRV
(Note 5) Driver Output Resistance
Steady State Drive
4
20
:
Resistance Match
10
%
Symbol
Parameter
Test Condition
Limits
Units
Temp
40
q
C to
85
q
C
Min
Typ
Max
DRIVER CHARACTERISTICS:
10% and 90%
ns
t
R
Rise Time
Figure 1
4
20
t
F
Fall Time
Figure 1
4
20
t
RFM
Rise/Fall Time Matching
(t
r
/t
f
)
90
110
%
V
CRS
Output Signal Crossover Voltage
1.3
2.0
V
DRIVER TIMINGS:
t
PLH
Driver Propagation Delay
Figure 2
18
ns
t
PLH
(VPO, VMO/FSEO to D
/D
)
Figure 2
18
ns
t
PHZ
Driver Disable Delay
Figure 4
13
ns
t
PLZ
(OE to D
/D
)
Figure 4
13
ns
t
PZH
Driver Enable Delay
Figure 4
17
ns
t
PZL
(OE to D
/D
)
Figure 4
17
ns
RECEIVER TIMINGS:
t
PLH
Receiver Propagation Delay
Figure 3
16
ns
t
PHL
(D
, D
to RCV)
Figure 3
19
ns
t
PLH
Single-ended Receiver Delay
Figure 3
8
ns
t
PHL
(D
, D
to VP, VM)
Figure 3
8
ns
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