ChipFind - документация

Электронный компонент: X24256

Скачать:  PDF   ZIP
REV 1.1.3 10/23/00
Characteristics subject to change without notice.
1 of 17
www.xicor.com
256K
X24256
32K x 8 Bit
400kHz 2-Wire Serial EEPROM
FEATURES
400kHz 2-wire serial interface
--Schmitt trigger input noise suppression
--Output slope control for ground bounce noise
elimination
Longer battery life with lower power
--Active read current less than 1mA
--Active write current less than 3mA
--Standby current less than 1A
2.5V to 5.5V power supply
64-byte page write mode
--Minimizes total write time per word
Internally organized 32K x 8
Bidirectional data transfer protocol
Self-timed write cycle
--Typical write cycle time of 5ms
High reliability
--Endurance: 100,000 cycles
--Data retention: 100 years
8-lead XBGA
8-lead SOIC
14-lead TSSOP
DESCRIPTION
The X24256 is a CMOS Serial EEPROM, internally
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
Two device select inputs (S
0
S
1
) allow up to 4 devices
to share a common two wire bus.
These pins have internal pull downs, so they are read
as LOW if not connected.
A WP pin, when pulled HIGH prevents any nonvolatile
writes to the array. When not connected WP is pulled
LOW, so the device is not normally protected.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Serial EEPROM Data
and Address (SDA)
SCL
S
1
S
0
WP
Command
Decode
and
Control
Logic
Write Protect
Control Logic
Device
Select
Logic
Page
Decode
Logic
Data Register
Y Decode Logic
Write Voltage
Control
Serial E
E
PROM
Array
32K x 8
X24256
Characteristics subject to change without notice.
2 of 17
REV 1.1.3 10/23/00
www.xicor.com
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
)
The device select inputs (S
0
, S
1
) are used to set bits in
the slave address. This allows up to four devices to
share a common bus. These inputs can be static or
actively driven. If used statically they must be tied to
V
SS
or V
CC
as appropriate. If actively driven, they must
be driven with CMOS levels (driven to V
CC
or V
SS
) and
they must be constant between each start and stop
issued on the SDA bus. These pins have an active pull
down internally and will be sensed as low if the pin is
left unconnected.
Write Protect (WP)
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Protect
feature. When held LOW, Protection is disabled and
the device operates normally. When this input is held
HIGH, the device is protected, preventing changes to
any and all locations in the EEPROM array.
PIN NAMES
PIN CONFIGURATION
Symbol
Description
S
0
, S
1
Device Select Inputs
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
8-Lead SOIC
V
CC
WP
SCL
S
0
S
1
1
2
3
4
6
7
8
X24256
V
SS
SDA
S
2
5
14-Lead TSSOP
V
CC
WP
SCL
S
0
S
1
NC
1
2
3
4
7
6
5
X24256
V
SS
SDA
NC
NC
NC
NC
8
9
10
11
12
14
13
NC
S
1
SDA
NC
SCL
V
CC
V
SS
S
0
WP
8
7
6
5
1
2
3
4
S
2
8-Lead XBGA: Top View
X24256
Characteristics subject to change without notice.
3 of 17
REV 1.1.3 10/23/00
www.xicor.com
DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
SCL
SDA
Data Stable
Data
Change
SCL
SDA
Start Bit
Stop Bit
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
X24256
Characteristics subject to change without notice.
4 of 17
REV 1.1.3 10/23/00
www.xicor.com
Figure 3. Acknowledge Response From Receiver
SCL from
Master
Data Output
from Transmitter
1
8
9
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal "1010". The next bit is a "0". The
following 2 bits are the device select bits `0', S
1
and S
0
.
This allows up to 4 devices to share a single bus.
These bits are compared to the S
0
and S
1
device
select input pins. The last bit of the Slave Address Byte
defines the operation to be performed. When the R/W
bit is a one, then a read operation is selected. When it is
zero then a write operation is selected. Refer to Figure 4.
After loading the Slave Address Byte from the SDA bus,
the device compares the device type bits with the value
"1010" and the device select bits with the status of the
device select input pins. If the compare is not success-
ful, no acknowledge is output during the ninth clock
cycle and the device returns to the standby mode.
On power up the internal address is undefined, so the
first read or write operation must supply an address.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
The internal organization of the E
2
array is 512 pages
by 64-bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
Figure 4. Device Addressing
1
S
1
S
0
R/W
Device
Select
0
1
0
0
Device Type
Identifier
Slave Address Byte
D7
D2
D1
D6
D5
D4
D3
Data Byte
A2
A1
A0
A5
A4
A3
Word Address Byte 0
0
A10
A9
A8
A14
High Order Word Address
A11
X24256 Word Address Byte 1
A13
A12
A7
A6
D0
Low Order Word Address
X24256
Characteristics subject to change without notice.
5 of 17
REV 1.1.3 10/23/00
www.xicor.com
WRITE OPERATIONS
Byte Write
For a write operation, the device follows "3 byte" proto-
col, consisting of one Slave Address Byte, one Word
Address Byte 1, and the Word Address Byte 0, which
gives the master access to any one of the words in the
array. Upon receipt of the Word Address Byte 0, the
device responds with an acknowledge, and waits for
the first eight bits of data. After receiving the 8 bits of
the data byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress
the device inputs are disabled and the device will not
respond to any requests from the master. The SDA pin
is at high impedance. See Figure 5.
Page Write
The device is capable of a 64 byte page write operation.
It is initiated in the same manner as the byte write
operation; but instead of terminating the write operation
after the first data word is transferred, the master can
transmit up to sixty-three more words. The device will
respond with an acknowledge after the receipt of each
word, and then the byte address is internally incre-
mented by one. The page address remains constant.
When the counter reaches the end of the page, it "rolls
over" and goes back to the first byte of the current
page. This means that the master can write 64-bytes to
the page beginning at any byte. If the master begins
writing at byte 32, and loads 64-bytes, then the first
32-bytes are written to bytes 32 through 63, and the
last 16 words are written to bytes 0 through 31. After-
wards, the address counter would point to byte 32. If the
master writes more than 64-bytes, then the previously
loaded data is overwritten by the new data, one byte at
a time.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
Figure 5. Byte Write Sequence
Figure 6. Page Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
T
A
R
T
Slave
Address
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Word Address
Byte 1
Data
1 0 1 0 0
Byte 0
S
P
0
Word Address
S
1
S
0
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data
(0)
(n)
S
P
Data
1 0 1 0
0
(0
n
64)
Slave
Address
Word Address
Byte 1
Byte 0
Word Address
Signals from
the Master
SDA Bus
Signals from
the Slave
0
S
1
S
0
X24256
Characteristics subject to change without notice.
6 of 17
REV 1.1.3 10/23/00
www.xicor.com
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it's associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 7.
Figure 7. Acknowledge Polling Sequence
Byte Load Completed
By Issuing Stop
Enter ACK Polling
Issue
Start
Issue Slave
Address Byte
(Read or Write)
ACK
Returned?
High
Voltage
Cycle Complete.
Continue
Sequence?
Continue Normal
Read or Write
Command Sequence
Proceed
Issue Stop
No
Yes
Yes
Issue Stop
No
X24256
Characteristics subject to change without notice.
7 of 17
REV 1.1.3 10/23/00
www.xicor.com
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will "roll over" to
the first address in the array. After a write operation to
the last address in a given page, the counter will "roll
over" to the first address on the same page.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 8. Current Address Read Sequence
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a "Dummy" write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/W
bit set to one. This is followed by an acknowledge and
then eight bits of data from the device. The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition. Refer
to Figure 9 for the address, acknowledge, and data
transfer sequence.
The device will perform a similar operation called "Set
Current Address" if a stop is issued instead of the
second start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the address
counter, but no data is output by the device.
The next Current Address Read operation will read
from the newly loaded address.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received. The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter "rolls over" to address
0000h and the device continues to output data for each
acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
S
T
A
R
T
Slave
Address
S
T
O
P
A
C
K
Data
Signals from
the Master
SDA Bus
Signals from
1
S
P
0 1 0
1
the Slave
S
0
0
S
1
X24256
Characteristics subject to change without notice.
8 of 17
REV 1.1.3 10/23/00
www.xicor.com
Figure 9. Random Read Sequence
Figure 10. Sequential Read Sequence
S
T
A
R
T
Slave
Address
S
T
O
P
A
C
K
A
C
K
A
C
K
Word Address
Byte 1
Slave
Address
0
Word Address
Byte 0
S
T
A
R
T
1
Data
A
C
K
S
P
S
1 0 1 0
Signals from
the Master
SDA Bus
Signals from
the Slave
S
1
S
0
0
S
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
(1)
(2)
(n1)
(n)
1
(n is any integer greater than 1)
P
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
Data
Data
Data
Data
S
1
S
0
0
X24256
Characteristics subject to change without notice.
9 of 17
REV 1.1.3 10/23/00
www.xicor.com
ABSOLUTE MAXIMUM RATINGS
Temperature under bias X24256 ...... 65C to +135C
Storage Temperature........................ 65C to +150C
Voltage on any pin with
respect to V
SS
.........................................1V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300C
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Supply Voltage
Limits
X242562.5
2.5V to 5.5V
D.C. OPERATING CHARACTERISTICS
V
CC
equals the range indicated for each device type, unless otherwise stated.
Symbol
Parameter
V
CC
= 2.5 to 5.5V
Unit
Test Conditions
Min.
Max.
I
CC1
Active Supply Current
(Read)
1
mA
V
IL
= V
CC
X 0.1, V
IH
= V
CC
X 0.9,
f
SCL
= 400kHz, SDA = Open
I
CC2
Active Supply Current
(Write)
3
mA
I
SB1
(2)
Standby Current AC
1
mA
V
IL
= V
CC
X 0.1, V
IH
= V
CC
X 0.9,
f
SCL
= 400kHz, SDA = Open
V
SB
Standby Voltage (Test)
V
CC
0.2
V
I
SB2
(2)
Standby Current DC
1
mA
V
SDA
= V
SCL
= V
SB
, Others =
GND or V
SB
I
LI
Input Leakage Current
10
mA
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
mA
V
SDA
= GND to V
CC
, Device is in
Standby
(2)
V
lL
(3)
Input LOW Voltage
0.5
V
CC
x 0.3
V
V
IH
(3)
Input HIGH Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
HYS
Schmitt Trigger Input
Hysteresis Fixed input level
0.2
V
V
CC
related level
V
CC
x 0.05
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 3mA
X24256
Characteristics subject to change without notice.
10 of 17
REV 1.1.3 10/23/00
www.xicor.com
CAPACITANCE T
A
= +25C, f = 1MHz, V
CC
= 5V
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t
WC
after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V
IL
Min. and V
IH
Max. are for reference only and are not tested.
Symbol
Parameter
Max.
Unit
Test Conditions
C
I/O
(3)
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
(3)
Input Capacitance (S
0
, S
1
, SCL, WP)
6
pF
V
IN
= 0V
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing levels
V
CC
X 0.5
Output load
Standard output load
5V
1.53K
100pF
Output
for V
OL
= 0.4V
I
OL
= 3mA
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise stated.
Read & Write Cycle Limits
Symbol
Parameter
V
CC
= 2.5V
Unit
Min.
Max.
f
SCL
SCL clock frequency
0
400
kHz
t
IN
Pulse width suppression time at inputs
50
ns
t
AA
SCL LOW to SDA data out valid
0.1
0.9
s
t
BUF
Time the bus must be free before a new transmission can start
1.3
s
t
LOW
Clock LOW period
1.3
s
t
HIGH
Clock HIGH period
0.6
s
t
SU:STA
Start condition setup time
0.6
s
t
HD:STA
Start condition hold time
0.6
s
t
SU:DAT
Data in setup time
100
ns
t
HD:DAT
Data in hold time
0
s
t
SU:STO
Stop condition setup time
0.6
s
t
DH
Data
output hold time
50
ns
t
R
SDA and SCL rise time
20 + .1Cb
(3)
300
ns
t
F
SDA and SCL fall time
300
ns
t
SU:S0, S1, WP
S0, S1, and WP Setup Time
0.6
ns
t
HD:S0, S1, WP
S0, S1, and WP Hold Time
0
ns
Cb
Capacitive load for each bus line
400
pF
X24256
Characteristics subject to change without notice.
11 of 17
REV 1.1.3 10/23/00
www.xicor.com
POWER-UP TIMING
(4)
Notes: (4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
(5) Typical values are for T
A
= 25C and nominal supply voltage (5V), Cb = total capacitance of one bus line in pF.
Bus Timing
S
0
, S
1
, and WP Pin Timing
Write Cycle Limits
Note:
(6) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24256 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Symbol
Parameter
Max.
Unit
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
5
ms
Symbol
Parameter
Min.
Typ.
Max.
Unit
T
WC
(6)
Write Cycle Time
--
5
10
ms
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
SU:STO
t
R
t
BUF
SCL
SDA IN
SDA OUT
t
DH
t
AA
t
F
t
HIGH
t
SU: S0, S1, WP
SCL
SDA IN
S
0
, S
1
, and WP
Slave Address Byte
Clk 1
Clk 9
t
HD: S0, S1, WP
X24256
Characteristics subject to change without notice.
12 of 17
REV 1.1.3 10/23/00
www.xicor.com
Write Cycle Timing
SCL
SDA
8
th
Bit
Word n
ACK
t
WC
Stop
Condition
Start
Condition
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
120
100
80
40
60
20
20
40
60
80 100 120
0
0
Resistance (K
)
Bus Capacitance (pF)
Min.
Resistance
Max.
Resistance
R
MAX
=
C
BUS
t
R
R
MIN
=
I
OL MIN
V
CC MAX
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X24256
Characteristics subject to change without notice.
13 of 17
REV 1.1.3 10/23/00
www.xicor.com
PACKAGING INFORMATION
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.020 (.508)
0.012 (.305)
.080 (2.03)
.070 (1.78)
.213 (5.41)
.205 (5.21)
.330 (8.38)
.300 (7.62)
.212 (5.38)
.203 (5.16)
.035 (.889)
.020 (.508)
.010 (.254)
.007 (.178)
08 Ref.
Pin 1 ID
.050 (1.27) BSC
8-Lead Plastic, 0.200" Wide Small Outline
Gullwing Package Typ "A" (EIAJ SOIC)
.013 (.330)
.004 (.102)
NOTES:
X24256
Characteristics subject to change without notice.
14 of 17
REV 1.1.3 10/23/00
www.xicor.com
PACKAGING INFORMATION
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
0.014 (0.35)
0.019 (0.49)
Pin 1
Pin 1 Index
0.010 (0.25)
0.020 (0.50)
0.050 (1.27)
0.188 (4.78)
0.197 (5.00)
0.004 (0.19)
0.010 (0.25)
0.053 (1.35)
0.069 (1.75)
(4X) 7
0.016 (0.410)
0.037 (0.937)
0.0075 (0.19)
0.010 (0.25)
0 - 8
X 45
8-Lead Plastic Small Outline Gull Wing Package Type S
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.250"
0.050"Typical
0.050"
Typical
0.030"
Typical
8 Places
FOOTPRINT
X24256
Characteristics subject to change without notice.
15 of 17
REV 1.1.3 10/23/00
www.xicor.com
PACKAGING INFORMATION
ALL DIMENSIONS IN M (to convert to inches, 1m = 3.94 x 10
-5
inch)
ALL DIMENSIONS ARE TYPICAL VALUES
8-Lead XBGA: Top View
S1
SDA
NC
SCL
V
CC
V
SS
S0
WP
8
7
6
5
1
2
3
4
.137"
.079"
8-Lead XBGA
Complete Part Number
Top Mark
8-Lead XBGA
X24256B-2.5
XAAI
X24256BI-2.5
XAAU
DWG Symbol
8L XBGA
A
Contact Factory
A1
Contact Factory
C
Contact Factory
D
Contact Factory
E
Contact Factory
e
Contact Factory
F
Contact Factory
X24256: Bottom View
F
D
C
S1
S0
V
SS
NC
WP
V
CC
SDA
SCL
A1
PIN 1
A1
E
C
e
A
D
X24256
Characteristics subject to change without notice.
16 of 17
REV 1.1.3 10/23/00
www.xicor.com
PACKAGINING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0 - 8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X24256
Characteristics subject to change without notice.
17 of 17
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Xicor, Inc. 2000 Patents Pending
REV 1.1.3 10/23/00
www.xicor.com
Ordering Information
Part Mark Conventions
Device
X24256
X
X
-X
V
CC
Range
2.5 = 2.5V to 5.5V
Temperature Range
Blank = 0
C to +70
C
I = 40
C to +85
C
Package
X24256
S8 = 8-Lead SOIC, 150 mil wide, JEDEC
V14 = 14-Lead TSSOP
A8 = 8-Lead SOIC, 200 mil wide, EIAJ
B = 8-Lead XBGA
S8 = 8-Lead SOIC (JEDEC)
AE = 2.5V to 5.5V, 0
C to +70
C
K = 2.5V to 5.5V, 40
C to +85
C
X24256
X
X
V14 = 14-Lead TSSOP
XBGA PACKAGE
Complete Part Number Top Mark
TSSOP/SOIC
X24256BI - 2.5
XAAU
X24256B - 2.5
XAAI
A8 = 8-Lead SOIC (EIAJ)