Direct Write
TM
and Block Lock
TM
Protection is a trademark of Xicor, Inc.
REV 1.02 11/28/00
Characteristics subject to change without notice.
1 of 17
www.xicor.com
Preliminary Information
256K
X25256
32K x 8 Bit
5MHz SPI Serial E
2
PROM with Block Lock
TM
Protection
FEATURES
5MHz Clock Rate
Low Power CMOS
--<1A standby current
--<5mA active current
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
32K X 8 Bits
--64 byte page mode
Block Lock
TM
Protection
--Protect first page, first 2 pages, first 4 pages,
first 8 pages, 1/4, 1/2 or all of E
2
PROM array
Programmable Hardware Write Protection
--In-circuit programmable ROM mode
Built-In Inadvertent Write Protection
--Power-up/down protection circuitry
--Write enable latch
--Write protect pin
Self-Timed Write Cycle
--5ms write cycle time (typical)
High Reliability
--Endurance: 100,000 cycles
--Data Retention: 100 Years
--ESD protection: 2000V on all pins
Packages
--8-lead XBGA
--8-lead SOIC (JEDEC, EIAJ)
--20-lead TSSOP
DESCRIPTION
The X25256 is a CMOS 256K-bit serial E
2
PROM, inter-
nally organized as 32K x 8. The X25256 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25256 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25256 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire
input to the X25256 disabling all write attempts to the
status register, thus providing a mechanism for limiting
end user capability of altering first page, first 2 pages, 4
pages, 8 pages, 0, 1/4, 1/2 or all of the memory.
FUNCTIONAL DIAGRAM
Command
Decode
And
Control
Logic
Write
Control
And
Timing
Logic
Write
Protect
Logic
X-Decode
Protect
32K Byte
Array
128 X 512
Y Decode
Data Register
SO
SI
SCK
CS
HOLD
WP
128
248
8
64
Status
Register
128
248 X 512
128 X 512
Logic
4 X 512
2 X 512
1 X 512
1 X 512
4
2
1
1
256 X 512
X25256 Preliminary Information
REV 1.02 11/28/00
Characteristics subject to change without notice.
2 of 17
www.xicor.com
The X25256 utilizes Xicor's proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
PIN CONFIGURATION
PIN NAMES
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25256 is deselected and the
SO output pin is at high impedance and unless an
internal write operation is underway, the X25256 will be
in the standby power mode. CS LOW enables the
X25256, placing it in the active power mode. It should
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is "1",
nonvolatile writes to the X25256 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25256 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no affect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is "0". This allows the user to install
the X25256 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set "1".
Symbol
Description
CS
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
V
SS
Ground
V
CC
Supply Voltage
HOLD
Hold Input
NC
No Connect
20-Lead TSSOP
NC
1
2
3
4
7
6
5
X25256
NC
NC
SO
NC
14
15
16
17
18
20
19
NC
CS
NC
NC
VCC
HOLD
SCK
WP
8
10
9
V
SS
NC
NC
11
12
13
NC
SI
NC
NC
8-Lead SOIC
VCC
HOLD
SCK
CS
1
2
3
4
6
7
8
X25256
VSS
SI
5
SO
WP
S0
SI
WP
SCK
V
CC
V
SS
CS
HOLD
8
7
6
5
1
2
3
4
8-Lead XBGA
X25256
Preliminary Information
REV 1.02 11/28/00
Characteristics subject to change without notice.
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Hold (HOLD)
HOLD is used in conjunction with the CS pin to pause
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication,
HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
Table 1. Instruction Set
Notes:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected address
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address (1 to 64 Bytes)
PRINCIPLES OF OPERATION
The X25256 is a 32K x 8 E
2
PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25256 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and
WP inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the
HOLD input to place the
X25256 into a "PAUSE" condition. After releasing
HOLD, the X25256 will resume operation from the
point when HOLD was first asserted.
Write Enable Latch
The X25256 contains a "write enable" latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
WPEN, BL0 and BL1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25256 is busy with a write operation. When set to a
"1", a write is in progress, when set to a "0", no write is
in progress. This bit is set and reset by hardware, it
cannot be controlled by the WRSR instruction. When
reading the Status Register while an internal nonvola-
tile write is in progress, all bits output will be `1'. This
allows the programmer to use the WIP bit to determine
an early end of write condition. It also allows the pro-
grammer to check for "FF" or "not FF" to determine end
of write. The programmer can also use the first one or
two bits received from the Status Register (if they were
known to be zero) to determine end of write. Each of
these techniques can simplify or speed the end of non-
volatile write detection.
7
6
5
4
3
2
1
0
WPEN
X
X
BL2
BL1
BL0
WEL
WIP
X25256 Preliminary Information
REV 1.02 11/28/00
Characteristics subject to change without notice.
4 of 17
www.xicor.com
The Write Enable Latch (WEL) bit indicates the status
of the "write enable" latch. When set to a "1", the latch
is set, when set to a "0", the latch is reset. This bit is
controlled by hardware and cannot be written by the
WRSR instruction.
The Block Lock
(BL0, BL1, and BL2) bits are nonvola-
tile and allow the user to select one of eight levels of
protection. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
Status Register Bits
Array Addresses Protected
Array Lock
BL2
BL1
BL0
0
0
0
None
None
0
0
1
$6000$7FFF (8K bytes)
Upper 1/4 (Q4)
0
1
0
$4000$7FFF (16K bytes)
Upper 1/2 (Q3, Q4)
0
1
1
$0000$7FFF (32K bytes)
Full Array (All)
1
0
0
$000$03F (64 bytes)
First Page (P1)
1
0
1
$000$07F (128 bytes)
First 2 Pages (P2)
1
1
0
$000$0FF (256 bytes)
First 4 Pages (P4)
1
1
1
$000$1FF (512 bytes)
First 8Pages (P8)
Figure 1. Block Lock Configurations
The Write-Protect-Enable (WPEN) bit is available for
the X25256 as a nonvolatile enable bit for the WP pin.
Programmable Hardware Write Protection
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register con-
trol the Programmable Hardware Write Protect feature.
Hardware Write Protection is enabled when WP pin is
LOW, and the WPEN bit is "1". Hardware Write Protec-
tion is disabled when either the WP pin is HIGH or the
WPEN bit is "0". When the chip is hardware write pro-
tected, nonvolatile writes are disabled to the Status
Register, including the Block Lock bits and the WPEN
bit itself, as well as the block-protected sections in the
memory array. Only the sections of the memory array
that are not block-protected can be written.
In Circuit Programmable ROM Mode
Note that since the WPEN bit is write protected, it can-
not be changed back to a LOW state; so write protec-
tion is enabled as long as the WP pin is held LOW.
Thus an In Circuit Programmable ROM function can be
implemented by hardwiring the WP pin to Vss, writing
to and Block Locking the desired portion of the array to
be ROM, and then programming the WPEN bit HIGH.
The table above defines the program protect status for
each combination of WPEN and WP.
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the E
2
PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25256, followed by the
16-bit address of which the last 15 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
000
001
010
011
100
101
110
111
1/2 Array
BL2-BL0
3/4 Array
All Array
X25256
Preliminary Information
REV 1.02 11/28/00
Characteristics subject to change without notice.
5 of 17
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can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
When the highest address is reached ($7FFF) the
address counter rolls over to address $0000 allowing the
read cycle to be continued indefinitely. The read operation
is terminated by taking CS HIGH. Refer to the read
E
2
PROM array operation sequence illustrated in Figure 2.
To read the status register the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the status register are shifted out on the SO line.
Figure 3 illustrates the read status register sequence.
WP
WPEN
Memory Array Not
Block Protected
Memory Array
Block Protected
Block Lock
Bits
WPEN Bit
Protection
HIGH
X
Writable
Blocked
Writable
Writable
Software
LOW
0
Writable
Blocked
Writable
Writable
Software
LOW
1
Writable
Blocked
Writes Blocked
Writes Blocked
Hardware
Write Sequence
Prior to any attempt to write data into the X25256, the
"write enable" latch must first be set by issuing the
WREN instruction (See Figure 4). CS is first taken
LOW, then the WREN instruction is clocked into the
X25256. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
To write data to the E
2
PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a thirty-
two clock operation. CS must go LOW and remain LOW
for the duration of the operation. The host may continue
to write up to 64 bytes of data to the X25256. The only
restriction is the 64 bytes must reside on the same
page. If the address counter reaches the end of the
page and the clock continues, the counter will "roll over"
to the first address of the page and overwrite any data
that may have been written.
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 5 and 6 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 5, and
6 are "don't care". Figure 7 illustrates this sequence.
While the write is in progress following a status register
or E
2
PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be HIGH.
Hold Operation
The HOLD input should be HIGH (at V
IH
) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK must
also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25256 powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The "write enable" latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
The "write enable" latch is reset upon power-up.
A WREN instruction must be issued to set the "write
enable" latch.
CS must come HIGH at the proper clock count in
order to start a write cycle.
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