Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Semiconductor
Application Note
AN2635
Rev. 4, 10/2005
On-Chip FLASH Programming
Routines
For MC68HC908LB8, MC68HC908QL4, MC68HC908QB8,
MC68HC908QB4, MC68HC908QY8, and MC68HC908QY4A Series
1
By: Kazue Kikuchi
MCU Applications Engineering
Austin, Texas
Introduction
This application note applies to the MC68HC908LB8, MC68HC908QL4, MC68HC908QB4/QB8/QY8,
and MC68HC908QY4A Series
1
FLASH-based microcontroller units (MCUs). To program, erase, and
verify FLASH, these MCUs have on-chip FLASH support routines residing in ROM (read-only memory).
These routines may be accessed in either user mode or monitor mode and eliminate the need to develop
separate FLASH routines for applications.
This application note describes how to call each of the routines in user software, what is performed, and
what is returned as confirmation of routine execution. The software files are available as a zip file,
AN2635SW, from the Freescale Semiconductor website: www.freescale.com
NOTE
With the exception of mask set errata documents, if any other
Freescale Semiconductor document contains information that conflicts with
the information in the device data sheet, the data sheet should be
considered to have the most current and correct data.
1. MC68HC908QY4A Series includes MC68HC908QY4A, MC68HC908QY2A, MC68HC908QY1A, MC68HC908QT4A,
MC68HC908QT2A, MC68HC908QT1A
On-Chip FLASH Programming Routines, Rev. 4
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Freescale Semiconductor
Routines Supported in ROM
FLASH Overview
The FLASH cell used on these 0.5-
MCUs is an industry-proven split-gate cell. The cell uses channel
hot electron injection for programming and Fowler-Nordheim tunnelling for erasing. All programming
voltages are generated internally by a charge pump from a single connection to V
DD
.
With the quick byte-programming time and the organization of the FLASH array into 32-byte rows, the
entire 8-Kbyte memory can be programmed in less than one-half second. This type of FLASH is specified
to withstand at least 10,000 program/erase cycles and has enhanced reliability over previous technology.
Usually, split-gate FLASH is programmed on a row basis and erased on a page basis. Also, an entire
specified array can be mass erased. For the target MCUs, rows are 32 bytes and pages are 64 bytes (two
rows of 32 bytes each).
Routines Supported in ROM
In the ROM, six routines are supported. Because the ROM has a jump table, the user does not call the
routines with direct addresses. Therefore, the calling addresses will not change--even when the ROM
code is updated in the future.
This section introduces each routine briefly. Details are discussed in later sections.
GetByte
This routine is used to receive a byte serially on the general-purpose I/O PTA0. The receiving baud rate
is the same as the baud rate used in monitor mode. In the GetByte routine, the GetBit routine is called to
generate baud rates required for each MCU.
PutByte
This routine is used to send a byte serially on the general-purpose I/O PTA0. The sending baud rate is
the same as the baud rate specified in monitor mode.
RDVRRNG
This routine is used to perform one of two options. Using the send-out option, this routine reads FLASH
locations and sends the data out serially on the general-purpose I/O PTA0. Using to verify option, this
routine verifies the FLASH data against data in a specific RAM location, which is referred to as a DATA
array.
PRGRNGE
This routine is used to program a contiguous range of FLASH locations that is up to 32 bytes and in the
same row. Programming data is first loaded into the DATA array. PRGRNGE can be used when the
internal operating frequency (f
op
) is between 1.0 MHz and 8.4 MHz.
Variables Used in the Routines
On-Chip FLASH Programming Routines, Rev. 4
Freescale Semiconductor
3
ERARNGE
This routine is used to erase either a page (64 bytes) or the whole array of FLASH. It can be used when
the internal operating frequency (f
op
) is between 1.0 MHz and 8.4 MHz.
DELNUS
This routine can generate a specified delay based on the values of register X and accumulator (A) as
parameters. DELNUS is used in ERARNGE routine.
Variables Used in the Routines
The RDVRNGE, PRGRNGE, and ERARNGE routines require certain registers and/or RAM locations to
be initialized before calling the routines in the user software.
Table 1
shows variables used in the routines
and their locations.
RAM
In general, RAM in
Table 1
indicates the RAM start address. See
Table 2
for RAM start locations for
specific MCUs. For example, the RAM start address for the MC68HC908LB8 (and each MCU currently
in the table) is $80.
CTRLBYT
The control byte (CTRLBYT) is located at RAM address RAM+$8 and is used for the ERARNGE routine.
In the case of the MC68HC908LB8, the CTRLBYT is located at $88. Bit 6 in this location is used to specify
either MASS (1) or PAGE (0) erase. The other bits must be 0. If one or more of these bits (except bit 6)
is initialized with 1, the erase operation is not executed.
Table 1. Variables and Their Locations
Location
Variable Name
Size (Bytes)
Description
RAM RAM+7
Reserved
8
Reserved for future use
RAM+$8
CTRLBYT
1
Control byte setting erase size
RAM+$9
CPUSPD
1
CPU speed -- the nearest integer of
f
op
(in MHz)
4;
for example, if
f
op
= 2.4576 MHz, CPUSPD = 10
RAM+$A,
RAM+$B
LADDR
2
Last address of a 16-bit range
RAM+$C
DATA
Varies
First location of DATA array;
DATA array size must match a programming or verifying range
Registers H:X
--
2
Beginning address of a 16-bit range
On-Chip FLASH Programming Routines, Rev. 4
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How to Use the Routines
CPUSPD
To set up proper delays used in the PRGRNGE and ERARNGE routines, a value indicating the internal
operating frequency (f
op
) must be stored at CPUSPD, which is located at RAM address RAM+$9. In the
case of the MC68HC908LB8, the CPUSPD is located at $89. The CPUSPD value is the nearest integer
of f
op
(in MHz) times 4. For example, if f
op
is 4.2 MHz, the CPUSPD value is 17. If f
op
is 2.1 MHz, the
CPUSPD value is 8. Setting a correct CPUSPD value is very important to program or erase the FLASH
successfully.
LADDR
A range specifies the FLASH locations to be read, verified, or programmed. The 16-bit value in RAM
addresses RAM+$A and RAM+$B holds the last address of a range. The addresses RAM+$A and
RAM+$B are the high and low bytes of the last address, respectively. In the case of MC68HC908LB8, the
LADDR is located at $8A and $8B. LADDR is used for RDVRRNG and PRGRNGE routines.
DATA
DATA is the first location of the DATA array and is located at RAM address RAM+$C. For the
MC68HC908LB8, the DATA is located at $8C. The array is used for loading program or verify data. The
DATA array must be in the zero page and its size must match the size of the range to be programmed or
verified.
Registers H:X
In the RDVRRNG and PRGRNGE routines, registers H and X are initialized with a 16-bit value
representing the first address of a range. High and low bytes of the address are stored to registers H and
X, respectively. In the ERARNGE routine, registers H and X are initialized with an address which is within
the page or entire array to be erased.
How to Use the Routines
This section describes the details of each routine.
Table 2
provides necessary addresses used in the
on-chip FLASH routines for each MCU type.
Table 3
summarizes the six routines.
Table 2. MCU Type vs. Necessary Addresses Required for On-Chip FLASH Routines
MCU Name
RAM
GetByte
PutByte
RDVRRNG PRGRNGE
ERARNGE
DELNUS
MC68HC908LB8
$80
$037E
$0381
$0384
$038A
$0387
$038D
MC68HC908QL4
$80
$2B7E
$2B81
$2B84
$2B8A
$2B87
$2B8D
MC68HC908QY4A
Series
(1)
NOTES:
1. MC68HC908QY4A Series includes MC68HC908QY4A, MC68HC908QY2A, MC68HC908QY1A, MC68HC908QT4A,
MC68HC908QT2A, MC68HC908QT1A
$80
$2800
$280F
$2803
$2809
$2806
$280C
MC68HC908QB4/QB8,
MC68HC908QY8
$80
$2800
$280F
$2803
$2809
$2806
$280C
How to Use the Routines
On-Chip FLASH Programming Routines, Rev. 4
Freescale Semiconductor
5
Table 3. Summary of On-Chip FLASH Support Routines
GetByte
PutByte
RDVRRNG
PRGRNGE
ERARNGE
DELNUS
Routine
Description
Get a data byte
serially through
PTA0
Send a data
byte serially
through PTA0
Read and/or
verify
a FLASH
range
Program a
FLASH range
(maximum 32
bytes in a row)
Erase a PAGE
or entire array
Generate
delay
3
A X + 8
(cycles)
Internal
Operating
Frequency
(f
op
)
--
--
--
1 MHz to
8.4 MHz
1 MHz to
8.4 MHz
--
Hardware
Requirement
Pullup on PTA0 Pullup on PTA0
For send-out
option, pullup
on PTA0
N/A
N/A
N/A
Entry
Conditions
PTA0: Input
(DDRA0 = 0)
PTA0: Input
and 0 data bit
(DDRA0 = 0,
PTA0 = 0)
A: data to be
sent
H:X: First
address of
range
LADDR: Last
address of
range
A: A = $00 for
send-out
option or
A
$00 for
verify option
For send-out
option
PTA0: Input
and 0 data bit
(DDRA0 = 0,
PTA0 = 0)
For verify
option,
DATA array:
Load data to
be verified
against
FLASH read
data
H:X: First
address
of range
LADDR: Last
address of
range
CPUSPD: the
nearest
integer
f
op
(in
MHz) times 4
Data array:
Load data
to be
programmed
H:X: Address
within a page
or an array to
be erased
CPUSPD: the
nearest
integer
f
op
(in
MHz) times 4
CTRLBYT:
$40 = MASS
erase
$00 = PAGE
erase
A: Value
between
4 and 255
X: Value
between
1 and 255
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