Document Outline

• Preface
• About This Manual
• Chapter1 5685X Overview
  • 1.1 Introduction
  • 1.2 5685x Family Description
    • 1.2.1 5685x Key Family Features
  • 1.3 5685x Family Architectural Overview
  • 1.4 56800E Core Description
    • 1.4.1 Key Features
    • 1.4.2 56800E Core Enhancements
    • 1.4.3 System Architecture and Peripheral Interface
    • 1.4.4 56800E Core Block Diagram
    • 1.4.5 Address Buses
    • 1.4.6 Data Buses
    • 1.4.7 Data Arithmetic Logic Unit (Data ALU)
    • 1.4.8 Address Generation Unit (AGU)
    • 1.4.9 Program Controller and Hardware Looping Unit
    • 1.4.10 Bit Manipulation Unit
    • 1.4.11 Enhanced On-Chip Emulation (EOnCE) Module
    • 1.4.12 Clocks
    • 1.4.13 Resets
    • 1.4.14 IPBus Bridge
  • 1.5 System Bus Controller
    • 1.5.1 Operation
    • 1.5.2 IPBus Bridge (IPBB)
  • 1.6 5685x Memory
    • 1.6.1 Program SRAM
    • 1.6.2 Data SRAM
    • 1.6.3 Boot ROM
  • 1.7 56853 Peripheral Blocks
  • 1.8 56854 Peripheral Blocks
  • 1.9 56855 Peripheral Blocks
  • 1.10 56857 Peripheral Blocks
  • 1.11 56858 Peripheral Blocks
  • 1.12 Peripheral Descriptions
    • 1.12.1 External Memory Interface
    • 1.12.2 General Purpose Input/Output Port (GPIO)
    • 1.12.3 Serial Communications Interface (SCI)
    • 1.12.4 Enhanced Synchronous Serial Interface (ESSI)
    • 1.12.5 Quad Timer (TMR) Module
    • 1.12.6 Serial Peripheral Interface (SPI)
    • 1.12.7 Host Interface 8 (HI8)
    • 1.12.8 COP/Watchdog Timer Module
    • 1.12.9 Time of Day
    • 1.12.10 System Integration Module
    • 1.12.11 JTAG/Enhanced OnCE Port
    • 1.12.12 Six-Channel DMA Controller
    • 1.12.13 Peripheral Interrupts/Interrupt Controller
  • 1.13 56800E Programming Model
• Chapter2 Pin Descriptions
  • 2.1 Introduction
  • 2.2 Signal and Package Information
  • 2.3 Power, Ground and Peripheral Signals
• Chapter3 Memory (MEM)
  • 3.1 Introduction
  • 3.2 Program Boot ROM
    • 3.2.1 Boot Mode 0: Bootstrap From Byte-Wide External Memory
    • 3.2.2 Boot Mode 1: Bootstrap From SPI
    • 3.2.3 Boot Mode 2: Normal Expanded Mode
    • 3.2.4 Boot Mode 3: Development Expanded Mode
    • 3.2.5 Boot Mode 4: Bootstrap From Host Port�Single Strobe Clocking
    • 3.2.6 Boot Mode 5: Bootstrap From Host Port�Dual Strobe Clocking
    • 3.2.7 Boot Mode 6: Bootstrap From SCI
    • 3.2.8 Boot Mode 7: Reserved for Future Use
  • 3.3 Memory Maps
    • 3.3.1 Memory Register Summary
    • 3.3.2 Interrupt Vectors
• Chapter4 System Integration Module (SIM)
  • 4.1 Introduction
  • 4.2 Features
  • 4.3 Block Diagram
  • 4.4 Signal Description
    • 4.4.1 SIM Interface Signals
  • 4.5 Module Memory Map
  • 4.6 Register Descriptions (SYS_BASE = $1FFF08)
    • 4.6.1 SIM Control Register (SCR)
    • 4.6.2 SIM Software Control Data 1 (SCD1)
    • 4.6.3 SIM Software Control Data 2 (SCD2)
  • 4.7 Clock Generation Concepts
  • 4.8 Generated Clocks
  • 4.9 Power Mode Controls
  • 4.10 Resets
• Chapter5 External Memory Interface (EMI)
  • 5.1 Introduction
  • 5.2 Features
  • 5.3 Functional Description
    • 5.3.1 Core Interface Detail
  • 5.4 Block Diagram
  • 5.5 Module Memory Map
  • 5.6 Register Descriptions (EMI_BASE = $1FFE40)
    • 5.6.1 Chip Select Base Address Registers 0�3 (CSBAR0�CSBAR3)
    • 5.6.2 Chip Select Option Registers 0�3 (CSOR0�CSOR3)
    • 5.6.3 Chip Select Timing Control Registers 0�3 (CSTC0�CSTC3)
    • 5.6.4 Bus Control Register (BCR)
  • 5.7 Timing Specifications
    • 5.7.1 Read Timing
    • 5.7.2 Write Timing
  • 5.1 Clocks
  • 5.1 Interrupts
  • 5.1 Resets
• Chapter6 On-Chip Clock Synthesis (OCCS)
  • 6.1 Introduction
    • 6.1.1 OCCS Features
  • 6.2 OSC (Oscillator) Circuit Detail
    • 6.2.1 Using an External Crystal
    • 6.2.2 Using an External Active Clock Source Below 4 MHz
    • 6.2.3 Using an External Active Clock Source Above 4 MHz
    • 6.2.4 STOP Mode Features
  • 6.3 PLL (Phase Locked Loop) Circuit Detail
    • 6.3.1 Phase Frequency Detector
    • 6.3.2 Charge Pump
    • 6.3.3 Loop Filter
    • 6.3.4 Voltage Controlled Oscillator
    • 6.3.5 Down Counter
    • 6.3.6 PLL Lock Time User Notes
  • 6.4 CGM Functional Detail
    • 6.4.1 PLL Frequency Lock Detector
  • 6.5 Module Memory Map
  • 6.6 Register Descriptions (CGM_BASE = $1FFF10)
    • 6.6.1 Clock Generation Module (CGM) Control Register
    • 6.6.2 Clock Generation Module (CGM) Divide-By Register
    • 6.6.3 Clock Generation Module (CGM) Time-of-Day Register
  • 6.7 OCCS Resets
  • 6.8 OCCS Interrupts
• Chapter7 Power-On Reset (POR) and Computer Operating Properly (COP)
  • 7.1 Introduction
  • 7.2 Features
  • 7.3 Block Diagram
  • 7.4 Method of Operation
  • 7.5 Computer Operating Properly (COP) Module
    • 7.5.1 COP Functional Description
    • 7.5.2 Time-Out Specifications
    • 7.5.3 COP After Reset
    • 7.5.4 Wait Mode Operation
    • 7.5.5 Stop Mode Operation
    • 7.5.6 Debug Mode Operation
  • 7.6 Operating Modes
  • 7.7 Block Diagram
  • 7.8 Module Memory Map
  • 7.9 Register Descriptions (COP_BASE = $1FFFD0)
    • 7.9.1 COP Control Register (COPCTL)
    • 7.9.2 COP Time-Out Register (COPTO)
    • 7.9.3 COP Counter Register (COPCTR)
  • 7.10 Clocks
  • 7.11 Resets
  • 7.12 Interrupts
• Chapter8 Interrupt Controller (ITCN)
  • 8.1 Introduction
  • 8.2 Features
  • 8.3 Signal Description
  • 8.4 Module Memory Map
  • 8.5 Block Diagram
  • 8.6 Functional Description
  • 8.7 Register Descriptions (ITCN_BASE = $1FFF20)
    • 8.7.1 Interrupt Priority Register 0 (IPR0)
    • 8.7.2 Interrupt Priority Register 1 (IPR1)
    • 8.7.3 Interrupt Priority Register 2 (IPR2)
    • 8.7.4 Interrupt Priority Register 3 (IPR3)
    • 8.7.5 Interrupt Priority Register 4 (IPR4)
    • 8.7.6 Interrupt Priority Register 5 (IPR5)
    • 8.7.7 Interrupt Priority Register 6 (IPR6)
    • 8.7.8 Interrupt Priority Register 7 (IPR7)
    • 8.7.9 Interrupt Priority Register 8 (IPR8)
    • 8.7.10 Vector Base Address Register (VBA)
    • 8.7.11 Fast Interrupt Match Registers (FIM0 and FIM1)
    • 8.7.12 Fast Interrupt Vector Address Registers (FIVAL0, FIVAH0, FIVAL1, FIVAH1)
    • 8.7.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
    • 8.7.14 Fast Interrupt 1 Vector Address High Register (FIVAH1)
    • 8.7.15 IRQ Pending Registers (IRQP0, IRQP1, IRQP2, IRQP3, IRQP4)
    • 8.7.16 Interrupt Control Register (ICTL)
    • 8.7.17 Interrupt Vector Map
  • 8.8 Wait and Stop Mode Operations
  • 8.9 Host Control Interrupt Vector
  • 8.10 Resets
    • 8.10.1 Reset Handshake Timing
    • 8.10.2 ITCN After Reset
  • 8.11 Interrupts
    • 8.11.1 Interrupt Handshake Timing
    • 8.11.2 Interrupt Nesting
• Chapter9 Direct Memory Access (DMA)
  • 9.1 Introduction
  • 9.2 Features
  • 9.3 Signal Description
  • 9.4 Module Memory Maps
  • 9.5 DMA Controller Block Diagram
  • 9.6 Register Descriptions (DMA_BASES = $1FFEC0, $1FFEC8, $1FFED0, $1FFED8, $1FFEE0, $1FFEE8)
    • 9.6.1 DMA Transfer Control (DMATC)
    • 9.6.2 DMA Circular Queue Size (DMACQS)
    • 9.6.3 DMA Transfer Count (DMACNT)
    • 9.6.4 DMA Destination Address Low (DMADAL)
    • 9.6.5 DMA Destination Side Address High (DMADAH)
    • 9.6.6 DMA Source Address Low (DMASAL)
    • 9.6.7 DMA Source Address High (DMASAH)
  • 9.7 Programming Examples
    • 9.7.1 Peripheral-to-Memory DMA Operation
    • 9.7.2 Memory-to-Memory DMA Operation
    • 9.7.3 Peripheral-to-Memory Circular Queue DMA Operation
• Chapter10 Serial Communications Interface (SCI)
  • 10.1 Introduction
  • 10.2 Features
  • 10.3 Block Diagram
  • 10.4 External Pin Descriptions
    • 10.4.1 Transmit Data (TXD) Pin
    • 10.4.2 Receiver Data (RXD) Pin
  • 10.5 Module Memory Maps
  • 10.6 Functional Description
    • 10.6.1 Data Frame Format
    • 10.6.2 Baud Rate Generation
    • 10.6.3 SCI Transmitter Block Diagram
    • 10.6.4 SCI Receiver Block Diagram
    • 10.6.5 Single Wire Operation
    • 10.6.6 Loop Operation
  • 10.7 DMA Operation
    • 10.7.1 Transmit DMA Operation
    • 10.7.2 Receive DMA Operation
    • 10.7.3 Receiver Wake Up with DMA
  • 10.8 Low Power Modes
    • 10.8.1 Run Mode
    • 10.8.2 Wait Mode
    • 10.8.3 Stop Mode
    • 10.8.4 Wait Mode Recovery
  • 10.9 SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)
    • 10.9.1 SCI Baud Rate (SCIBR)
    • 10.9.2 SCI Control Register (SCICR)
    • 10.9.3 SCI Control Register 2 (SCICR2)
    • 10.9.4 SCI Status Register (SCISR)
    • 10.9.5 SCI Data Register (SCIDR)
  • 10.10 Clocks
  • 10.11 Resets
  • 10.12 Interrupts
    • 10.12.1 Transmitter Empty Interrupt
    • 10.12.2 Transmitter Idle Interrupt
    • 10.12.3 Receiver Full Interrupt
    • 10.12.4 Receive Error Interrupt
    • 10.12.5 Receiver Idle Interrupt
• Chapter11 Serial Peripheral Interface (SPI)
  • 11.1 Introduction
  • 11.2 Features
  • 11.3 SPI Block Diagram
  • 11.4 Signal Descriptions
    • 11.4.1 Master In/Slave Out (MISO)
    • 11.4.2 Master Out/Slave In (MOSI)
    • 11.4.3 Serial Clock (SCLK)
    • 11.4.4 Slave Select (SS)
  • 11.5 External I/O Signals
  • 11.6 Operating Modes
    • 11.6.1 Master Mode
    • 11.6.2 Slave Mode
    • 11.6.3 DMA Mode
    • 11.6.4 Wired OR Mode
  • 11.7 Transmission Formats
    • 11.7.1 Data Transmission Length
    • 11.7.2 Data Shift Ordering
    • 11.7.3 Clock Phase and Polarity Controls
    • 11.7.4 Transmission Format When CPHA = 0
    • 11.7.5 Transmission Format When CPHA = 1
    • 11.7.6 Transmission Initiation Latency
  • 11.8 Transmission Data
  • 11.9 Error Conditions
    • 11.9.1 Overflow Error
    • 11.9.2 Mode Fault Error
  • 11.10 Module Memory Map
  • 11.11 SPI Register Descriptions (SPI_BASE = $1FFFE8)
    • 11.11.1 SPI Status and Control Register (SPSCR)
    • 11.11.2 SPI Data Size and Control Register (SPDSCR)
    • 11.11.3 SPI Data Receive Register (SPDRR)
    • 11.11.4 SPI Data Transmit Register (SPDTR)
  • 11.12 Resets
  • 11.13 Interrupts
• Chapter12 Enhanced Synchronous Serial Interface (ESSI)
  • 12.1 Introduction
  • 12.2 Features
  • 12.3 Signal Descriptions
    • 12.3.1 Signal Properties
    • 12.3.2 External Signals Descriptions
  • 12.4 ESSI Block Diagram
  • 12.5 Functional Description
    • 12.5.1 Normal Mode
    • 12.5.2 Network Mode
    • 12.5.3 Synchronous/Asynchronous Operating Modes
    • 12.5.4 Network Mode with Mask Registers Implemented
  • 12.6 ESSI Configurations
  • 12.7 Module Memory Map
  • 12.8 Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
    • 12.8.1 ESSI Transmit Registers (STX0, STX1, STX2)
    • 12.8.2 ESSI Transmit FIFO Registers (TXFIFO0, TXFIFO1, TXFIFO2)
    • 12.8.3 ESSI Transmit Shift Registers (TXSR0, TXSR1, TXSR2)
    • 12.8.4 ESSI Receive Register (SRX)
    • 12.8.5 ESSI Receive FIFO Register (RXFIFO)
    • 12.8.6 ESSI Receive Shift Register (RXSR)
    • 12.8.7 ESSI Status Register (SSR)
    • 12.8.8 ESSI Control Register 2 (SCR2)
    • 12.8.9 ESSI Control Register 3 (SCR3)
    • 12.8.10 ESSI Control Register 4 (SCR4)
    • 12.8.11 ESSI Transmit and Receive Control Registers (STXCR, SRXCR)
    • 12.8.12 Time Slot Register (STSR)
    • 12.8.13 ESSI FIFO Control/Status Register (SFCSR)
    • 12.8.14 Transmit Slot Mask Registers (TSMA, TSMB)
    • 12.8.15 Receive Slot Mask Registers (RSMA, RSMB)
  • 12.9 Clocks
  • 12.10 Clock Operation Description
    • 12.10.1 ESSI Clock and Frame Sync Generation
  • 12.11 Resets
  • 12.12 Interrupts
  • 12.13 Interrupt Operation Description
    • 12.13.1 Receive Data With Exception
    • 12.13.2 Receive Data (RX)
    • 12.13.3 Receive Last Slot (RLS)
    • 12.13.4 Transmit Data With Exception
    • 12.13.5 Transmit Data (TX)
    • 12.13.6 Transmit Last Slot (TLS)
  • 12.14 User Notes
    • 12.14.1 External Frame Sync Setup
    • 12.14.2 Maximum External Clock Rate
• Chapter13 Quad Timer (TMR)
  • 13.1 Introduction
  • 13.2 Features
  • 13.3 Operatng Modes
  • 13.4 Block Diagram
  • 13.5 Signal Description
  • 13.6 Functional Description
  • 13.7 Counting Modes Definitions
    • 13.7.1 Stop Mode
    • 13.7.2 Count Mode
    • 13.7.3 Edge Count Mode
    • 13.7.4 Gated Count Mode
    • 13.7.5 Quadrature Count Mode
    • 13.7.6 Signed Count Mode
    • 13.7.7 Triggered Count Mode
    • 13.7.8 One-Shot Mode
    • 13.7.9 Cascade Count Mode
    • 13.7.10 Pulse Output Mode
    • 13.7.11 Fixed Frequency PWM Mode
    • 13.7.12 Variable Frequency PWM Mode
    • 13.7.13 Compare Registers Use
    • 13.7.14 Capture Register Use
  • 13.8 Module Memory Map
  • 13.9 Register Descriptions (TMR_BASE = $1FFE80)
    • 13.9.1 Timer Control Registers (CTL)
    • 13.9.2 Timer Channel Status and Control Registers (SCR)
    • 13.9.3 Timer Channel Compare Register 1 (CMP1)
    • 13.9.4 Timer Channel Compare Register 2 (CMP2)
    • 13.9.5 Timer Channel Capture Register (CAP)
    • 13.9.6 Timer Channel Load Register (LOAD)
    • 13.9.7 Timer Channel Hold Register (HOLD)
    • 13.9.8 Timer Channel Counter Register (CNTR)
  • 13.10 Resets
  • 13.11 Interrupts
    • 13.11.1 Timer Compare Interrupts
    • 13.11.2 Timer Overflow Interrupts
    • 13.11.3 Timer Input Edge Interrupts
• Chapter14 Time-Of-Day (TOD)
  • 14.1 Introduction
  • 14.2 Features
  • 14.3 Block Diagram
  • 14.4 Module Memory Map
  • 14.5 Functional Description
    • 14.5.1 Scaler
    • 14.5.2 Time Units
    • 14.5.3 Stop Mode
    • 14.5.4 General Information
    • 14.5.5 Alarm Interrupt Flag and Outputs
    • 14.5.6 1-Second Interrupt Flag and Outputs
  • 14.6 Register Description (TOD_BASE = $1FFFC0)
    • 14.6.1 TOD Register Map
    • 14.6.2 Time-of-Day Control Status (TODCS)
    • 14.6.3 Time-of-Day Clock Scaler (TODCSL)
    • 14.6.4 Time-of-Day Seconds Counter (TODSEC)
    • 14.6.5 Time-of-Day Seconds Alarm Register (TODSAL)
    • 14.6.6 Time-of-Day Minutes Register (TODMIN)
    • 14.6.7 Time-of-Day Minutes Alarm Register (TODMAL)
    • 14.6.8 Time-of-Day Hours Register (TODHR)
    • 14.6.9 Time-of-Day Hours Alarm Register (TODHAL)
    • 14.6.10 Time-of-Day Days Register (TODDAY)
    • 14.6.11 Time-of-Day Days Alarm Register (TODDAL)
• Chapter15 General Purpose Input/Output (GPIO)
  • 15.1 Introduction
  • 15.2 Features
  • 15.3 Block Diagram
  • 15.4 Functional Description
  • 15.5 Modes of Operation
    • 15.5.1 Normal Mode
    • 15.5.2 GPIO Mode
  • 15.6 GPIO Configurations
  • 15.7 Module Memory Maps
  • 15.8 Register Descriptions
    • 15.8.1 Port A Peripheral Enable Register (GPIOA_PER)
    • 15.8.2 Port B Peripheral Enable Register (GPIOB_PER)
    • 15.8.3 Port C Peripheral Enable Register (GPIOC_PER)
    • 15.8.4 Port D Peripheral Enable Register (GPIOD_PER)
    • 15.8.5 Port E Peripheral Enable Register (GPIOE_PER)
    • 15.8.6 Port F Peripheral Enables Register (GPIOF_PER)
    • 15.8.7 Port G Peripheral Enables Register (GPIOG_PER)
    • 15.8.8 Port H Peripheral Enables Register (GPIOH_PER)
    • 15.8.9 Port A Data Direction Register (GPIOA_DDR)
    • 15.8.10 Port B Data Direction Register (GPIOB_DDR)
    • 15.8.11 Port C Data Direction Register (GPIOC_DDR)
    • 15.8.12 Port D Data Direction Register (GPIOD_DDR)
    • 15.8.13 Port E Data Direction Register (GPIOE_DDR)
    • 15.8.14 Port F Data Direction Register (GPIOF_DDR)
    • 15.8.15 Port G Data Direction Register (GPIOG_DDR)
    • 15.8.16 Port H Data Direction Register (GPIOH_DDR)
    • 15.8.17 Port A Data Register (GPIOA_DR)
    • 15.8.18 Port B Data Register (GPIOB_DR)
    • 15.8.19 Port C Data Register (GPIOC_DR)
    • 15.8.20 Port D Data Register (GPIOD_DR)
    • 15.8.21 Port E Data Register (GPIOE_DR)
    • 15.8.22 Port F Data Register (GPIOF_DR)
    • 15.8.23 Port G Data Register (GPIOG_DR)
    • 15.8.24 Port H Data Register (GPIOH_DR)
    • 15.8.25 Port A Pull-Up Enable Register (GPIOA_PUER)
    • 15.8.26 Port B Pull-Up Enable Register (GPIOB_PUER)
    • 15.8.27 Port C Pull-Up Enable Register (GPIOC_PUER)
    • 15.8.28 Port D Pull-Up Enable Register (GPIOD_PUER)
    • 15.8.29 Port E Pull-Up Enable Register (GPIOE_PUER)
    • 15.8.30 Port F Pull-Up Enable Register (GPIOF_PUER)
    • 15.8.31 Port G Pull-Up Enable Register (GPIOG_PUER)
    • 15.8.32 Port H Pull-Up Enable Register (GPIOH_PUER)
  • 15.9 Data Register Access
  • 15.10 Resets
  • 15.11 Interrupts
• Chapter16 Host Interface Eight (HI8)
  • 16.1 Introduction
  • 16.2 Features
    • 16.2.1 Dgital Signal Controller (DSC) Side
    • 16.2.2 Host Side
  • 16.3 Signal Descriptions
  • 16.4 HI8 Host Port
  • 16.5 HI8 Block Diagram
  • 16.6 DSC Side Register Descriptions (HI8_BASE = $1FFFD8)
  • 16.7 Host Side Register Descriptions
  • 16.8 DSC Side Registers
    • 16.8.1 HI8 Control Register (HCR)
    • 16.8.2 HI8 Status Register (HSR)
    • 16.8.3 HI8 Transmit Data Register (HTX)
    • 16.8.4 HI8 Receive Data Register (HRX)
    • 16.8.5 DSC Side Registers After Reset
    • 16.8.6 HI8 DSC Core Interrupts
  • 16.9 Host Side Registers
    • 16.9.1 Interface Control Register (ICR)
    • 16.9.2 Command Vector Register (CVR)
  • 16.10 Servicing the Host Interface
    • 16.10.1 Interface Status Register (ISR)
    • 16.10.2 Interrupt Vector Register (IVR)
    • 16.10.3 Receive Byte Registers (RXH, RXL)
    • 16.10.4 Transmit Byte Registers (TXH, TXL)
    • 16.10.5 Host Side Registers After Reset
    • 16.10.6 HI8 Host Processor Data Transfer
    • 16.10.7 Polling
    • 16.10.8 Servicing Interrupts
    • 16.10.9 Host Side DMA Mode Operation
    • 16.10.10 Host Port Use Considerations
• Chapter17 JTAG Port
  • 17.1 Introduction
  • 17.2 Features
  • 17.3 Master Test Access Port (TAP)
    • 17.3.1 Signal Description
  • 17.4 TAP Block Diagram
  • 17.5 JTAG Port Architecture
    • 17.5.1 JTAG Instruction Register (JTAGIR) and Decoder
    • 17.5.2 Sample and Preload Instructions (SAMPLE/PRELOAD)
    • 17.5.3 JTAG Chip Identification (CID) Register
  • 17.6 Bypass Register (BYPASS)
  • 17.7 JTAG Boundary Scan Register (BSR)
  • 17.8 TAP Controller
    • 17.8.1 Operation
  • 17.9 5685x Restrictions
• AppendixA Glossary
• AppendixB Programmer�s Sheets