56F802 Technical Data, Rev. 7

Freescale Semiconductor

56F802 Block Diagram

JTAG/
OnCE

Port

Digital Reg

Analog Reg

Low Voltage

Supervisor

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Manipulation

Unit

16-Bit
56800

Core

PAB

PDB

XDB2

CGDB

XAB1
XAB2

INTERRUPT

CONTROLS

IPBB

CONTROLS

IPBus Bridge

(IPBB)

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

COP RESET

RESET

Applica-

tion-Specific

Memory &

Peripherals

Interrupt

Controller

Program Memory

8188 x 16 Flash

1024 x 16 SRAM

Boot Flash

2048x 16 Flash

Data Memory

2048 x 16 Flash

1024 x 16 SRAM

COP/

Watchdog

SCI0

GPIO

Quad Timer D

or GPIO

Quad Timer C

A/D1
A/D2

ADC

PWM Outputs

PWMA

VCAPC V

* V

DDA

SSA

VREF

PLL

Relaxation

Oscillator

includes TCS pin which is reserved for factory use and is tied to

VSS

Fault A0

· Up to 30 MIPS operation at 60MHz core frequency
· Up to 40 MIPS operation at 80MHz core frequency
· DSP and MCU functionality in a unified,

C-efficient architecture

· MCU-friendly instruction set supports both DSP and

controller functions: MAC, bit manipulation unit, 14

addressing modes

· Hardware DO and REP loops
· 6-channel PWM Module with fault input
· Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
· Serial Communications Interface (SCI)
· Two General Purpose Quad Timers with 2 external

outputs

· 8K

× 16-bit words (16KB) Program Flash

· 1K

× 16-bit words (2KB) Program RAM

· 2K

× 16-bit words (4KB) Data Flash

· 1K

× 16-bit words (2KB) Data RAM

· 2K

× 16-bit words (4KB) Boot Flash

· JTAG/OnCE

port for debugging

· On-chip relaxation oscillator
· 4 shared GPIO
· 32-pin LQFP Package

56F802 General Description

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Part 1 Overview

1.1 56F802 Features

1.1.1

Processing Core

Efficient 16-bit 56800 family controller engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency

Single-cycle 16

× 16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators including extension bits

16-bit bidirectional barrel shifter

Parallel instruction set with unique processor addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE debug programming interface

1.1.2

Memory

Harvard architecture permits as many as three simultaneous accesses to program and data memory

On-chip memory including a low-cost, high-volume Flash solution
-- 8K

× 16 bit words of Program Flash

-- 1K

× 16-bit words of Program RAM

-- 2K

× 16-bit words of Data Flash

-- 1K

× 16-bit words of Data RAM

-- 2K

× 16-bit words of Boot Flash

Programmable Boot Flash supports customized boot code and field upgrades of stored code through a

variety of interfaces (JTAG)

1.1.3

Peripheral Circuits for 56F802

Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection;

supports both center- and edge-aligned modes

Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support two

simultaneous conversions; ADC and PWM modules can be synchronized

Two General Purpose Quad Timers with two external pins (or two GPIO)

Serial Communication Interface (SCI) with two pins (or two GPIO)

Four multiplexed General Purpose I/O (GPIO) pins

56F802 Description

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Computer-Operating Properly (COP) watchdog timer

External interrupts via GPIO

Trimmable on-chip relaxation oscillator

External reset pin for hardware reset

JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

1.1.4

Energy Information

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

Uses a single 3.3V power supply

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

Integrated power supervisor

1.2 56F802 Description

The 56F802 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many
peripherals that are especially useful for applications such as motion control, home appliances, encoders,
tachometers, limit switches, power supply and control, engine management, and industrial control for
power, lighting, automation and HVAC.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.

The 56F802 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4
General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.

A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time

56F802 Technical Data, Rev. 7

Freescale Semiconductor

insertion, and separate top and bottom output polarity control. The up-counter value is programmable to
support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width
control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:
ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM
(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection
with sufficient output drive capability to directly drive standard opto-isolators. A "smoke-inhibit",
write-once protection feature for key parameters is also included. The PWM is double-buffered and
includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The PWM
modules provide a reference output to synchronize the Analog-to-Digital Converters.

The 56F802 incorporates two 12-bit Analog-to-Digital Converters (ADCs) with a total of five channels.
A full set of standard programmable peripherals is provided that include a Serial Communications
Interface (SCI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator eliminates the need
for an external crystal.

1.3 State of the Art Development Environment

Processor Expert

(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.

The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards

will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable

tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in

Table 1-1

are required for a complete description and proper design with the

56F802. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56F802 Chip Documentation

Topic

Description

Order Number

56800E

Family Manual

Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set

56800EFM

DSP56F801/803/805/807
User's Manual

Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F802, 56F803, 56F805, and 56F807

DSP56F801-7UM

56F802

Technical Data Sheet

Electrical and timing specifications, pin descriptions, and
package descriptions (this document)

DSP56F802

56F802
Errata

Details any chip issues that might be present

56F802E

Data Sheet Conventions

56F802 Technical Data, Rev. 7

Freescale Semiconductor

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

"asserted"

A high true (active high) signal is high or a low true (active low) signal is low.

"deasserted"

A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

1. Values for V

, V

, and V

are defined by individual product specifications

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F802 are organized into functional groups, as shown in

Table 2-1

and as illustrated in

Figure 2-1

. In

Table 2-2

through

Table 2-10

, each table row describes the signal or

signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of

Pins

Detailed

Description

Power (V

or V

DDA

)

Table 2-2

Ground (V

SS,

SSA,

TCS)

Table 2-3

Supply Capacitors

Table 2-4

Program Control

Table 2-5

Pulse Width Modulator (PWM) Port and Fault Input

Table 2-6

Serial Communications Interface (SCI) Port

1. Alternately, GPIO pins

Table 2-7

Analog-to-Digital Converter (ADC) Port (including V

REF)

Table 2-8

Quad Timer Module Port

Table 2-9

JTAG/On-Chip Emulation (OnCE)

Table 2-10

56F802 Technical Data, Rev. 7

Freescale Semiconductor

2.2 Power and Ground Signals

Table 2-2 Power Inputs

No. of Pins

Signal Name

Signal Description

Power--These pins provide power to the internal structures of the chip, and should
all be attached to V

DD.

DDA

Analog Power--This pin is a dedicated power pin for the analog portion of the chip
and should be connected to a low noise 3.3V supply.

Table 2-3 Grounds

No. of Pins

Signal Name

Signal Description

GND--These pins provide grounding for the internal structures of the chip, and should
all be attached to V

SS.

SSA

Analog Ground--This pin supplies an analog ground.

TCS

TCS--This Schmitt pin is reserved for factory use and must be tied to V

for normal

use. In block diagrams, this pin is considered an additional V

SS.

Table 2-4 Supply Capacitors and VPP

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

VCAPC

Supply

VCAPC--Connect each pin to a 2.2

µF or greater bypass

capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, refer to

Section 5.2

Interrupt and Program Control Signals

56F802 Technical Data, Rev. 7

Freescale Semiconductor

2.3 Interrupt and Program Control Signals

2.4 Pulse Width Modulator (PWM) Signals

2.5 Serial Communications Interface (SCI) Signals

Table 2-5 Program Control Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

RESET

Input

(Schmitt)

Input

Reset--This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.

To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.

Table 2-6 Pulse Width Modulator (PWMA) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

PWMA0-5

Output

Tri-stated

PWMA0-5-- These are six PWMA output pins.

FAULTA0

Input

(Schmitt)

Input

FAULTA0 --This fault input is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.

Table 2-7 Serial Communications Interface (SCI0) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TXD0

GPIOB0

Output

Input/Ou

tput

Input

Transmit Data (TXD0)--SCI0 transmit data output

Port B GPIO--This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.

After reset, the default state is SCI output.

56F802 Technical Data, Rev. 7

Freescale Semiconductor

2.6 Analog-to-Digital Converter (ADC) Signals

2.7 Quad Timer Module Signals

RXD0

GPIOB1

Input

Input/

Output

Input

Receive Data (RXD0)--SCI0 receive data input

Port B GPIO--This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.

After reset, the default state is SCI input.

Table 2-8 Analog to Digital Converter Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

ANA2-4

Input

ANA2-4--Analog inputs to ADC, channel 1

ANA6-7

Input

ANA6-7--Analog inputs to ADC, channel 2

VREF

Input

VREF--Analog reference voltage. Must be set to V

DDA

- 0.3V for

optimal performance.

Table 2-9 Quad Timer Module Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TD1-2

GPIOA1-2

Input/

Output

Input/

Output

Input

TD1-2--Timer D Channel 1-2

Port A GPIO--These pins are General Purpose I/O (GPIO) pins that
can be individually programmed as input or output pins.

After reset, the default state is the quad timer input.

Table 2-7 Serial Communications Interface (SCI0) Signals (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

JTAG/OnCE

56F802 Technical Data, Rev. 7

Freescale Semiconductor

2.8 JTAG/OnCE

Table 2-10 JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TCK

Input

(Schmitt)

Input, pulled

low internally

Test Clock Input--This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.

TMS

Input

(Schmitt)

Input, pulled

high internally

Test Mode Select Input--This input pin is used to sequence the JTAG TAP
controller's state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.

TDI

Input

(Schmitt)

Input, pulled

high internally

Test Data Input--This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.

TDO

Output

Tri-stated

Test Data Output--This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.

TRST

Input

(Schmitt)

Input, pulled

high internally

Test Reset--As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted at power-up and whenever RESET is asserted. The only exception
occurs in a debugging environment, since the OnCE/JTAG module is under
the control of the debugger. In this case it is not necessary to assert TRST
when asserting RESET. Outside of a debugging environment RESET should
be permanently asserted by grounding the signal, thus disabling the
OnCE/JTAG module on the device.

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Part 3 Specifications

3.1 General Characteristics

The 56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

± 10% during

normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in

Table 3-1

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56F802 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Table 3-1 Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage

0.3

+ 4.0

All other input voltages, excluding Analog inputs

0.3

+ 5.5V

Analog Inputs ANAx, V

REF

0.3

DDA

+ 0.3V

Current drain per pin excluding V

, V

, & PWM ouputs

General Characteristics

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Notes:

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.

Determined on 2s2p thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (

) was simulated to be equivalent to the JEDEC

specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on

a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number

of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R

), was simulated to be equivalent to the measured values

using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold

plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.

Table 3-2 Recommended Operating Conditions

Characteristic

Symbol

Min

Typ

Max

Unit

Supply voltage, digital

3.0

3.3

3.6

Supply Voltage, analog

DDA

3.0

3.3

3.6

ADC reference voltage

1. VREF must be 0.3V below V

DDA

VREF

2.7

DDA

Ambient operating temperature

°C

Table 3-3 Thermal Characteristics

Characteristic

Comments

Symbol

Value

Unit

Note

32-pin LQFP

Junction to ambient
Natural convection

50.2

°C/W

Junction to ambient (@1m/sec)

JMA

47.1

°C/W

Junction to ambient
Natural convection

Four layer board (2s2p)

JMA

(2s2p)

38.7

°C/W

1,2

Junction to ambient (@1m/sec)

Four layer board (2s2p)

JMA

37.4

°C/W

1,2

Junction to case

17.8

°C/W

Junction to center of case

3.07

°C/W

I/O pin power dissipation

I/O

User Determined

Power dissipation

= (I

x V

+ P

I/O

)

Junction to center of case

DMAX

(TJ - TA) /R

56F802 Technical Data, Rev. 7

Freescale Semiconductor

4. Thermal Characterization Parameter, Psi-JT (

), is the "resistance" from junction to reference point

thermocouple on top center of case as defined in JESD51-2.

is a useful value to use to estimate junction

temperature in steady state customer environments.

5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and

board thermal resistance.

6. See Section 5.1 from more details on thermal design considerations.
7. TJ = Junction Temperature

TA = Ambient Temperature

3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C, C

50pF

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

IHC

2.25

2.75

Input low voltage (XTAL/EXTAL)

ILC

0.5

Input high voltage (Schmitt trigger inputs)

IHS

2.2

5.5

Input low voltage (Schmitt trigger inputs)

ILS

-0.3

0.8

Input high voltage (all other digital inputs)

2.0

5.5

Input low voltage (all other digital inputs)

-0.3

0.8

Input current high (pullup/pulldown resistors disabled, V

)

-1

µA

Input current low (pullup/pulldown resistors disabled, V

)

-1

µA

Input current high (with pullup resistor, V

)

IHPU

-1

µA

Input current low (with pullup resistor, V

)

ILPU

-210

-50

µA

Input current high (with pulldown resistor, V

)

IHPD

180

µA

Input current low (with pulldown resistor, V

)

ILPD

-1

µA

Nominal pullup or pulldown resistor value

, R

Output tri-state current low

OZL

-10

µA

Output tri-state current high

OZH

-10

µA

Input current high (analog inputs, V

DDA

)

IHA

-15

µA

DC Electrical Characteristics

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Input current low (analog inputs, V

SSA

)

ILA

-15

µA

Output High Voltage (at IOH)

0.7

Output Low Voltage (at IOL)

0.4

Output source current

Output sink current

PWM pin output source current

OHP

PWM pin output sink current

OLP

Input capacitance

Output capacitance

OUT

supply current

DDT

Run

(80MHz Operation)

120

130

Run

(60MHz Operation)

102

111

Wait

102

Stop

Low Voltage Interrupt, external power supply

EIO

2.4

2.7

3.0

Low Voltage Interrupt, internal power supply

EIC

2.0

2.2

2.4

Power on Reset

POR

1.7

2.0

1. Schmitt Trigger inputs are: FAULTA0, TCS, TCK, TMS, TDI, RESET, and TRST

2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

3. PWM pin output source current measured with 50% duty cycle.

4. PWM pin output sink current measured with 50% duty cycle.

5. I

DDT

= I

+ I

DDA

(Total supply current for V

+ V

DDA

)

6. Run (operating) I

measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;

measured with all modules enabled.

7. Wait I

measured using external square wave clock source (f

osc

= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less

than 50pF on all outputs. C

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I

; measured

with PLL enabled.

8. This low voltage interrupt monitors the V

DDA

external power supply. V

DDA

is generally connected to the same potential as V

via

separate traces. If V

DDA

drops below V

EIO

, an interrupt is generated. Functionality of the device is guaranteed under transient conditions

when V

DDA

EIO

(between the minimum specified V

and the point when the V

EIO

interrupt is generated).

Table 3-4 DC Electrical Characteristics (Continued)

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C, C

50pF

Characteristic

Symbol

Min

Typ

Max

Unit

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in

Table 3-4

)

3.3 AC Electrical Characteristics

Timing waveforms in

Section 3.3

are tested using the V

and V

levels specified in the DC Characteristics

table. In

Figure 3-2

the levels of V

and V

for an input signal are shown.

Figure 3-2 Input Signal Measurement References

9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below V

EIC

, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless

the external power supply drops below the minimum specified value (3.0V).

10. Power

on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,

this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally
regulated voltage is typically 100 mV less than V

during ramp up until 2.5V is reached, at which time it self regulates.

120

160

Freq. (MHz)

IDD (mA

)

IDD Digital

IDD Analog

IDD Total

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

90%

50%

10%

Rise Time

Flash Memory Characteristics

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Figure 3-3

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state

Tri-stated, when a bus or signal is placed in a high impedance state

Data Valid state, when a signal level has reached V

or V

Data Invalid state, when a signal level is in transition between V

and V

Figure 3-3 Signal States

3.4 Flash Memory Characteristics

Table 3-5 Flash Memory Truth Table

Mode

1. X address enable, all rows are disabled when XE = 0

2. Y address enable, YMUX is disabled when YE = 0

3. Sense amplifier enable

4. Output enable, tri-state Flash data out bus when OE = 0

PROG

5. Defines program cycle

ERASE

6. Defines erase cycle

MAS1

7. Defines mass erase cycle, erase whole block

NVSTR

8. Defines non-volatile store cycle

Standby

Read

Word Program

Page Erase

Mass Erase

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Table 3-6 IFREN Truth Table

Mode

IFREN = 1

IFREN = 0

Read

Read information block

Read main memory block

Word program

Program information block

Program main memory block

Page erase

Erase information block

Erase main memory block

Mass erase

Erase both blocks

Erase main memory block

Table 3-7 Flash Timing Parameters

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6V, T

= 40

° to +85°C, C

50pF

Characteristic

Symbol

Min

Typ

Max

Unit

Figure

Program time

prog*

Figure 3-4

Erase time

erase*

Figure 3-5

Mass erase time

me*

100

Figure 3-6

Endurance

1. One Cycle is equal to an erase program and read.

CYC

10,000

20,000

cycles

Data Retention

@ 5000 cycles

RET

years

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set
up time

nvs*

Figure 3-4

Figure 3-5

Figure 3-6

NVSTR hold time

nvh*

Figure 3-4

Figure 3-5

NVSTR hold time (mass erase)

nvh1*

100

Figure 3-6

NVSTR to program set up time

pgs*

Figure 3-4

Recovery time

rcv*

Figure 3-4

Figure 3-5

Figure 3-6

Cumulative program
HV period

Figure 3-4

Program hold time

pgh

Figure 3-4

Address/data set up time

ads

Figure 3-4

Address/data hold time

adh

Figure 3-4

Clock Operation

56F802 Technical Data, Rev. 7

Freescale Semiconductor

3.5 Clock Operation

The 56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates a
master reference frequency that determines the speed at which chip operations occur.

The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.

3.5.1

Use of On-Chip Relaxation Oscillator

The 56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal
or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting the 8-bit
IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output frequency of
the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures 9 and 10
show the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim
value.

During factory production test, an oscillator calibration procedure is executed which determines an
optimum trim value for a given device (8MHz at 25

C). This optimum trim value is then stored at address

$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence
(executed after power-up and RESET). This trim routine automatically sets the oscillator frequency by
programming the IOSCTL register with the optimum trim value.

Due to the inherent frequency tolerances required for SCI communication, changing the factory-trimmed
oscillator frequency is not recommended. If modification of the Boot Flash contents are required, code
must be included which retrieves the optimum trim value (from address $103F in the Data Flash
Information Block) and writes it to the IOSCTL register. Note that the IFREN bit in the Data Flash control
register must be set in order to read the Data Flash Information Block.

Table 3-8 Relaxation Oscillator Characteristics

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency Accuracy

1. Over full temperature range.

Frequency Drift over Temp

f/t

+0.1

Frequency Drift over Supply

f/V

0.1

%/V

Reset, Stop, Wait, Mode Select, and Interrupt Timing

56F802 Technical Data, Rev. 7

Freescale Semiconductor

3.5.2

Phase Locked Loop Timing

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-9 PLL Timing

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency for the PLL

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.

2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f

out

/2, please refer to the OCCS chapter in the

User Manual. ZCLK = f

3. Will not exceed 60MHz for the DSP56F802TA60 device.

4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

osc

MHz

PLL output frequency

out

MHz

PLL stabilization time

to +85

plls

PLL stabilization time

-40

to 0

plls

100

200

Table 3-10 Reset, Stop, Wait, Mode Select, and Interrupt Timing

1, 3

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C, C

50pF

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

RESET Assertion to Address, Data and Control Signals High
Impedance

RAZ

Minimum RESET Assertion Duration

OMR Bit 6 = 0
OMR Bit 6 = 1

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

· After power-on reset

· When recovering from Stop state

3. Parameters listed are guaranteed by design.

275,000T

128T

--
--

ns
ns

RESET De-assertion to First External Address Output

RDA

33T

34T

Edge-sensitive Interrupt Request Width

IRW

1.5T

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Figure 3-9 External Level-Sensitive Interrupt Timing

3.7 Quad Timer Timing

Figure 3-10 Timer Timing

Table 3-11 Timer Timing

1, 2

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C, C

50pF

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.

2. Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

4T+6

Timer input high/low period

INHL

2T+3

Timer output period

OUT

Timer output high/low period

OUTHL

General

Purpose

I/O Pin

IRQA

b) General Purpose I/O

Timer Inputs

Timer Outputs

OUTHL

OUT

INHL

Serial Communication Interface (SCI) Timing

56F802 Technical Data, Rev. 7

Freescale Semiconductor

3.8 Serial Communication Interface (SCI) Timing

Figure 3-11 RXD Pulse Width

Figure 3-12 TXD Pulse Width

Table 3-12 SCI Timing

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C, C

50pF

Characteristic

Symbol

Min

Max

Unit

Baud Rate

1. f

MAX

is the frequency of operation of the system clock in MHz.

MAX

*2.5)/(80)

Mbps

RXD

Pulse Width

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

TXD

Pulse Width

3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

4. Parameters listed are guaranteed by design.

TXD

0.965/BR

1.04/BR

RXD

SCI receive

data pin

(Input)

RXD

TXD

SCI receive

data pin

(Input)

TXD

56F802 Technical Data, Rev. 7

Freescale Semiconductor

3.9 Analog-to-Digital Converter (ADC) Characteristics

Table 3-13 ADC Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

ADC input voltages

ADCIN

1. For optimum ADC performance,keep the minimum V

ADCIN

value > 250mV. Inputs less than 250mV volts may convert

to a digital output code of 0 or cause erroneous conversions.

REF

2. V

REF

must be equal to or less than V

DDA

- 0.3V and must be greater than 2.7V.

Resolution

Bits

Integral Non-Linearity

3. Measured in 10-90% range.

INL

+/- 4

+/- 5

LSB

4. LSB = Least Significant Bit.

Differential Non-Linearity

DNL

+/- 0.9

+/- 1

LSB

Monotonicity

GUARANTEED

ADC internal clock

5. Guaranteed by characterization.

ADIC

0.5

MHz

Conversion range

SSA

DDA

Power-up time

ADPU

2.5

msec

Conversion time

ADC

AIC

cycles

6. t

AIC

= 1/

ADIC

Sample time

ADS

AIC

cycles

Input capacitance

ADI

Gain Error (transfer gain)

GAIN

1.00

1.10

1.15

Offset Voltage

OFFSET

+10

+230

+325

Total Harmonic Distortion

THD

Signal-to-Noise plus Distortion

SINAD

Effective Number of Bits

ENOB

8.5

9.5

bit

Spurious Free Dynamic Range

SFDR

Spurious Free Dynamic Range

SFDR

ADC Quiescent Current (both ADCs)

ADC

REF

Quiescent Current (both ADCs)

VREF

16.5

JTAG Timing

56F802 Technical Data, Rev. 7

Freescale Semiconductor

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at
sampling time. (1pf)

Figure 3-13 Equivalent Analog Input Circuit

3.10 JTAG Timing

Table 3-14 JTAG Timing

1, 3

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

° to +85°C, C

50 pF

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz

operation, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters listed are guaranteed by design.

MHz

TCK cycle time

100

TCK clock pulse width

TMS, TDI data setup time

0.4

TMS, TDI data hold time

1.2

TCK low to TDO data valid

26.6

TCK low to TDO tri-state

23.5

TRST assertion time

TRST

ADC analog input

Package and Pin-Out Information 56F802

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Figure 4-2 32-pin LQFP Mechanical Information (Case 873A)

Please see www.freescale.com for the most current case outline.

NOTES:

DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

CONTROLLING DIMENSION: MILLIMETER.

DATUM PLANE A, B AND D TO BE DETERMINED
AT DATUM PLANE H.

DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.

DIMENSIONS b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION
BY MORE THEN 0.08 MM. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTURSION: 0.07 MM.

DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
MM PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC
BODY SIZE DIMENSIONS INCLUDING MOLD
MISMATCH.

EXACT SHAPE OF EACH CORNER IS OPTIONAL.

THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.25
MM FROM THE LEAD TIP.

DIM

MIN

MAX

MILLIMETERS

0.30

0.40

0.09

0.20

0.09

0.16

7.00 BSC

1.00 REF

0.70

0.08

0.20

1.40

1.60

0.05

1.45

0.15

1.35

0.45

0.30

9.00 BSC

0.20 REF

0.80 BSC

9.00 BSC

7.00 BSC

0.50

° REF

0.08

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, in

°C can be obtained from the equation:

Equation 1:

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether

the thermal performance is adequate, a system level model may be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the

chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation

across the surface.

(

)

Electrical Design Considerations

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Measure the thermal resistance from the junction to where the leads are attached to the case. This definition

is approximately equal to a junction to board thermal resistance.

Use the value obtained by the equation (T

)/P

where T

is the temperature of the package case

determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.

5.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

Provide a low-impedance path from the board power supply to each V

pin on the controller, and from the

board ground to each V

(GND) pin.

The minimum bypass requirement is to place 0.1

µF capacitors positioned as close as possible to the

package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of

the V

pairs, including V

DDA

SSA.

Ceramic and tantalum capacitors tend to provide better

performance tolerances.

CAUTION

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and V

(GND)

pins are less than 0.5 inch per capacitor lead.

Bypass the V

and V

layers of the PCB with approximately 100

µF, preferably with ceramic or tantalum

capacitors which tend to provide better performance tolerances.

Because the controller's output signals have fast rise and fall times, PCB trace lengths should be minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the V

and GND circuits.

Take special care to minimize noise levels on the VREF, V

DDA

and V

SSA

pins.

Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or

debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means

to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs

that do not require debugging functionality, such as consumer products, TRST should be tied low.

Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an

interface to this port to allow in-circuit Flash programming.

Electrical Design Considerations

56F802 Technical Data, Rev. 7

Freescale Semiconductor

Part 6 Ordering Information

Table 6-1

lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

*This package is RoHS compliant.

Table 6-1 56F802 Ordering Information

Part

Supply

Voltage

Package Type

Pin

Count

Frequency

(MHz)

Order Number

56F802

3.03.6 V

Low Profile Plastic Quad Flat Pack (LQFP)

DSP56F802TA80

56F802

3.03.6 V

Low Profile Plastic Quad Flat Pack (LQFP)

DSP56F802TA60

56F802

3.03.6 V

Low Profile Plastic Quad Flat Pack (LQFP)

DSP56F802TA80E*

56F802

3.03.6 V

Low Profile Plastic Quad Flat Pack (LQFP)

DSP56F802TA60E*

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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor,
Inc. All other product or service names are the property of their respective owners.

DSP56F802
Rev. 7
07/2005

Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.

Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
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particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. "Typical" parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including "Typicals", must be validated for each customer
application by customer's technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
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Document Outline

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