MC100ES6014
Rev 3, 06/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
2.5 V/3.3 V 1:5 Differential
ECL/PECL/HSTL/LVDS Clock Driver
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock
distribution in mind, accepting two clock sources into an input multiplexer. The
ECL/PECL input signals can be either differential or single-ended (if the V
BB
output is used). HSTL and LVDS inputs can be used when the ES6014 is
operating under PECL conditions.
The ES6014 specifically guarantees low output-to-output skew. Optimal
design, layout, and processing minimize skew within a device and from device to
device.
To ensure that the tight skew specification is realized, both sides of any
differential output need to be terminated identically into 50
even if only one
output is being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the
LOW state. This avoids a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop is clocked on
the falling edge of the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
The MC100ES6014, as with most other ECL devices, can be operated from a
positive V
CC
supply in PECL mode. This allows the ES6014 to be used for high
performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK
input pin operation is limited to a V
CC
3.0 V in PECL mode, or V
EE
3.0 V in
ECL mode. Designers can take advantage of the ES6014's performance to
distribute low skew clocks across the backplane or the board.
Features
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
ECL Mode: V
CC
= 0 V with V
EE
= 2.375 V to 3.8 V
LVDS and HSTL Input Compatible
Open Input Default State
20-Lead Pb-Free Package Available
MC100ES6014
ORDERING INFORMATION
Device
Package
MC100ES6014DT
TSSOP-20
MC100ES6014DTR2
TSSOP-20
MC100ES6014EJ
TSSOP-20 (Pb-Free)
MC100ES6014EJR2
TSSOP-20 (Pb-Free)
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
Advanced Clock Drivers Device Data
2
Freescale Semiconductor
MC100ES6014
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
* Pins will default LOW when left open.
** Pins will default to V
CC
/2 when left open.
* On next negative transition of CLK0 or CLK1
4
3
5
6
7
8
9
10
2
1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
17
18
16
15
14
13
12
11
19
20
1
0
D
Q
V
CC
EN
V
CC
CLK1
CLK1
V
BB
CLK0
CLK0 CLK_SEL
V
EE
Table 1. Pin Description
Pin
Function
CLK0*, CLK0**
ECL/PECL/HSTL CLK Input
CLK1*, CLK1**
ECL/PECL/HSTL CLK Input
Q0:4, Q0:4
ECL/PECL Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
EN*
ECL Sync Enable
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
Table 2. Function Table
CLK0
CLK1
CLK_SEL
EN
Q
L
H
X
X
X
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
Table 3. General specifications
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
75 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2000 V
> 200 V
> 1500 V
Thermal Resistance (Junction-to-Ambient)
0 LFPM, 20 TSSOP
500 LFPM, 20 TSSOP
140
C/W
100
C/W
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
MC100ES6014
Table 4. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol
Characteristic
Conditions
Rating
Units
V
SUPPLY
Power Supply Voltage
Difference between V
CC
& V
EE
3.9
V
V
IN
Input Voltage
V
CC
V
EE
3.6 V
V
CC
+ 0.3
V
EE
0.3
V
I
OUT
Output Current
Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source Current
0.5
C
T
A
Operating Temperature Range
40 to +85
C
T
STG
Storage Temperature Range
65 to +150
C
Table 5. DC Characteristics (V
CC
= 0 V, V
EE
= 2.5 V 5% or V
CC
= 2.5 V 5%, V
EE
= 0 V)
Symbol
Characteristics
40C
0C to 85C
Unit
Min
Typ
Max
Min
Typ
Max
I
EE
Power Supply Current
30
60
30
60
mA
V
OH
Output HIGH Voltage
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
CC
1250
V
CC
990
V
CC
800
V
CC
1200
V
CC
960
V
CC
750
mV
V
OL
Output LOW Voltage
(1)
V
CC
2000 V
CC
1550 V
CC
1150 V
CC
1925 V
CC
1630 V
CC
1200
mV
V
outPP
Output Peak-to-Peak Voltage
200
200
mV
V
IH
Input HIGH Voltage
V
CC
1165
V
CC
880
V
CC
1165
V
CC
880
mV
V
IL
Input LOW Voltage
V
CC
1810
V
CC
1475 V
CC
1810
V
CC
1475
mV
V
BB
Output Reference Voltage
I
BB
= 200
A
V
CC
1400
V
CC
1200 V
CC
1400
V
CC
1200
mV
V
PP
Differential Input Voltage
(2)
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.12
1.3
0.12
1.3
mV
V
CMR
Differential Cross Point Voltage
(3)
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
V
EE
+0.2
V
CC
1.0
V
EE
+0.2
V
CC
1.0
mV
I
IN
Input Current
150
150
A
Table 6. DC Characteristics (V
CC
= 0 V, V
EE
= 3.8 V to 3.135 V or V
CC
= 3.135 V to 3.8 V, V
EE
= 0 V)
Symbol
Characteristics
40C
0C to 85C
Unit
Min
Typ
Max
Min
Typ
Max
I
EE
Power Supply Current
30
60
30
60
mA
V
OH
Output HIGH Voltage
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
CC
1150 V
CC
1020
V
CC
800
V
CC
1200
V
CC
970
V
CC
750
mV
V
OL
Output LOW Voltage
(1)
V
CC
1950 V
CC
1620 V
CC
1250 V
CC
2000 V
CC
1680 V
CC
1300
mV
V
outPP
Output Peak-to-Peak Voltage
200
200
mV
V
IH
Input HIGH Voltage
V
CC
1165
V
CC
880
V
CC
1165
V
CC
880
mV
V
IL
Input LOW Voltage
V
CC
1810
V
CC
1475 V
CC
1810
V
CC
1475
mV
V
BB
Output Reference Voltage
I
BB
= 200
A
V
CC
1400
V
CC
1200 V
CC
1400
V
CC
1200
mV
V
PP
Differential Input Voltage
(2)
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.12
1.3
0.12
1.3
V
V
CMR
Differential Cross Point Voltage
(3)
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
V
EE
+0.2
V
CC
1.1
V
EE
+0.2
V
CC
1.1
V
I
IN
Input Current
150
150
A
Advanced Clock Drivers Device Data
4
Freescale Semiconductor
MC100ES6014
Figure 2. Typical Termination for Output Driver and Device Evaluation
Table 7. AC Characteristics (V
CC
= 0 V, V
EE
= 3.8 V to 3.135 V or V
CC
= 3.135 V to 3.8 V, V
EE
= 0 V)
(1)
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V
CC
2.0 V.
Symbol
Characteristics
40C
25C
85C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
f
max
Maximum Output Frequency
2
2
2
GHz
t
PLH
t
PHL
Propagation Delay (Differential)
CLK to Q, Q
300
355
425
300
375
475
300
400
525
ps
t
SKEW
Within Device Skew
(2)
Q, Q
Device-to-Device Skew
(2)
2. Skew is measured between outputs under identical transitions.
23
45
125
23
45
175
23
45
225
ps
ps
t
JITTER
Cycle-to-Cycle Jitter
RMS (1
)
1
1
1
ps
V
PP
Input Peak-to-Peak Voltage Swing
(Differential)
200
1200
200
1200
200
1200
mV
V
CMR
Differential Cross Point Voltage
V
EE
+0.2
V
CC
1.2 V
EE
+0.2
V
CC
1.2 V
EE
+0.2
V
CC
1.2
V
t
r
/t
f
Output Rise/Fall Time (20%80%)
70
225
70
250
70
275
ps
Driver
Device
Receiver
Device
Q
D
D
Q
50
50
V
TT
V
TT
= V
CC
2.0 V
Advanced Clock Drivers Device Data
Freescale Semiconductor
5
MC100ES6014
PACKAGE DIMENSIONS
PAGE 1 OF 3
CASE 948E-03
ISSUE B
20-LEAD TSSOP PACKAGE
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