MC100ES6056
Rev 4, 06/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
2.5 V/3.3 V ECL/PECL/LVDS
Dual Differential 2:1 Multiplexer
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential
data path makes the device ideal for multiplexing low skew clock or other skew
sensitive signals. Multiple V
BB
pins are provided.
The V
BB
pin, an internally generated voltage supply, is available to this device
only. For single-ended input conditions, the unused differential input is connected
to V
BB
as a switching reference voltage. V
BB
may also rebias AC coupled inputs.
When used, decouple V
BB
and V
CC
via a 0.01
F capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, V
BB
should be left open.
The device features both individual and common select inputs to address both
data path and random logic applications.
The 100ES Series contains temperature compensation.
Features
360 ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
ECL Mode Operating Range: V
CC
= 0 V with V
EE
= 2.375 V to 3.8 V
Open Input Default State
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Outputs
LVDS Input Compatible
20-Lead Pb-Free Package Available
MC100ES6056
ORDERING INFORMATION
Device
Package
MC100ES6056DT
TSSOP-20
MC100ES6056DTR2
TSSOP-20
MC100ES6056EJ
TSSOP-20 (Pb-Free)
MC100ES6056EJR2
TSSOP-20 (Pb-Free)
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
4
3
5
6
7
8
9
10
2
1
17
18
16
15
14
13
12
11
19
20
1
0
1
0
V
CC
Q0
Q0
SEL0 COM_SEL SEL1 V
CC
Q1
Q1
V
EE
D0a
D0a
V
BB0
D0b
D0b
D1a
D1a
V
BB1
D1b
D1b
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
Advanced Clock Drivers Device Data
2
Freescale Semiconductor
MC100ES6056
* Input function will default LOW when left open.
Table 1. Pin Description
Pin
Function
D0a* D1a*
ECL Input Data a
D0a* D1a*
ECL Input Data a Invert
D0b* D1b*
ECL Input Data b
D0b* D1b*
ECL Input Data b Invert
SEL0* SEL1*
ECL Indiv. Select Input
COM_SEL*
ECL Common Select Input
V
BB0
, V
BB1
Output Reference Voltage
Q0 Q1
ECL True Outputs
Q0 Q1
ECL Inverted Outputs
V
CC
Positive Supply
V
EE
Negative Supply
Table 2. Function Table
SEL0
SEL1
COM_SEL
Q0, Q0
Q1, Q1
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
Table 3. General Specifications
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
75 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 400 V
> 2 kV
Thermal Resistance
(Junction-to-Ambient)
0 LFPM, 20 TSSOP
500 LFPM, 20 TSSOP
140
C/W
100
C/W
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
MC100ES6056
Table 4. Absolute Maximum Ratings
(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Symbol
Characteristic
Conditions
Rating
Units
V
SUPPLY
Power Supply Voltage
Difference between V
CC
& V
EE
3.9
V
V
IN
Input Voltage
V
CC
V
EE
3.6 V
V
CC
+ 0.3
V
EE
0.3
V
I
OUT
Output Current
Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source Current
0.5
C
T
A
Operating Temperature Range
40 to +85
C
T
STG
Storage Temperature Range
65 to +150
C
Table 5. DC Characteristics (V
CC
= 0 V, V
EE
= 2.5 V 5% or 3.8 V to 3.135 V; V
CC
= 2.5 V 5% or 3.135 V to 3.8 V, V
EE
= 0 V)
Symbol
Characteristics
40C
0C to 85C
Unit
Min
Typ
Max
Min
Typ
Max
I
EE
Power Supply Current
30
60
30
60
mA
V
OH
Output HIGH Voltage
(1)
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
V
CC
1085
V
CC
960
V
CC
880
V
CC
1025
V
CC
930
V
CC
860
mV
V
OL
Output LOW Voltage
(1)
V
CC
1950 V
CC
1695 V
CC
1500 V
CC
1950 V
CC
1705 V
CC
1500
mV
V
IH
Input HIGH Voltage
V
CC
1165
V
CC
880
V
CC
1165
V
CC
880
mV
V
IL
Input LOW Voltage
V
CC
1810
V
CC
1475 V
CC
1810
V
CC
1475
mV
V
BB
Output Reference Voltage
V
CC
1380 V
CC
1290 V
CC
1220 V
CC
1380 V
CC
1290 V
CC
1200
mV
V
PP
Differential Input Voltage
(2)
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
0.15
1.3
0.15
1.3
V
V
CMR
Differential Cross Point Voltage
(3)
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
V
CC
2.3
V
CC
0.8
V
CC
2.3
V
CC
0.8
V
I
IH
Input HIGH Current
150
150
A
I
IL
Input LOW Current
0.5
0.5
A
Advanced Clock Drivers Device Data
4
Freescale Semiconductor
MC100ES6056
Figure 2. Typical Termination for Output Driver and Device Evaluation
Table 6. AC Characteristics (V
CC
= 0 V; V
EE
= 2.5 V 5% or 3.8 V to 3.135 V; V
CC
= 2.5 V 5% or 3.135 V to 3.8 V;
V
EE
= 0 V)
(1)
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50
to V
CC
2.0 V.
Symbol
Characteristics
40C to 85C
Unit
Min
Typ
Max
f
max
Maximum Frequency
> 3
GHz
t
PLH
, t
PHL
Propagation Delay to Output Differential
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
300
300
300
400
430
490
500
600
650
ps
ps
ps
t
SKEW
Skew
Output-to-Output
(2)
Part-to-Part
2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are
measured from the cross point of the inputs to the cross point of the outputs.
10
50
200
ps
ps
t
JITTER
Cycle-to-Cycle Jitter
RMS (1
)
1
ps
V
PP
Minimum Input Swing
200
800
1200
mV
V
CMR
Differential Cross Point Voltage
V
CC
2.1
V
CC
1.1
V
t
r
/ t
f
Output Rise/Fall Time (20%80%)
70
120
230
ps
Driver
Device
Receiver
Device
Q
D
D
Q
50
50
V
TT
V
TT
= V
CC
2.0 V
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