MC33701
Rev 4.0, 05/2005
Freescale Semiconductor
Technical Data
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
Freescale Semiconductor, Inc., 2005. All rights reserved.
1.5 A Switch-Mode Power
Supply with Linear Regulator
The 34701 provides the means to efficiently supply the Freescale
Power QUICCTM I, II, and other families of Freescale
microprocessors and DSPs. The 34701 incorporates a high-
performance switching regulator, providing the direct supply for the
microprocessor's core, and a low dropout (LDO) linear regulator
control circuit providing the microprocessor I/O and bus voltage.
The switching regulator is a high-efficiency synchronous buck
regulator with integrated N-channel power MOSFETs to provide
protection features and to allow space-efficient, compact design.
The 34701 incorporates many advanced features; e.g., precisely
maintained up/down power sequencing, ensuring the proper
operation and protection of the CPU and power system.
Features
Operating Voltage from 2.8 V to 6.0 V
High-Accuracy Output Voltages
Fast Transient Response
Switcher Output Current Up to 1.5 A
Undervoltage Lockout and Overcurrent Protection
Enable Inputs and Programmable Watchdog Timer
Voltage Margining via I
2
CTM Bus
Reset with Programmable Power-ON Delay
Pb-Free Packaging Designated by Suffix Code EK
I
2
C is a trademark of Philips Corporation.
Figure 1. 34701 Simplified Application Diagram
POWER SUPPLY
INTEGRATED CIRCUIT
34701
ORDERING INFORMATION
Device
Temperature
Range (T
A
)
Package
MC34701EK/R2
-40 to 85C
32 SOICW
EK (Pb-FREE) SUFFIX
98AARH99137A
32-TERMINAL SOICW
Other
Circuits
RT
VBD
VDDH (I/Os)
VDDL (Core)
MPC8xxx
34701
2.8 V to 6.0 V Input
VIN2
CLKSEL
FREQ
PORESET
GND
SDA
SCL
Adjustable:
0.8 V to VIN -
Dropout
ADDR
VIN1
LDRV
LDO
LFB
CS
RST
SW
PGND
INV
VBST
BOOT
VOUT
CLKSYN
Optional
EN1
EN2
VBST
Adjustable:
0.8 V to VIN -
Dropout
VDDI
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
34701
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 34701 Simplified Internal Block Diagram
VIN1
VBST
VBD
VIN
VDDI
Internal
Supply
Boost
Control
Bandgap
Voltage
Reference
EN1
EN2
RT
ADDR
SDA
SCL
RST
Power
Sequencing
Voltage Margining
Watchdog Timer
Reset
Control
POR
Timer
Buck
Control
Logic
Buck
HS
and
LS
Driver
Thermal
Limit
I
2
C
Interface
Switcher
Oscillator
300 kHz
Ramp
Gen.
UVLO
Linear
Regulator
Control
ILim
+
-
+
-
+
-
VBST
VREF
VREF
VREF
VREF
VBST
VBST
VBST
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
LDRV
CS
LDO
LFB
LCMP
BOOT
SW
VIN2
PGND
INV
VOUT
GND
FREQ
CLKSYN
CLKSEL
(4)
(2)
(2)
(2)
8.0 V
0.8 V
Reset
Power
Enable
SysCon
I
2
C
Control
SysCon
SoftSt
Power
Down
Current Limit
PWM
Comp
Error
Amp
VLDO
VOUT
To Reset
Control
VOUT
Power
Seq
Power
Seq
I
2
C
Control
Q1
Q2
INV
LFB
Q3
Q4
To Reset
Control
Q5
Q6
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
34701
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Figure 3. Terminal Connections
Table 1.
Terminal Function Description
A functional description of each terminal can be found in the
FUNCTIONAL TERMINAL DESCRIPTION
section beginning
on
page 15
.
Terminal
Terminal
Name
Formal Name
Definition
1
FREQ
Oscillator Frequency
This switcher frequency selection terminal can be adjusted by connecting external
resistor RF to the FREQ terminal. The default switching frequency (FREQ terminal
left open or tied to VDDI) is set to 300 kHz.
2
INV
Inverting Input
Buck Controller Error Amplifier inverting input.
3
VOUT
Output Voltage
Output voltage of the buck converter. Input terminal of the switching regulator power
sequence control circuit.
4, 5
VIN2
Input Voltage 2
Buck regulator power input. Drain of the high-side power MOSFET.
6, 7
SW
Switch
Buck regulator switching node. This terminal is connected to the inductor.
8, 9
24, 25
GND
Ground
Analog ground of the IC, thermal heatsinking.
10, 11
PGND
Power Ground
Buck regulator power ground.
12
VBD
Boost Drain
Drain of the internal boost regulator power MOSFET.
13
VBST
Boost Voltage
Internal boost regulator output voltage. The internal boost regulator provides a
20 mA output current to supply the drive circuits for the integrated power MOSFETs
and the external N-channel power MOSFET of the linear regulator. The voltage at
the VBST terminal is 7.75V nominal.
14
BOOT
Bootstrap
Bootstrap capacitor input.
15
SDA
Serial Data
I
2
C bus terminal. Serial data.
16
SCL
Serial Clock
I
2
C bus terminal. Serial clock.
17
LCMP
Linear Compensation
Linear regulator compensation terminal.
18
LFB
Linear Feedback
Linear regulator feedback terminal.
19
LDO
Linear Regulator
Input terminal of the linear regulator power sequence control circuit.
CLKSYN
1
EN2
EN1
ADDR
GND
GND
V
DD1
V
IN1
LDRV
CS
LFB
LCMP
LDO
RT
CLKSEL
RST
FREQ
V
IN2
SW
SW
GND
GND
PGND
PGND
VBD
VBST
SDA
SCL
BOOT
V
IN2
INV
V
OUT
8
9
10
11
12
13
14
15
16
3
4
5
6
7
2
32
25
24
23
22
21
20
19
18
17
30
29
28
27
26
31
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
34701
TERMINAL CONNECTIONS
20
CS
Current Sense
Current sense terminal of the LDO. Overcurrent protection of the linear regulator
external power MOSFET. The voltage drop over the LDO current sense resistor RS
is sensed between the CS and LDO terminals. The LDO current limit can be adjusted
by selecting the proper value of the current sensing resistor RS.
21
LDRV
Linear Drive
LDO gate drive of the external pass N-channel MOSFET.
22
VIN1
Input Voltage 1
The input supply terminal for the integrated circuit. The internal circuits of the IC are
supplied through this terminal.
23
VDDI
Power Supply
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is
recommended.
26
ADDR
Address
I
2
C address selection. This terminal can either be left open, tied to VDDI, or
grounded through a 10 k
resistor.
27
EN1
Enable 1
Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2
inputs determines operation mode and type of power sequencing of the IC.
28
EN2
Enable 2
Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2
inputs determines operation mode and type of power sequencing of the IC.
29
RT
Reset Timer
This terminal allows programming of the Power-ON Reset delay by means of an
external RC network.
30
RST
Reset Output
(Active LOW)
The Reset Control circuit monitors both the switching regulator and the LDO
feedback voltages. It is an open drain output and has to be pulled up to some supply
voltage (e.g., the output of the LDO) by an external resistor.
31
CLKSEL
Clock Selection
This terminal sets the CLKSYN terminal as either an oscillator output or a
synchronization input terminal. The CLKSEL terminal is also used for the I
2
C
address selection.
32
CLKSYN
Clock Synchronization
Oscillator output/synchronization input terminal.
Table 1.
Terminal Function Description (continued)
A functional description of each terminal can be found in the
FUNCTIONAL TERMINAL DESCRIPTION
section beginning
on
page 15
.
Terminal
Terminal
Name
Formal Name
Definition
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
34701
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum
Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
Electrical Ratings
Supply Voltage
V
IN1
, V
IN2
-0.3 to 7.0
V
Switching Node Voltage
V
SW
-1.0 to 7.0
V
Buck Regulator Bootstrap Input Voltage (BOOT - SW)
V
IN(BOOT)
-0.3 to 8.5
V
Boost Regulator Output Voltage
V
BST
-0.3 to 8.5
V
Boost Regulator Drain Voltage
V
BD
-0.3 to 9.5
V
RST
Drain Voltage
V
RST
-0.3 to 7.0
V
Enable Terminal Voltage at EN1, EN2
V
EN
-0.3 to 7.0
V
Logic Terminal Voltage at SDA, SCL
V
LOG
-0.3 to 7.0
V
Analog Terminal Voltage
LDO, VOUT, RST
LDRV, LCMP, CS
V
OUT
V
LIN
-0.3 to 7.0
-0.3 to 8.5
V
Terminal Voltage at CLKSEL, ADDR, RT, FREQ, VDDI, CLKSYN, INV,
LFB
V
LOGIC
-0.3 to 3.6
V
ESD Voltage
(1)
Human Body Model
Machine Model
V
ESD
2000
200
V
Thermal Ratings
Storage Temperature
T
STG
-65 to 150
C
Lead Soldering Temperature
(2)
T
SOLDER
260
C
Maximum Junction Temperature
T
JMAX
125
C
Thermal Resistance
Junction to Ambient (Single Layer)
(3)
,
(4)
Junction to Ambient (Four Layers)
(3)
,
(4)
R
JA
70
55
C/W
Thermal Resistance, Junction to Base
(5)
R
JB
18
C/W
Operational Package Temperature (Ambient Temperature)
T
A
-40 to 85
C
Notes
1.
ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
=100 pF, R
ZAP
=1500
), ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
=200 pF, R
ZAP
=0
), and the Charge Device Model.
2.
Lead soldering temperature limit is for 10 seconds maximum duration.
3.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board and board thermal resistance.
4.
Per JEDEC JESD51-6 with the board horizontal
5.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
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