56F8355 Technical Data, Rev. 5.0
2
Freescale Semiconductor
Preliminary
Document Revision History
Version History
Description of Change
Rev 0.0
Initial release
Rev 1.0
Fixed typos in Section 1.1.3; Replace any reference to Flash Interface Unit with Flash
Memory Module; added note to Vcap pin in
Table 2-2
; corrected
Table 4-4
, removed
unneccessary notes in
Table 10-12
; corrected temperature range in
Table 10-14
; added
ADC calibration information to
Table 10-23
and new graphs in
Figure 10-21
Rev 2.0
Corrected 2.2
F to 0.1
F low ESR capacitor in
Table 2-2
. Replaced
Table 10-16
with
correct parameters for the 128 package pinout. Corrected (fout/2) with (fout) in
Table 10-14
.
Corrected pinout labels in
Figure 11-1
.
Rev 3.0
Adding/clarifing notes to
Table 4-4
to help clarify independent program flash blocks and
other Program Flash modes, clarification to
Table 10-22
, corrected Digital Input Current Low
(pull-up enabled) numbers in
Table 10-5
. Removed text and Table 10-2; replaced with note
to
Table 10-1
.
Rev 4.0
Correcting
Table 4-6
Address locations.
Rev 5.0
Added 56F8155 information; edited to indicate differences in 56F8355 and 56F8155. Refor-
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout the family. Clarified I/O power
description in
Table 2-2
, added note to
Table 10-7
and clarified
Section 12.3
.
Please see http://www.freescale.com/semiconductors for the most current Data Sheet revision.
56F8355 Technical Data, Rev. 5.0
Freescale Semiconductor
3
Preliminary
56F8355/56F8155 Block Diagram
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Program Controller
and Hardware
Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
56800E Core
Interrupt
Controller
COP/
Watchdog
SCI1 or
GPIOD
4
2
IRQA IRQB
Program Memory
128K x 16 Flash
2K x 16 RAM
Boot ROM
8K x 16 Flash
Data Memory
4K x 16 Flash
8K x 16 RAM
PDB
PDB
XAB1
XAB2
XDB2
CDBR
SCI0 or
GPIOE
IPBus Bridge (IPBB)
Decoding
Peripherals
Peripheral
Device Selects
RW
Control
IPAB IPWDB
IPRDB
2
System Bus
R/W Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
V
CAP
V
DD
V
SS
V
DDA
V
SSA
5
4
7
5
2
V
PP
2
RESET
RSTO
4
6
3
4
6
3
Quad Timer D
or GPIOE
Quad Timer C
or GPIOE
ADCA
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
FlexCAN
2
4
2
ADCB
Temp_Sense
4
* External
Address Bus
Switch
Ex
t
e
r
n
a
l
Bu
s
In
t
e
r
f
a
ce Un
it
* External
Data
Bus Switch
A8-13 or GPIOA0-5
D7-10 or GPIOF0-3
GPIOB0-4 or A16-20
GPIOD0-5 or CS2-7
* Bus
Control
6
5
6
* EMI not functional in
this package; use as
GPIO pins
PLL
Clock
Generator
XTAL
EXTAL
CLKMODE
Integration
Module
System
P
O
R
O
S
C
Clock
resets
CLKO
PWM Outputs
Fault Inputs
PWMA
Current Sense Inputs
or GPIOC
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
or GPIOD
OCR_DIS
4
SPI0 or
GPIOE
AD0
AD1
4
4
VREF
AD0
AD1
4
5
4
Control
56F8355/56F8155 General Description
Note: Features in italics are NOT available in the 56F8155 device.
Up to 60 MIPS at 60MHz core frequency
DSP and MCU functionality in a unified,
C-efficient architecture
256KB Program Flash
4KB Program RAM
8KB Data Flash
16KB Data RAM
16KB Boot Flash
Up to two 6-channel PWM modules
Four 4-channel, 12-bit ADCs
Temperature Sensor
Up to two Quadrature Decoders
FlexCAN module
Two Serial Communication Interfaces (SCIs)
Up to two Serial Peripheral Interface (SPIs)
Up to four general purpose Quad Timers
Computer Operating Properly (COP)/Watchdog
JTAG/Enhanced On-Chip Emulation (OnCETM) for
unobtrusive, real-time debugging
Up to 49 GPIO lines
128-pin LQFP Package
56F8355 Technical Data, Rev. 5.0
4
Freescale Semiconductor
Preliminary
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8355/56F8155 Features . . . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . . . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . . 33
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2. External Clock Operation . . . . . . . . . . . . . . . . 33
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 35
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . . . 37
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . . . 41
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . . . 43
4.7. Peripheral Memory Mapped Registers . . . . . . 44
4.8. Factory Programmed Memory . . . . . . . . . . . . 70
Part 5: Interrupt Controller (ITCN) . . . . . . . . 71
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3. Functional Description . . . . . . . . . . . . . . . . . . 71
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 73
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . . 73
5.6. Register Descriptions . . . . . . . . . . . . . . . . . . . 74
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Part 6: System Integration Module (SIM) . 101
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . . 102
6.4. Operating Mode Register . . . . . . . . . . . . . . . 102
6.5. Register Descriptions . . . . . . . . . . . . . . . . . . 103
6.6. Clock Generation Overview . . . . . . . . . . . . . 116
6.7. Power Down Modes Overview . . . . . . . . . . . 117
6.8. Stop and Wait Mode Disable Function . . . . . 117
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Part 7: Security Features . . . . . . . . . . . . . . 118
7.1. Operation with Security Enabled . . . . . . . . . 118
7.2. Flash Access Blocking Mechanisms . . . . . . . 119
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 121
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . 122
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 122
Part 9: Joint Test Action Group (JTAG) . . 127
9.1. 56F8355 Information . . . . . . . . . . . . . . . . . . 127
Part 10: Specifications . . . . . . . . . . . . . . . . 128
10.1. General Characteristics . . . . . . . . . . . . . . . 128
10.2. DC Electrical Characteristics . . . . . . . . . . . 132
10.3. AC Electrical Characteristics . . . . . . . . . . . 136
10.4. Flash Memory Characteristics . . . . . . . . . . 136
10.5. External Clock Operation Timing . . . . . . . . 137
10.6. Phase Locked Loop Timing . . . . . . . . . . . . 137
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . . 138
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . . 138
10.9. Serial Peripheral Interface (SPI) Timing . . . 140
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . . 143
10.11. Quadrature Decoder Timing . . . . . . . . . . . 144
10.12. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . . 145
10.13. Controller Area Network (CAN) Timing . . 145
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 146
10.15. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . . 147
10.16. Equivalent Circuit for ADC Inputs . . . . . . . 150
10.17. Power Consumption . . . . . . . . . . . . . . . . . 150
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 152
11.1. 56F8355 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 152
11.2. 56F8155 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 155
Part 12: Design Considerations . . . . . . . . . 159
12.1. Thermal Design Considerations . . . . . . . . . 159
12.2. Electrical Design Considerations . . . . . . . . 160
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . . 161
Part 13: Ordering Information . . . . . . . . . . 162
56F8355/56F8155 Features
56F8355 Technical Data, Rev. 5.0
Freescale Semiconductor
5
Preliminary
Part 1 Overview
1.1 56F8355/56F8155 Features
1.1.1
Hybrid Controller Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8355 and 56F8155 devices.
Table 1-1 Device Differences
Feature
56F8355
56F8155
Guaranteed Speed
60MHz/60 MIPS
40MHz/40MIPS
Program RAM
4KB
Not Available
Data Flash
8KB
Not Available
PWM
2 x 6
1 x 6
CAN
1
Not Available
Quad Timer
4
2
Quadrature Decoder
2 x 4
1 x 4
Temperature Sensor
1
Not Available
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