Document Outline

• Revision History
• List of Chapters
• Table of Contents
• Chapter 1 General Description
  • 1.1 Introduction
  • 1.2 Features
    • 1.2.1 Standard Features of the MC68HC908GT16/MC68HC908GT8
    • 1.2.2 Features of the CPU08
  • 1.3 MCU Block Diagram
  • 1.4 Pin Assignments
  • 1.5 Pin Functions
    • 1.5.1 Power Supply Pins (VDD and VSS)
    • 1.5.2 Oscillator Pins (PTE4/OSC1 and PTE3/OSC2)
    • 1.5.3 External Reset Pin (RST)
    • 1.5.4 External Interrupt Pin (IRQ)
    • 1.5.5 ADC and ICG Power Supply Pins (VDDA and VSSA)
    • 1.5.6 ADC Reference Pins (VREFH and VREFL)
    • 1.5.7 Port A Input/Output (I/O) Pins (PTA7/KBD7-PTA0/KBD0)
    • 1.5.8 Port B I/O Pins (PTB7/AD7-PTB0/AD0)
    • 1.5.9 Port C I/O Pins (PTC6-PTC0)
    • 1.5.10 Port D I/O Pins (PTD7/T2CH1-PTD0/SS)
    • 1.5.11 Port E I/O Pins (PTE4-PTE2, PTE1/RxD, and PTE0/TxD)
• Chapter 2 Memory
  • 2.1 Introduction
  • 2.2 Unimplemented Memory Locations
  • 2.3 Reserved Memory Locations
  • 2.4 Input/Output (I/O) Section
  • 2.5 Random-Access Memory (RAM)
  • 2.6 FLASH Memory
    • 2.6.1 Functional Description
    • 2.6.2 FLASH Control Register
    • 2.6.3 FLASH Page Erase Operation
    • 2.6.4 FLASH Mass Erase Operation
    • 2.6.5 FLASH Program/Read Operation
    • 2.6.6 FLASH Block Protection
    • 2.6.7 FLASH Block Protect Register
    • 2.6.8 ICG User Trim Registers (ICGTR5 and ICGTR3)
    • 2.6.9 Wait Mode
    • 2.6.10 Stop Mode
• Chapter 3 Analog-to-Digital Converter (ADC)
  • 3.1 Introduction
  • 3.2 Features
  • 3.3 Functional Description
    • 3.3.1 ADC Port I/O Pins
    • 3.3.2 ADC Port I/O Pins
    • 3.3.3 Voltage Conversion
    • 3.3.4 Conversion Time
    • 3.3.5 Conversion
    • 3.3.6 Accuracy and Precision
  • 3.4 Interrupts
  • 3.5 Low-Power Modes
    • 3.5.1 Wait Mode
    • 3.5.2 Stop Mode
  • 3.6 I/O Signals
    • 3.6.1 ADC Analog Power Pin (VDDA)
    • 3.6.2 ADC Analog Ground Pin (VSSA)
    • 3.6.3 ADC Voltage Reference High Pin (VREFH)
    • 3.6.4 ADC Voltage Reference Low Pin (VREFL)
    • 3.6.5 ADC Voltage In (VADIN)
  • 3.7 I/O Registers
    • 3.7.1 ADC Status and Control Register
    • 3.7.2 ADC Data Register
    • 3.7.3 ADC Clock Register
• Chapter 4 Configuration Register (CONFIG)
  • 4.1 Introduction
  • 4.2 Functional Description
• Chapter 5 Computer Operating Properly (COP) Module
  • 5.1 Introduction
  • 5.2 Functional Description
  • 5.3 I/O Signals
    • 5.3.1 COPCLK
    • 5.3.2 STOP Instruction
    • 5.3.3 COPCTL Write
    • 5.3.4 Power-On Reset
    • 5.3.5 Internal Reset
    • 5.3.6 Reset Vector Fetch
    • 5.3.7 COPD (COP Disable)
    • 5.3.8 COPRS (COP Rate Select)
  • 5.4 COP Control Register
  • 5.5 Interrupts
  • 5.6 Monitor Mode
  • 5.7 Low-Power Modes
    • 5.7.1 Wait Mode
    • 5.7.2 Stop Mode
  • 5.8 COP Module During Break Mode
• Chapter 6 Central Processor Unit (CPU)
  • 6.1 Introduction
  • 6.2 Features
  • 6.3 CPU Registers
    • 6.3.1 Accumulator
    • 6.3.2 Index Register
    • 6.3.3 Stack Pointer
    • 6.3.4 Program Counter
    • 6.3.5 Condition Code Register
  • 6.4 Arithmetic/Logic Unit (ALU)
  • 6.5 Low-Power Modes
    • 6.5.1 Wait Mode
    • 6.5.2 Stop Mode
  • 6.6 CPU During Break Interrupts
  • 6.7 Instruction Set Summary
  • 6.8 Opcode Map
• Chapter 7 Internal Clock Generator (ICG) Module)
  • 7.1 Introduction
  • 7.2 Features
  • 7.3 Functional Description
    • 7.3.1 Clock Enable Circuit
    • 7.3.2 Internal Clock Generator
      • 7.3.2.1 Digitally Controlled Oscillator
      • 7.3.2.2 Modulo N Divider
      • 7.3.2.3 Frequency Comparator
      • 7.3.2.4 Digital Loop Filter
    • 7.3.3 External Clock Generator
      • 7.3.3.1 External Oscillator Amplifier
      • 7.3.3.2 External Clock Input Path
    • 7.3.4 Clock Monitor Circuit
      • 7.3.4.1 Clock Monitor Reference Generator
      • 7.3.4.2 Internal Clock Activity Detector
      • 7.3.4.3 External Clock Activity Detector
    • 7.3.5 Clock Selection Circuit
      • 7.3.5.1 Clock Selection Switches
      • 7.3.5.2 Clock Switching Circuit
  • 7.4 Usage Notes
    • 7.4.1 Switching Clock Sources
    • 7.4.2 Enabling the Clock Monitor
    • 7.4.3 Using Clock Monitor Interrupts
    • 7.4.4 Quantization Error in DCO Output
      • 7.4.4.1 Digitally Controlled Oscillator
      • 7.4.4.2 Binary Weighted Divider
      • 7.4.4.3 Variable-Delay Ring Oscillator
      • 7.4.4.4 Ring Oscillator Fine-Adjust Circuit
    • 7.4.5 Switching Internal Clock Frequencies
    • 7.4.6 Nominal Frequency Settling Time
      • 7.4.6.1 Settling to Within 15 Percent
      • 7.4.6.2 Settling to Within 5 Percent
      • 7.4.6.3 Total Settling Time
    • 7.4.7 Trimming Frequency on the Internal Clock Generator
  • 7.5 Low-Power Modes
    • 7.5.1 Wait Mode
    • 7.5.2 Stop Mode
  • 7.6 CONFIG2 Options
    • 7.6.1 External Clock Enable (EXTCLKEN)
    • 7.6.2 External Crystal Enable (EXTXTALEN)
    • 7.6.3 Slow External Clock (EXTSLOW)
    • 7.6.4 Oscillator Enable In Stop (OSCENINSTOP)
  • 7.7 Input/Output (I/O) Registers
    • 7.7.1 ICG Control Register
    • 7.7.2 ICG Multiplier Register
    • 7.7.3 ICG Trim Register
    • 7.7.4 ICG DCO Divider Register
    • 7.7.5 ICG DCO Stage Register
• Chapter 8 External Interrupt (IRQ)
  • 8.1 Introduction
  • 8.2 Features
  • 8.3 Functional Description
  • 8.4 IRQ Pin
  • 8.5 IRQ Module During Break Interrupts
  • 8.6 IRQ Status and Control Register
• Chapter 9 Keyboard Interrupt Module (KBI)
  • 9.1 Introduction
  • 9.2 Features
  • 9.3 Functional Description
  • 9.4 Keyboard Initialization
  • 9.5 Low-Power Modes
    • 9.5.1 Wait Mode
    • 9.5.2 Stop Mode
  • 9.6 Keyboard Module During Break Interrupts
  • 9.7 I/O Registers
    • 9.7.1 Keyboard Status and Control Register
    • 9.7.2 Keyboard Interrupt Enable Register
• Chapter 10 Low-Voltage Inhibit (LVI)
  • 10.1 Introduction
  • 10.2 Features
  • 10.3 Functional Description
    • 10.3.1 Polled LVI Operation
    • 10.3.2 Forced Reset Operation
    • 10.3.3 Voltage Hysteresis Protection
    • 10.3.4 LVI Trip Selection
  • 10.4 LVI Status Register
  • 10.5 LVI Interrupts
  • 10.6 Low-Power Modes
    • 10.6.1 Wait Mode
    • 10.6.2 Stop Mode
• Chapter 11 Low-Power Modes (MODES)
  • 11.1 Introduction
    • 11.1.1 Wait Mode
    • 11.1.2 Stop Mode
  • 11.2 Analog-to-Digital Converter (ADC)
    • 11.2.1 Wait Mode
    • 11.2.2 Stop Mode
  • 11.3 Break Module (BRK)
    • 11.3.1 Wait Mode
    • 11.3.2 Stop Mode
  • 11.4 Central Processor Unit (CPU)
    • 11.4.1 Wait Mode
    • 11.4.2 Stop Mode
  • 11.5 Internal Clock Generator Module (ICG)
    • 11.5.1 Wait Mode
    • 11.5.2 Stop Mode
  • 11.6 Computer Operating Properly Module (COP)
    • 11.6.1 Wait Mode
    • 11.6.2 Stop Mode
  • 11.7 External Interrupt Module (IRQ)
    • 11.7.1 Wait Mode
    • 11.7.2 Stop Mode
  • 11.8 Keyboard Interrupt Module (KBI)
    • 11.8.1 Wait Mode
    • 11.8.2 Stop Mode
  • 11.9 Low-Voltage Inhibit Module (LVI)
    • 11.9.1 Wait Mode
    • 11.9.2 Stop Mode
  • 11.10 Enhanced Serial Communications Interface Module (SCI)
    • 11.10.1 Wait Mode
    • 11.10.2 Stop Mode
  • 11.11 Serial Peripheral Interface Module (SPI)
    • 11.11.1 Wait Mode
    • 11.11.2 Stop Mode
  • 11.12 Timer Interface Module (TIM1 and TIM2)
    • 11.12.1 Wait Mode
    • 11.12.2 Stop Mode
  • 11.13 Timebase Module (TBM)
    • 11.13.1 Wait Mode
    • 11.13.2 Stop Mode
  • 11.14 Exiting Wait Mode
  • 11.15 Exiting Stop Mode
• Chapter 12 Input/Output (I/O) Ports (PORTS)
  • 12.1 Introduction
  • 12.2 Port A
    • 12.2.1 Port A Data Register
    • 12.2.2 Data Direction Register A
    • 12.2.3 Port A Input Pullup Enable Register
  • 12.3 Port B
    • 12.3.1 Port B Data Register
    • 12.3.2 Data Direction Register B
  • 12.4 Port C
    • 12.4.1 Port C Data Register
    • 12.4.2 Data Direction Register C
    • 12.4.3 Port C Input Pullup Enable Register
  • 12.5 Port D
    • 12.5.1 Port D Data Register
    • 12.5.2 Data Direction Register D
    • 12.5.3 Port D Input Pullup Enable Register
  • 12.6 Port E
    • 12.6.1 Port E Data Register
    • 12.6.2 Data Direction Register E
• Chapter 13 Resets and Interrupts
  • 13.1 Introduction
  • 13.2 Resets
    • 13.2.1 Effects
    • 13.2.2 External Reset
    • 13.2.3 Internal Reset
      • 13.2.3.1 Power-On Reset (POR)
      • 13.2.3.2 Computer Operating Properly (COP) Reset
      • 13.2.3.3 Low-Voltage Inhibit Reset
      • 13.2.3.4 Illegal Opcode Reset
      • 13.2.3.5 Illegal Address Reset
    • 13.2.4 SIM Reset Status Register
  • 13.3 Interrupts
    • 13.3.1 Effects
    • 13.3.2 Sources
      • 13.3.2.1 Software Interrupt (SWI) Instruction
      • 13.3.2.2 Break Interrupt
      • 13.3.2.3 IRQ Pin
      • 13.3.2.4 Internal Clock Generator (ICG)
      • 13.3.2.5 Timer Interface Module 1 (TIM1)
      • 13.3.2.6 Timer Interface Module 2 (TIM2)
      • 13.3.2.7 Serial Peripheral Interface (SPI)
      • 13.3.2.8 Serial Communications Interface (SCI)
      • 13.3.2.9 KBD0-KBD7 Pins
      • 13.3.2.10 Analog-to-Digital Converter (ADC)
      • 13.3.2.11 Timebase Module (TBM)
    • 13.3.3 Interrupt Status Registers
      • 13.3.3.1 Interrupt Status Register 1
      • 13.3.3.2 Interrupt Status Register 2
      • 13.3.3.3 Interrupt Status Register 3
• Chapter 14 Enhanced Serial Communications Interface (ESCI) Module
  • 14.1 Introduction
  • 14.2 Features
  • 14.3 Pin Name Conventions
  • 14.4 Functional Description
    • 14.4.1 Data Format
    • 14.4.2 Transmitter
      • 14.4.2.1 Character Length
      • 14.4.2.2 Character Transmission
      • 14.4.2.3 Break Characters
      • 14.4.2.4 Idle Characters
      • 14.4.2.5 Inversion of Transmitted Output
      • 14.4.2.6 Transmitter Interrupts
    • 14.4.3 Receiver
      • 14.4.3.1 Character Length
      • 14.4.3.2 Character Reception
      • 14.4.3.3 Data Sampling
      • 14.4.3.4 Framing Errors
      • 14.4.3.5 Baud Rate Tolerance
      • 14.4.3.6 Receiver Wakeup
      • 14.4.3.7 Receiver Interrupts
      • 14.4.3.8 Error Interrupts
  • 14.5 Low-Power Modes
    • 14.5.1 Wait Mode
    • 14.5.2 Stop Mode
  • 14.6 ESCI During Break Module Interrupts
  • 14.7 I/O Signals
    • 14.7.1 PTE0/TxD (Transmit Data)
    • 14.7.2 PTE1/RxD (Receive Data)
  • 14.8 I/O Registers
    • 14.8.1 ESCI Control Register 1
    • 14.8.2 ESCI Control Register 2
    • 14.8.3 ESCI Control Register 3
    • 14.8.4 ESCI Status Register 1
    • 14.8.5 ESCI Status Register 2
    • 14.8.6 ESCI Data Register
    • 14.8.7 ESCI Baud Rate Register
    • 14.8.8 ESCI Prescaler Register
  • 14.9 ESCI Arbiter
    • 14.9.1 ESCI Arbiter Control Register
    • 14.9.2 ESCI Arbiter Data Register
    • 14.9.3 Bit Time Measurement
    • 14.9.4 Arbitration Mode
• Chapter 15 System Integration Module (SIM)
  • 15.1 Introduction
  • 15.2 SIM Bus Clock Control and Generation
    • 15.2.1 Bus Timing
    • 15.2.2 Clock Startup from POR or LVI Reset
    • 15.2.3 Clocks in Stop Mode and Wait Mode
  • 15.3 Reset and System Initialization
    • 15.3.1 External Pin Reset
    • 15.3.2 Active Resets from Internal Sources
      • 15.3.2.1 Power-On Reset
      • 15.3.2.2 Computer Operating Properly (COP) Reset
      • 15.3.2.3 Illegal Opcode Reset
      • 15.3.2.4 Illegal Address Reset
      • 15.3.2.5 Low-Voltage Inhibit (LVI) Reset
      • 15.3.2.6 Monitor Mode Entry Module Reset (MODRST)
  • 15.4 SIM Counter
    • 15.4.1 SIM Counter During Power-On Reset
    • 15.4.2 SIM Counter During Stop Mode Recovery
    • 15.4.3 SIM Counter and Reset States
  • 15.5 Exception Control
    • 15.5.1 Interrupts
      • 15.5.1.1 Hardware Interrupts
      • 15.5.1.2 SWI Instruction
      • 15.5.1.3 Interrupt Status Registers
    • 15.5.2 Reset
    • 15.5.3 Break Interrupts
    • 15.5.4 Status Flag Protection in Break Mode
  • 15.6 Low-Power Modes
    • 15.6.1 Wait Mode
    • 15.6.2 Stop Mode
  • 15.7 SIM Registers
    • 15.7.1 SIM Break Status Register
    • 15.7.2 SIM Reset Status Register
    • 15.7.3 SIM Break Flag Control Register
• Chapter 16 Serial Peripheral Interface (SPI) Module
  • 16.1 Introduction
  • 16.2 Features
  • 16.3 Functional Description
    • 16.3.1 Master Mode
    • 16.3.2 Slave Mode
  • 16.4 Transmission Formats
    • 16.4.1 Clock Phase and Polarity Controls
    • 16.4.2 Transmission Format When CPHA = 0
    • 16.4.3 Transmission Format When CPHA = 1
    • 16.4.4 Transmission Initiation Latency
  • 16.5 Queuing Transmission Data
  • 16.6 Error Conditions
    • 16.6.1 Overflow Error
    • 16.6.2 Mode Fault Error
  • 16.7 Interrupts
  • 16.8 Resetting the SPI
  • 16.9 Low-Power Modes
    • 16.9.1 Wait Mode
    • 16.9.2 Stop Mode
  • 16.10 SPI During Break Interrupts
  • 16.11 I/O Signals
    • 16.11.1 MISO (Master In/Slave Out)
    • 16.11.2 MOSI (Master Out/Slave In)
    • 16.11.3 SPSCK (Serial Clock)
    • 16.11.4 SS (Slave Select)
  • 16.12 I/O Registers
    • 16.12.1 SPI Control Register
    • 16.12.2 SPI Status and Control Register
    • 16.12.3 SPI Data Register
• Chapter 17 Timebase Module (TBM)
  • 17.1 Introduction
  • 17.2 Features
  • 17.3 Functional Description
  • 17.4 Timebase Register Description
  • 17.5 Interrupts
  • 17.6 Low-Power Modes
    • 17.6.1 Wait Mode
    • 17.6.2 Stop Mode
• Chapter 18 Timer Interface Module (TIM)
  • 18.1 Introduction
  • 18.2 Features
  • 18.3 Pin Name Conventions
  • 18.4 Functional Description
    • 18.4.1 TIM Counter Prescaler
    • 18.4.2 Input Capture
    • 18.4.3 Output Compare
      • 18.4.3.1 Unbuffered Output Compare
      • 18.4.3.2 Buffered Output Compare
    • 18.4.4 Pulse Width Modulation (PWM)
      • 18.4.4.1 Unbuffered PWM Signal Generation
      • 18.4.4.2 Buffered PWM Signal Generation
      • 18.4.4.3 PWM Initialization
  • 18.5 Interrupts
  • 18.6 Low-Power Modes
    • 18.6.1 Wait Mode
    • 18.6.2 Stop Mode
  • 18.7 TIM During Break Interrupts
  • 18.8 I/O Signals
  • 18.9 I/O Registers
    • 18.9.1 TIM Status and Control Register
    • 18.9.2 TIM Counter Registers
    • 18.9.3 TIM Counter Modulo Registers
    • 18.9.4 TIM Channel Status and Control Registers
    • 18.9.5 TIM Channel Registers
• Chapter 19 Development Support
  • 19.1 Introduction
  • 19.2 Break Module (BRK)
    • 19.2.1 Functional Description
      • 19.2.1.1 Flag Protection During Break Interrupts
      • 19.2.1.2 TIM1 and TIM2 During Break Interrupts
      • 19.2.1.3 COP During Break Interrupts
    • 19.2.2 Break Module Registers
      • 19.2.2.1 Break Status and Control Register
      • 19.2.2.2 Break Address Registers
      • 19.2.2.3 SIM Break Status Register
      • 19.2.2.4 Break Flag Control Register
  • 19.3 Monitor Module (MON)
    • 19.3.1 Functional Description
      • 19.3.1.1 Normal Monitor Mode
      • 19.3.1.2 Forced Monitor Mode
      • 19.3.1.3 Monitor Vectors
      • 19.3.1.4 Data Format
      • 19.3.1.5 Break Signal
      • 19.3.1.6 Baud Rate
      • 19.3.1.7 Commands
    • 19.3.2 Security
• Chapter 20 Electrical Specifications
  • 20.1 Introduction
  • 20.2 Absolute Maximum Ratings
  • 20.3 Functional Operating Range
  • 20.4 Thermal Characteristics
  • 20.5 5.0-V DC Electrical Characteristics
  • 20.6 3.0-V DC Electrical Characteristics
  • 20.7 Supply Current Characteristics
  • 20.8 5-V Control Timing
  • 20.9 3-V Control Timing
  • 20.10 Internal Oscillator Characteristics
  • 20.11 External Oscillator Characteristics
  • 20.12 Trimmed Accuracy of the Internal Clock Generator
    • 20.12.1 2.7-Volt to 3.3-Volt Trimmed Internal Clock Generator Characteristics
    • 20.12.2 4.5-Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics
  • 20.13 Output High-Voltage Characteristics
  • 20.14 Output Low-Voltage Characteristics
  • 20.15 Typical Supply Currents
  • 20.16 ADC Characteristics
  • 20.17 5.0-V SPI Characteristics
  • 20.18 3.0-V SPI Characteristics
  • 20.19 Timer Interface Module Characteristics
  • 20.20 Memory Characteristics
• Chapter 21 Ordering Information and Mechanical Specifications
  • 21.1 Introduction
  • 21.2 MC Order Numbers
  • 21.3 42-Pin Shrink Dual in-Line Package (SDIP)
  • 21.4 44-Pin Plastic Quad Flat Pack (QFP)