Document Outline

• Revision History
• List of Chapters
• Table of Contents
• Chapter 1 General Description
  • 1.1 Introduction
  • 1.2 Features
  • 1.3 MCU Block Diagram
  • 1.4 Pin Assignments
  • 1.5 Pin Functions
  • 1.6 Pin Function Priority
• Chapter 2 Memory
  • 2.1 Introduction
  • 2.2 Unimplemented Memory Locations
  • 2.3 Reserved Memory Locations
  • 2.4 Direct Page Registers
  • 2.5 Random-Access Memory (RAM)
  • 2.6 FLASH Memory (FLASH)
    • 2.6.1 FLASH Control Register
    • 2.6.2 FLASH Page Erase Operation
    • 2.6.3 FLASH Mass Erase Operation
    • 2.6.4 FLASH Program Operation
    • 2.6.5 FLASH Protection
    • 2.6.6 FLASH Block Protect Register
    • 2.6.7 EEPROM Memory Emulation Using FLASH Memory
• Chapter 3 Analog-to-Digital Converter (ADC10) Module
  • 3.1 Introduction
  • 3.2 Features
  • 3.3 Functional Description
    • 3.3.1 Clock Select and Divide Circuit
    • 3.3.2 Input Select and Pin Control
    • 3.3.3 Conversion Control
      • 3.3.3.1 Initiating Conversions
      • 3.3.3.2 Completing Conversions
      • 3.3.3.3 Aborting Conversions
      • 3.3.3.4 Total Conversion Time
    • 3.3.4 Sources of Error
      • 3.3.4.1 Sampling Error
      • 3.3.4.2 Pin Leakage Error
      • 3.3.4.3 Noise-Induced Errors
      • 3.3.4.4 Code Width and Quantization Error
      • 3.3.4.5 Linearity Errors
      • 3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes
  • 3.4 Interrupts
  • 3.5 Low-Power Modes
    • 3.5.1 Wait Mode
    • 3.5.2 Stop Mode
  • 3.6 ADC10 During Break Interrupts
  • 3.7 I/O Signals
    • 3.7.1 ADC10 Analog Power Pin (VDDA)
    • 3.7.2 ADC10 Analog Ground Pin (VSSA)
    • 3.7.3 ADC10 Voltage Reference High Pin (VREFH)
    • 3.7.4 ADC10 Voltage Reference Low Pin (VREFL)
    • 3.7.5 ADC10 Channel Pins (ADn)
  • 3.8 Registers
    • 3.8.1 ADC10 Status and Control Register
    • 3.8.2 ADC10 Result High Register (ADRH)
    • 3.8.3 ADC10 Result Low Register (ADRL)
    • 3.8.4 ADC10 Clock Register (ADCLK)
• Chapter 4 Auto Wakeup Module (AWU)
  • 4.1 Introduction
  • 4.2 Features
  • 4.3 Functional Description
  • 4.4 Interrupts
  • 4.5 Low-Power Modes
    • 4.5.1 Wait Mode
    • 4.5.2 Stop Mode
  • 4.6 Registers
    • 4.6.1 Port A I/O Register
    • 4.6.2 Keyboard Status and Control Register
    • 4.6.3 Keyboard Interrupt Enable Register
    • 4.6.4 Configuration Register 2
    • 4.6.5 Configuration Register 1
• Chapter 5 Configuration Register (CONFIG)
  • 5.1 Introduction
  • 5.2 Functional Description
• Chapter 6 Computer Operating Properly (COP)
  • 6.1 Introduction
  • 6.2 Functional Description
  • 6.3 I/O Signals
    • 6.3.1 BUSCLKX4
    • 6.3.2 STOP Instruction
    • 6.3.3 COPCTL Write
    • 6.3.4 Power-On Reset
    • 6.3.5 Internal Reset
    • 6.3.6 COPD (COP Disable)
    • 6.3.7 COPRS (COP Rate Select)
  • 6.4 Interrupts
  • 6.5 Monitor Mode
  • 6.6 Low-Power Modes
    • 6.6.1 Wait Mode
    • 6.6.2 Stop Mode
  • 6.7 COP Module During Break Mode
  • 6.8 Register
• Chapter 7 Central Processor Unit (CPU)
  • 7.1 Introduction
  • 7.2 Features
  • 7.3 CPU Registers
    • 7.3.1 Accumulator
    • 7.3.2 Index Register
    • 7.3.3 Stack Pointer
    • 7.3.4 Program Counter
    • 7.3.5 Condition Code Register
  • 7.4 Arithmetic/Logic Unit (ALU)
  • 7.5 Low-Power Modes
    • 7.5.1 Wait Mode
    • 7.5.2 Stop Mode
  • 7.6 CPU During Break Interrupts
  • 7.7 Instruction Set Summary
  • 7.8 Opcode Map
• Chapter 8 External Interrupt (IRQ)
  • 8.1 Introduction
  • 8.2 Features
  • 8.3 Functional Description
    • 8.3.1 MODE = 1
    • 8.3.2 MODE = 0
  • 8.4 Interrupts
  • 8.5 Low-Power Modes
    • 8.5.1 Wait Mode
    • 8.5.2 Stop Mode
  • 8.6 IRQ Module During Break Interrupts
  • 8.7 I/O Signals
    • 8.7.1 IRQ Input Pins (IRQ)
  • 8.8 Registers
• Chapter 9 Keyboard Interrupt Module (KBI)
  • 9.1 Introduction
  • 9.2 Features
  • 9.3 Functional Description
    • 9.3.1 Keyboard Operation
      • 9.3.1.1 MODEK = 1
      • 9.3.1.2 MODEK = 0
    • 9.3.2 Keyboard Initialization
  • 9.4 Interrupts
  • 9.5 Low-Power Modes
    • 9.5.1 Wait Mode
    • 9.5.2 Stop Mode
  • 9.6 KBI During Break Interrupts
  • 9.7 I/O Signals
    • 9.7.1 KBI Input Pins (KBIx:KBI0)
  • 9.8 Registers
    • 9.8.1 Keyboard Status and Control Register (KBSCR)
    • 9.8.2 Keyboard Interrupt Enable Register (KBIER)
    • 9.8.3 Keyboard Interrupt Polarity Register (KBIPR)
• Chapter 10 Low-Voltage Inhibit (LVI)
  • 10.1 Introduction
  • 10.2 Features
  • 10.3 Functional Description
    • 10.3.1 Polled LVI Operation
    • 10.3.2 Forced Reset Operation
    • 10.3.3 LVI Hysteresis
    • 10.3.4 LVI Trip Selection
  • 10.4 LVI Interrupts
  • 10.5 Low-Power Modes
    • 10.5.1 Wait Mode
    • 10.5.2 Stop Mode
  • 10.6 Registers
• Chapter 11 Oscillator (OSC) Module
  • 11.1 Introduction
  • 11.2 Features
  • 11.3 Functional Description
    • 11.3.1 Internal Signal Definitions
      • 11.3.1.1 Oscillator Enable Signal (SIMOSCEN)
      • 11.3.1.2 XTAL Oscillator Clock (XTALCLK)
      • 11.3.1.3 RC Oscillator Clock (RCCLK)
      • 11.3.1.4 Internal Oscillator Clock (INTCLK)
      • 11.3.1.5 Bus Clock Times 4 (BUSCLKX4)
      • 11.3.1.6 Bus Clock Times 2 (BUSCLKX2)
    • 11.3.2 Internal Oscillator
      • 11.3.2.1 Internal Oscillator Trimming
      • 11.3.2.2 Internal to External Clock Switching
      • 11.3.2.3 External to Internal Clock Switching
    • 11.3.3 External Oscillator
    • 11.3.4 XTAL Oscillator
    • 11.3.5 RC Oscillator
  • 11.4 Interrupts
  • 11.5 Low-Power Modes
    • 11.5.1 Wait Mode
    • 11.5.2 Stop Mode
  • 11.6 OSC During Break Interrupts
  • 11.7 I/O Signals
    • 11.7.1 Oscillator Input Pin (OSC1)
    • 11.7.2 Oscillator Output Pin (OSC2)
  • 11.8 Registers
    • 11.8.1 Oscillator Status and Control Register
    • 11.8.2 Oscillator Trim Register (OSCTRIM)
• Chapter 12 Input/Output Ports (PORTS)
  • 12.1 Introduction
  • 12.2 Port A
    • 12.2.1 Port A Data Register
    • 12.2.2 Data Direction Register A
    • 12.2.3 Port A Input Pullup Enable Register
    • 12.2.4 Port A Summary Table
  • 12.3 Port B
    • 12.3.1 Port B Data Register
    • 12.3.2 Data Direction Register B
    • 12.3.3 Port B Input Pullup Enable Register
    • 12.3.4 Port B Summary Table
• Chapter 13 System Integration Module (SIM)
  • 13.1 Introduction
  • 13.2 RST and IRQ Pins Initialization
  • 13.3 SIM Bus Clock Control and Generation
    • 13.3.1 Bus Timing
    • 13.3.2 Clock Start-Up from POR
    • 13.3.3 Clocks in Stop Mode and Wait Mode
  • 13.4 Reset and System Initialization
    • 13.4.1 External Pin Reset
    • 13.4.2 Active Resets from Internal Sources
      • 13.4.2.1 Power-On Reset
      • 13.4.2.2 Computer Operating Properly (COP) Reset
      • 13.4.2.3 Illegal Opcode Reset
      • 13.4.2.4 Illegal Address Reset
      • 13.4.2.5 Low-Voltage Inhibit (LVI) Reset
  • 13.5 SIM Counter
    • 13.5.1 SIM Counter During Power-On Reset
    • 13.5.2 SIM Counter During Stop Mode Recovery
    • 13.5.3 SIM Counter and Reset States
  • 13.6 Exception Control
    • 13.6.1 Interrupts
      • 13.6.1.1 Hardware Interrupts
      • 13.6.1.2 SWI Instruction
    • 13.6.2 Interrupt Status Registers
      • 13.6.2.1 Interrupt Status Register 1
      • 13.6.2.2 Interrupt Status Register 2
      • 13.6.2.3 Interrupt Status Register 3
    • 13.6.3 Reset
    • 13.6.4 Break Interrupts
    • 13.6.5 Status Flag Protection in Break Mode
  • 13.7 Low-Power Modes
    • 13.7.1 Wait Mode
    • 13.7.2 Stop Mode
  • 13.8 SIM Registers
    • 13.8.1 SIM Reset Status Register
    • 13.8.2 Break Flag Control Register
• Chapter 14 Timer Interface Module (TIM)
  • 14.1 Introduction
  • 14.2 Features
  • 14.3 Functional Description
    • 14.3.1 TIM Counter Prescaler
    • 14.3.2 Input Capture
    • 14.3.3 Output Compare
      • 14.3.3.1 Unbuffered Output Compare
      • 14.3.3.2 Buffered Output Compare
    • 14.3.4 Pulse Width Modulation (PWM)
      • 14.3.4.1 Unbuffered PWM Signal Generation
      • 14.3.4.2 Buffered PWM Signal Generation
      • 14.3.4.3 PWM Initialization
  • 14.4 Interrupts
  • 14.5 Low-Power Modes
    • 14.5.1 Wait Mode
    • 14.5.2 Stop Mode
  • 14.6 TIM During Break Interrupts
  • 14.7 I/O Signals
    • 14.7.1 TIM Channel I/O Pins (TCH1:TCH0)
    • 14.7.2 TIM Clock Pin (TCLK)
  • 14.8 Registers
    • 14.8.1 TIM Status and Control Register
    • 14.8.2 TIM Counter Registers
    • 14.8.3 TIM Counter Modulo Registers
    • 14.8.4 TIM Channel Status and Control Registers
    • 14.8.5 TIM Channel Registers
• Chapter 15 Development Support
  • 15.1 Introduction
  • 15.2 Break Module (BRK)
    • 15.2.1 Functional Description
      • 15.2.1.1 Flag Protection During Break Interrupts
      • 15.2.1.2 TIM During Break Interrupts
      • 15.2.1.3 COP During Break Interrupts
    • 15.2.2 Break Module Registers
      • 15.2.2.1 Break Status and Control Register
      • 15.2.2.2 Break Address Registers
      • 15.2.2.3 Break Auxiliary Register
      • 15.2.2.4 Break Status Register
      • 15.2.2.5 Break Flag Control Register
    • 15.2.3 Low-Power Modes
  • 15.3 Monitor Module (MON)
    • 15.3.1 Functional Description
      • 15.3.1.1 Normal Monitor Mode
      • 15.3.1.2 Forced Monitor Mode
      • 15.3.1.3 Monitor Vectors
      • 15.3.1.4 Data Format
      • 15.3.1.5 Break Signal
      • 15.3.1.6 Baud Rate
      • 15.3.1.7 Commands
    • 15.3.2 Security
• Chapter 16 Electrical Specifications
  • 16.1 Introduction
  • 16.2 Absolute Maximum Ratings
  • 16.3 Functional Operating Range
  • 16.4 Thermal Characteristics
  • 16.5 5-V DC Electrical Characteristics
  • 16.6 Typical 5-V Output Drive Characteristics
  • 16.7 5-V Control Timing
  • 16.8 3-V DC Electrical Characteristics
  • 16.9 Typical 3-V Output Drive Characteristics
  • 16.10 3-V Control Timing
  • 16.11 Oscillator Characteristics
  • 16.12 Supply Current Characteristics
  • 16.13 ADC10 Characteristics
  • 16.14 Timer Interface Module Characteristics
  • 16.15 Memory Characteristics
• Chapter 17 Ordering Information and Mechanical Specifications
  • 17.1 Introduction
  • 17.2 MC Order Numbers
  • 17.3 Package Dimensions
• Appendix A 908QTA/QYxA Conversion Guidelines
  • A.1 Introduction
  • A.2 Benefits of the Enhanced QYxA
    • A.2.1 New Analog-to-Digital Converter Module (ADC)
      • A.2.1.1 Registers Affected
    • A.2.2 Enhanced Oscillator Module (OSC)
      • A.2.2.1 Registers Affected
    • A.2.3 Improved Auto Wakeup Module (AWU)
      • A.2.3.1 Registers Affected
    • A.2.4 New Power-on Reset Module (POR)
    • A.2.5 Keyboard Interface Module (KBI) Functionality
      • A.2.5.1 Registers Affected
    • A.2.6 On-Chip Routine Enhancements
  • A.3 Conversion Considerations
  • A.4 Code Changes Checklist
  • A.5 Development Tools
  • A.6 Differences in Packaging