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HCS08
Microcontrollers
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MC9S08QG8
MC9S08QG4
Data Sheet
MC9S08QG8
Rev. 1.01
10/2005
8-Bit HCS08 Central Processor Unit (CPU)
20-MHz HCS08 CPU (central processor unit)
HC08 instruction set with added BGND instruction
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
Debug module containing two comparators and nine
trigger modes. Eight deep FIFO for storing
change-of-flow addresses and event-only data
Debug module supports both tag and force
breakpoints
Support for up to 32 interrupt/reset sources
Memory Options
FLASH read/program/erase over full operating
voltage and temperature
MC9S08QG8 -- 8 Kbytes FLASH, 512 bytes RAM
MC9S08QG4 -- 4 Kbytes FLASH, 256 bytes RAM
Power-Saving Modes
Wait plus three stops
Clock Source Options
ICS -- Internal clock source module containing a
frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation
over temperature and voltage; supports bus
frequencies from 1 MHz to 10 MHz
XOSC -- Low-power oscillator module with
software selectable crystal or ceramic resonator
range, 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz,
and supports external clock source input up to
20 MHz
System Protection
Watchdog computer operating properly (COP) reset
with option to run from dedicated 1-kHz internal
clock source or bus clock
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
Illegal address detection with reset
FLASH block protect
Peripherals
ADC -- 8-channel, 10-bit analog-to-digital
converter with automatic compare function,
asynchronous clock source, temperature sensor, and
internal bandgap reference channel; ADC is
hardware triggerable using the RTI counter
ACMP -- Analog comparator module with option
to compare to internal reference; output can be
optionally routed to TPM module
SCI -- Serial communications interface module
with option for 13-bit break capabilities
SPI -- Serial peripheral interface module
IIC -- Inter-integrated circuit bus module
TPM-- 2-channel timer/pulse-width modulator;
each channel can be used for input capture, output
compare, buffered edge-aligned PWM, or buffered
center-aligned PWM
MTIM -- 8-bit modulo timer module with 8-bit
prescaler
KBI -- 8-pin keyboard interrupt module with
software selectable polarity on edge or edge/level
modes
Input/Output
12 general-purpose input/output (I/O) pins, one
input-only pin and one output-only pin; outputs
10 mA each, 60 mA max for package
Software selectable pullups on ports when used as
input
Software selectable slew rate control and drive
strength on ports when used as output
Internal pullup on RESET and IRQ pin to reduce
customer system cost
Development Support
Single-wire background debug interface
On-chip, in-circuit emulation (ICE) with real-time
bus capture
Package Options
16-pin plastic dual in-line package (PDIP) --
MC9S08QG8 only
16-pin quad flat no lead (QFN) package
16-pin thin shrink small outline package (TSSOP)
8-pin dual flat no lead (DFN) package
8-pin PDIP -- MC9S08QG4 only
8-pin narrow body small outline integrated circuit
(SOIC) package
MC9S08QG8/4 Features
MC9S08QG8 Data Sheet
Covers MC9S08QG8
MC9S08QG4
MC9S08QG8
Rev. 1.01
10/2005
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc., 2005. All rights reserved.
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Freescale Semiconductor, Inc., 2005. All rights reserved.
This product incorporates SuperFlash
Technology licensed from SST.
Revision
Number
Revision
Date
Description of Changes
1.01
10/07/2005
Initial public release
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
7
List of Chapters
Chapter 1
Device Overview ...................................................................... 19
Chapter 2
External Signal Description .................................................... 23
Chapter 3
Modes of Operation ................................................................. 31
Chapter 4
Memory Map and Register Definition .................................... 37
Chapter 5
Resets, Interrupts, and General System Control.................. 57
Chapter 6
Parallel Input/Output Control.................................................. 75
Chapter 7
Central Processor Unit (S08CPUV2) ...................................... 85
Chapter 8
Analog Comparator (S08ACMPV2) ...................................... 105
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)........................ 113
Chapter 10
Internal Clock Source (S08ICSV1)........................................ 141
Chapter 11
Inter-Integrated Circuit (S08IICV1) ....................................... 155
Chapter 12
Keyboard Interrupt (S08KBIV2) ............................................ 173
Chapter 13
Modulo Timer (S08MTIMV1).................................................. 181
Chapter 14
Serial Communications Interface (S08SCIV3)..................... 191
Chapter 15
Serial Peripheral Interface (S08SPIV3) ................................ 211
Chapter 16
Timer/Pulse-Width Modulator (S08TPMV2) ......................... 227
Chapter 17
Development Support ........................................................... 243
Appendix A
Electrical Characteristics...................................................... 257
Appendix B
Ordering Information and Mechanical Drawings................ 281
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
9
Contents
Section Number
Title
Page
Chapter 1
Device Overview
1.1
Introduction .....................................................................................................................................19
1.1.1
Devices in the MC9S08QG8/4 Series ...............................................................................19
1.1.2
MCU Block Diagram ........................................................................................................20
Chapter 2
External Signal Description
2.1
Device Pin Assignment ...................................................................................................................23
2.2
Recommended System Connections ...............................................................................................25
2.2.1
Power ................................................................................................................................25
2.2.2
Oscillator (XOSC) ............................................................................................................26
2.2.3
Reset (Input Only) .............................................................................................................26
2.2.4
Background / Mode Select (BKGD/MS) ..........................................................................27
2.2.5
General-Purpose I/O and Peripheral Ports ........................................................................27
Chapter 3
Modes of Operation
3.1
Introduction .....................................................................................................................................31
3.2
Features ...........................................................................................................................................31
3.3
Run Mode ........................................................................................................................................31
3.4
Active Background Mode ................................................................................................................31
3.5
Wait Mode .......................................................................................................................................32
3.6
Stop Modes ......................................................................................................................................33
3.6.1
Stop3 Mode .......................................................................................................................33
3.6.2
Stop2 Mode .......................................................................................................................34
3.6.3
Stop1 Mode .......................................................................................................................35
3.6.4
On-Chip Peripheral Modules in Stop Modes ....................................................................35
Chapter 4
Memory Map and Register Definition
4.1
MC9S08QG8/4 Memory Map ........................................................................................................37
4.2
Reset and Interrupt Vector Assignments .........................................................................................38
4.3
Register Addresses and Bit Assignments ........................................................................................39
4.4
RAM ................................................................................................................................................43
4.5
FLASH ............................................................................................................................................43
4.5.1
Features .............................................................................................................................44
4.5.2
Program and Erase Times .................................................................................................44
4.5.3
Program and Erase Command Execution .........................................................................45
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Section Number
Title
Page
4.5.4
Burst Program Execution ..................................................................................................46
4.5.5
Access Errors ....................................................................................................................48
4.5.6
FLASH Block Protection ..................................................................................................48
4.5.7
Vector Redirection ............................................................................................................49
4.6
Security ............................................................................................................................................49
4.7
FLASH Registers and Control Bits .................................................................................................51
4.7.1
FLASH Clock Divider Register (FCDIV) ........................................................................51
4.7.2
FLASH Options Register (FOPT and NVOPT) ................................................................52
4.7.3
FLASH Configuration Register (FCNFG) ........................................................................53
4.7.4
FLASH Protection Register (FPROT and NVPROT) .......................................................53
4.7.5
FLASH Status Register (FSTAT) ......................................................................................54
4.7.6
FLASH Command Register (FCMD) ...............................................................................55
Chapter 5
Resets, Interrupts, and General System Control
5.1
Introduction .....................................................................................................................................57
5.2
Features ...........................................................................................................................................57
5.3
MCU Reset ......................................................................................................................................57
5.4
Computer Operating Properly (COP) Watchdog .............................................................................58
5.5
Interrupts .........................................................................................................................................59
5.5.1
Interrupt Stack Frame .......................................................................................................60
5.5.2
External Interrupt Request Pin (IRQ) ...............................................................................60
5.5.3
Interrupt Vectors, Sources, and Local Masks ....................................................................61
5.6
Low-Voltage Detect (LVD) System ................................................................................................63
5.6.1
Power-On Reset Operation ...............................................................................................63
5.6.2
LVD Reset Operation ........................................................................................................63
5.6.3
LVD Interrupt Operation ...................................................................................................63
5.6.4
Low-Voltage Warning (LVW) ...........................................................................................63
5.7
Real-Time Interrupt (RTI) ...............................................................................................................63
5.8
Reset, Interrupt, and System Control Registers and Control Bits ...................................................64
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC) ............................................65
5.8.2
System Reset Status Register (SRS) .................................................................................66
5.8.3
System Background Debug Force Reset Register (SBDFR) ............................................67
5.8.4
System Options Register 1 (SOPT1) ................................................................................68
5.8.5
System Options Register 2 (SOPT2) ................................................................................69
5.8.6
System Device Identification Register (SDIDH, SDIDL) ................................................70
5.8.7
System Real-Time Interrupt Status and Control Register (SRTISC) ................................71
5.8.8
System Power Management Status and Control 1 Register (SPMSC1) ...........................72
5.8.9
System Power Management Status and Control 2 Register (SPMSC2) ...........................73
5.8.10 System Power Management Status and Control 3 Register (SPMSC3) ...........................74
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
11
Section Number
Title
Page
Chapter 6
Parallel Input/Output Control
6.1
Port Data and Data Direction ..........................................................................................................75
6.2
Pin Control -- Pullup, Slew Rate, and Drive Strength ...................................................................76
6.3
Pin Behavior in Stop Modes ............................................................................................................77
6.4
Parallel I/O Registers .......................................................................................................................77
6.4.1
Port A Registers ................................................................................................................77
6.4.2
Port A Control Registers ...................................................................................................78
6.4.3
Port B Registers ................................................................................................................81
6.4.4
Port B Control Registers ...................................................................................................82
Chapter 7
Central Processor Unit (S08CPUV2)
7.1
Introduction .....................................................................................................................................85
7.1.1
Features .............................................................................................................................85
7.2
Programmer's Model and CPU Registers .......................................................................................86
7.2.1
Accumulator (A) ...............................................................................................................86
7.2.2
Index Register (H:X) .........................................................................................................86
7.2.3
Stack Pointer (SP) .............................................................................................................87
7.2.4
Program Counter (PC) ......................................................................................................87
7.2.5
Condition Code Register (CCR) .......................................................................................87
7.3
Addressing Modes ...........................................................................................................................88
7.3.1
Inherent Addressing Mode (INH) .....................................................................................89
7.3.2
Relative Addressing Mode (REL) .....................................................................................89
7.3.3
Immediate Addressing Mode (IMM) ................................................................................89
7.3.4
Direct Addressing Mode (DIR) ........................................................................................89
7.3.5
Extended Addressing Mode (EXT) ..................................................................................89
7.3.6
Indexed Addressing Mode ................................................................................................89
7.4
Special Operations ...........................................................................................................................90
7.4.1
Reset Sequence .................................................................................................................91
7.4.2
Interrupt Sequence ............................................................................................................91
7.4.3
Wait Mode Operation ........................................................................................................92
7.4.4
Stop Mode Operation ........................................................................................................92
7.4.5
BGND Instruction .............................................................................................................92
7.5
HCS08 Instruction Set Summary ....................................................................................................93
Chapter 8
Analog Comparator (S08ACMPV2)
8.1
Introduction ...................................................................................................................................105
8.1.1
ACMP Configuration Information ..................................................................................105
8.1.2
ACMP/TPM Configuration Information .........................................................................105
8.1.3
Features ...........................................................................................................................107
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Section Number
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8.1.4
Modes of Operation ........................................................................................................107
8.1.5
Block Diagram ................................................................................................................107
8.2
External Signal Description ..........................................................................................................109
8.3
Register Definition ........................................................................................................................109
8.3.1
ACMP Status and Control Register (ACMPSC) .............................................................110
8.4
Functional Description ..................................................................................................................111
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)
9.1
Introduction ...................................................................................................................................113
9.1.1
Module Configurations ...................................................................................................115
9.1.2
Features ...........................................................................................................................117
9.1.3
Block Diagram ................................................................................................................117
9.2
External Signal Description ..........................................................................................................118
9.2.1
Analog Power (V
DDAD
) ..................................................................................................119
9.2.2
Analog Ground (V
SSAD
) .................................................................................................119
9.2.3
Voltage Reference High (V
REFH
) ...................................................................................119
9.2.4
Voltage Reference Low (V
REFL
) .....................................................................................119
9.2.5
Analog Channel Inputs (ADx) ........................................................................................119
9.3
Register Definition ........................................................................................................................119
9.3.1
Status and Control Register 1 (ADCSC1) ......................................................................119
9.3.2
Status and Control Register 2 (ADCSC2) ......................................................................121
9.3.3
Data Result High Register (ADCRH) .............................................................................122
9.3.4
Data Result Low Register (ADCRL) ..............................................................................122
9.3.5
Compare Value High Register (ADCCVH) ....................................................................123
9.3.6
Compare Value Low Register (ADCCVL) .....................................................................123
9.3.7
Configuration Register (ADCCFG) ................................................................................123
9.3.8
Pin Control 1 Register (APCTL1) ..................................................................................125
9.3.9
Pin Control 2 Register (APCTL2) ..................................................................................126
9.3.10 Pin Control 3 Register (APCTL3) ..................................................................................127
9.4
Functional Description ..................................................................................................................128
9.4.1
Clock Select and Divide Control ....................................................................................128
9.4.2
Input Select and Pin Control ...........................................................................................129
9.4.3
Hardware Trigger ............................................................................................................129
9.4.4
Conversion Control .........................................................................................................129
9.4.5
Automatic Compare Function .........................................................................................132
9.4.6
MCU Wait Mode Operation ............................................................................................132
9.4.7
MCU Stop3 Mode Operation ..........................................................................................132
9.4.8
MCU Stop1 and Stop2 Mode Operation .........................................................................133
9.5
Initialization Information ..............................................................................................................133
9.5.1
ADC Module Initialization Example .............................................................................134
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
13
Section Number
Title
Page
9.6
Application Information ................................................................................................................135
9.6.1
External Pins and Routing ..............................................................................................135
9.6.2
Sources of Error ..............................................................................................................137
Chapter 10
Internal Clock Source (S08ICSV1)
10.1 Introduction ...................................................................................................................................141
10.1.1 Module Configuration .....................................................................................................141
10.1.2 Features ...........................................................................................................................143
10.1.3 Modes of Operation ........................................................................................................143
10.1.4 Block Diagram ................................................................................................................144
10.2 External Signal Description ..........................................................................................................145
10.3 Register Definition ........................................................................................................................145
10.3.1 ICS Control Register 1 (ICSC1) .....................................................................................145
10.3.2 ICS Control Register 2 (ICSC2) .....................................................................................146
10.3.3 ICS Trim Register (ICSTRM) .........................................................................................147
10.3.4 ICS Status and Control (ICSSC) .....................................................................................147
10.4 Functional Description ..................................................................................................................148
10.4.1 Operational Modes ..........................................................................................................148
10.4.2 Mode Switching ..............................................................................................................150
10.4.3 Bus Frequency Divider ...................................................................................................150
10.4.4 Low Power Bit Usage .....................................................................................................151
10.4.5 Internal Reference Clock ................................................................................................151
10.4.6 Optional External Reference Clock ................................................................................151
10.4.7 Fixed Frequency Clock ...................................................................................................152
10.5 Module Initialization ....................................................................................................................152
10.5.1 ICS Module Initialization Sequence ...............................................................................152
Chapter 11
Inter-Integrated Circuit (S08IICV1)
11.1 Introduction ...................................................................................................................................155
11.1.1 Module Configuration .....................................................................................................155
11.1.2 Features ...........................................................................................................................159
11.1.3 Modes of Operation ........................................................................................................159
11.1.4 Block Diagram ................................................................................................................160
11.2 External Signal Description ..........................................................................................................160
11.2.1 SCL -- Serial Clock Line ...............................................................................................160
11.2.2 SDA -- Serial Data Line ................................................................................................160
11.3 Register Definition ........................................................................................................................160
11.3.1 IIC Address Register (IICA) ...........................................................................................161
11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................161
11.3.3 IIC Control Register (IICC) ............................................................................................164
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
14
Freescale Semiconductor
Section Number
Title
Page
11.3.4 IIC Status Register (IICS) ...............................................................................................165
11.3.5 IIC Data I/O Register (IICD) ..........................................................................................166
11.4 Functional Description ..................................................................................................................167
11.4.1 IIC Protocol .....................................................................................................................167
11.5 Resets ............................................................................................................................................170
11.6 Interrupts .......................................................................................................................................170
11.6.1 Byte Transfer Interrupt ....................................................................................................171
11.6.2 Address Detect Interrupt .................................................................................................171
11.6.3 Arbitration Lost Interrupt ................................................................................................171
Chapter 12
Keyboard Interrupt (S08KBIV2)
12.1 Introduction ...................................................................................................................................173
12.1.1 Features ...........................................................................................................................175
12.1.2 Modes of Operation ........................................................................................................175
12.1.3 Block Diagram ................................................................................................................175
12.2 External Signal Description ..........................................................................................................176
12.3 Register Definition ........................................................................................................................177
12.3.1 KBI Status and Control Register (KBISC) .....................................................................177
12.3.2 KBI Pin Enable Register (KBIPE) ..................................................................................177
12.3.3 KBI Edge Select Register (KBIES) ................................................................................178
12.4 Functional Description ..................................................................................................................178
12.4.1 Edge Only Sensitivity .....................................................................................................179
12.4.2 Edge and Level Sensitivity ..............................................................................................179
12.4.3 KBI Pullup/Pulldown Resistors ......................................................................................179
12.4.4 KBI Initialization ............................................................................................................179
Chapter 13
Modulo Timer (S08MTIMV1)
13.1 Introduction ...................................................................................................................................181
13.1.1 MTIM/TPM Configuration Information .........................................................................181
13.1.2 Features ...........................................................................................................................183
13.1.3 Modes of Operation ........................................................................................................183
13.1.4 Block Diagram ................................................................................................................184
13.2 External Signal Description ..........................................................................................................184
13.3 Register Definition ........................................................................................................................184
13.3.1 MTIM Status and Control Register (MTIMSC) .............................................................185
13.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................186
13.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................187
13.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................187
13.4 Functional Description ..................................................................................................................188
13.4.1 MTIM Operation Example .............................................................................................189
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
15
Section Number
Title
Page
Chapter 14
Serial Communications Interface (S08SCIV3)
14.1 Introduction ...................................................................................................................................191
14.1.1 Features ...........................................................................................................................194
14.1.2 Modes of Operation ........................................................................................................194
14.1.3 Block Diagram ................................................................................................................195
14.2 Register Definition ........................................................................................................................197
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBHL) ..............................................................197
14.2.2 SCI Control Register 1 (SCIC1) .....................................................................................198
14.2.3 SCI Control Register 2 (SCIC2) .....................................................................................199
14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................200
14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................202
14.2.6 SCI Control Register 3 (SCIC3) .....................................................................................202
14.2.7 SCI Data Register (SCID) ...............................................................................................203
14.3 Functional Description ..................................................................................................................204
14.3.1 Baud Rate Generation .....................................................................................................204
14.3.2 Transmitter Functional Description ................................................................................204
14.3.3 Receiver Functional Description .....................................................................................206
14.3.4 Interrupts and Status Flags ..............................................................................................207
14.4 Additional SCI Functions ..............................................................................................................208
14.4.1 8- and 9-Bit Data Modes .................................................................................................208
14.4.2 Stop Mode Operation ......................................................................................................209
14.4.3 Loop Mode ......................................................................................................................209
14.4.4 Single-Wire Operation ....................................................................................................209
Chapter 15
Serial Peripheral Interface (S08SPIV3)
15.1 Introduction ...................................................................................................................................211
15.1.1 Features ...........................................................................................................................213
15.1.2 Block Diagrams ..............................................................................................................213
15.1.3 SPI Baud Rate Generation ..............................................................................................215
15.2 External Signal Description ..........................................................................................................216
15.2.1 SPSCK -- SPI Serial Clock ............................................................................................216
15.2.2 MOSI -- Master Data Out, Slave Data In ......................................................................216
15.2.3 MISO -- Master Data In, Slave Data Out ......................................................................216
15.2.4 SS -- Slave Select ...........................................................................................................216
15.3 Register Definition ........................................................................................................................217
15.3.1 SPI Control Register 1 (SPIC1) ......................................................................................217
15.3.2 SPI Control Register 2 (SPIC2) ......................................................................................218
15.3.3 SPI Baud Rate Register (SPIBR) ....................................................................................219
15.3.4 SPI Status Register (SPIS) ..............................................................................................220
15.3.5 SPI Data Register (SPID) ................................................................................................221
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
16
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15.4 Functional Description ..................................................................................................................221
15.4.1 SPI Clock Formats ..........................................................................................................222
15.4.2 SPI Interrupts ..................................................................................................................224
15.4.3 Mode Fault Detection .....................................................................................................225
Chapter 16
Timer/Pulse-Width Modulator (S08TPMV2)
16.1 Introduction ...................................................................................................................................227
16.1.1 ACMP/TPM Configuration Information .........................................................................227
16.1.2 MTIM/TPM Configuration Information .........................................................................227
16.1.3 Block Diagram ................................................................................................................229
16.2 External Signal Description ..........................................................................................................230
16.2.1 External TPM Clock Sources ..........................................................................................230
16.2.2 TPMCHn -- TPM Channel n I/O Pins ...........................................................................230
16.3 Register Definition ........................................................................................................................230
16.3.1 Timer Status and Control Register (TPMSC) .................................................................231
16.3.2 Timer Counter Registers (TPMCNTH:TPMCNTL) .......................................................232
16.3.3 Timer Counter Modulo Registers (TPMMODH:TPMMODL) ......................................233
16.3.4 Timer Channel n Status and Control Register (TPMCnSC) ...........................................234
16.3.5 Timer Channel Value Registers (TPMCnVH:TPMCnVL) .............................................235
16.4 Functional Description ..................................................................................................................236
16.4.1 Counter ............................................................................................................................236
16.4.2 Channel Mode Selection .................................................................................................237
16.4.3 Center-Aligned PWM Mode ...........................................................................................239
16.5 TPM Interrupts ..............................................................................................................................240
16.5.1 Clearing Timer Interrupt Flags .......................................................................................240
16.5.2 Timer Overflow Interrupt Description ............................................................................240
16.5.3 Channel Event Interrupt Description ..............................................................................241
16.5.4 PWM End-of-Duty-Cycle Events ...................................................................................241
Chapter 17
Development Support
17.1 Introduction ...................................................................................................................................243
17.1.1 Module Configuration .....................................................................................................243
17.2 Features .........................................................................................................................................244
17.3 Background Debug Controller (BDC) ..........................................................................................244
17.3.1 BKGD Pin Description ...................................................................................................245
17.3.2 Communication Details ..................................................................................................245
17.3.3 BDC Commands .............................................................................................................249
17.3.4 BDC Hardware Breakpoint .............................................................................................251
17.4 Registers and Control Bits .............................................................................................................252
17.4.1 BDC Registers and Control Bits .....................................................................................252
17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................254
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
17
Section Number
Title
Page
Appendix A
Electrical Characteristics
A.1
Introduction ...................................................................................................................................257
A.2
Absolute Maximum Ratings ..........................................................................................................257
A.3
Thermal Characteristics .................................................................................................................258
A.4
ESD Protection and Latch-Up Immunity ......................................................................................260
A.5
DC Characteristics .........................................................................................................................261
A.6
Supply Current Characteristics ......................................................................................................264
A.7
External Oscillator (XOSC) and Internal Clock Source (ICS) Characteristics .............................266
A.8
AC Characteristics .........................................................................................................................269
A.8.1 Control Timing ...............................................................................................................269
A.8.2 TPM/MTIM Module Timing ..........................................................................................270
A.8.3 SPI Timing ......................................................................................................................271
A.9
Analog Comparator (ACMP) Electricals ......................................................................................274
A.10 ADC Characteristics ......................................................................................................................274
A.11 FLASH Specifications ...................................................................................................................277
A.12 EMC Performance .........................................................................................................................278
A.12.1 Radiated Emissions .........................................................................................................278
A.12.2 Conducted Transient Susceptibility ................................................................................278
Appendix B
Ordering Information and Mechanical Drawings
B.1
Ordering Information ....................................................................................................................281
B.1.1 Device Numbering Scheme ............................................................................................281
B.2
Mechanical Drawings ....................................................................................................................281
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
19
Chapter 1
Device Overview
1.1
Introduction
The MC9S08QG8 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller
units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of
modules, memory sizes, memory types, and package types. Refer to
Table 1-1
for features associated with
each device in this family.
1.1.1
Devices in the MC9S08QG8/4 Series
Table 1-1
summarizes the features available in the MC9S08QG8/4 series of MCUs.
Table 1-1. Devices in the MC9S08QG8/4 Series
Feature
Device
MC9S08QG8
MC9S08QG4
Package
16-Pin
8-Pin
16-Pin
8-Pin
FLASH
8K
4K
RAM
512
256
XOSC
yes
no
yes
no
ICS
yes
yes
ACMP
yes
yes
ADC
8-ch
4-ch
8-ch
4-ch
DBG
yes
yes
no
IIC
yes
yes
IRQ
yes
yes
KBI
8-pin
4-pin
8-pin
4-pin
MTIM
yes
yes
SCI
yes
no
yes
no
SPI
yes
no
yes
no
TPM
2-ch
1-ch
2-ch
1-ch
I/O pins
12 I/O
1 Output only
1 Input only
4 I/O
1 Output only
1 Input only
12 I/O
1 Output only
1 Input only
4 I/O
1 Output only
1 Input only
Package
Types
16 PDIP
16 QFN
16 TSSOP
8 DFN
8 SOIC
16 QFN
16 TSSOP
8 DFN
8 PDIP
8 SOIC
Chapter 1 Device Overview
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
20
Freescale Semiconductor
1.1.2
MCU Block Diagram
Figure 1-1. MC9S08QG8/4 Block Diagram
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
Chapter 1 Device Overview
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
21
Table 1-2
provides the functional versions of the on-chip modules.
System Clock Distribution
Figure 1-2
shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function. All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Versions of On-Chip Modules
Module
Version
Analog Comparator
(ACMP)
2
Analog-to-Digital Converter
(ADC)
1
Central Processing Unit
(CPU)
2
IIC Module
(IIC)
1
Internal Clock Source
(ICS)
1
Keyboard Interrupt
(KBI)
2
Modulo Timer
(MTIM)
1
Serial Communications Interface
(SCI)
3
Serial Peripheral Interface
(SPI)
3
Timer Pulse-Width Modulator
(TPM)
2
Low-Power Oscillator
(XOSC)
1
Debug Module
(DBG)
2
TPM
MTIM
IIC
SCI
SPI
CPU
BDC
ADC
FLASH
ICS
ICSOUT
2
ICSFFE
SYSTEM
LOGIC
BUSCLK
ICSLCLK**
CONTROL
FIXED FREQ CLOCK (XCLK)
ICSERCLK*
RTI
* ICSERCLK requires XOSC module.
** ICSLCLK is the alternate BDC clock source for the MC9S08QG8/4.
2
FLASH has frequency
requirements for
program
and erase operation.
See
Appendix A,
"Electrical
Characteristics
."
ADC has min and max
frequency requirements.
See the ADC chapter
and
Appendix A, "Electrical
Characteristics
."
ICSFFCLK
XOSC
EXTAL
XTAL
COP
1-kHz
TCLK
Chapter 1 Device Overview
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
22
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
23
Chapter 2
External Signal Description
This section describes signals that connect to package pins. It includes pinout diagrams, table of signal
properties, and detailed discussions of signals.
2.1
Device Pin Assignment
Figure 2-1
shows the pin assignments for the 8-pin packages.
Figure 2-2
shows the pin assignments for the
16-pin package. See
Table 1-1
to see which package types are available for each device in the series.
Figure 2-1. 8-Pin Packages
8-PIN ASSIGNMENT
PDIP/SOIC
1
2
3
4
8
7
6
5
8-PIN ASSIGNMENT
DFN
1
2
3
4
8
7
6
5
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/ADP1/ACMP
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
V
SS
V
DD
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/ADP1/ACMP
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
V
SS
V
DD
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
24
Freescale Semiconductor
Figure 2-2. 16-Pin Packages
1
2
3
4
5
6
7
8
16-PIN ASSIGNMENT
PDIP
16
15
14
13
12
11
10
9
16-PIN ASSIGNMENT
QFN
16
15
14
13
1
2
3
4
PTA5/IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
V
DD
V
SS
PTB4/MISO
PTB5/TPMCH1/
SS
PTB6/SD
A/XT
AL
PTB7/SCL/EXT
AL
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
PTB1/KBIP5/TxD/ADP5
PTA1/KBIP1/ADP1/ACMP
PT
A2/KBIP2/SD
A/ADP2
PT
A3/KBIP3/SCL/ADP3
PTB0/KBIP4/RxD/ADP4
PT
A0/KBIP0/TPMCH0/ADP0/A
CMP+
12
11
10
9
5
6
7
8
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/ADP1/ACMP
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
PTB2/KBIP6/SPSCK/ADP6
PTB3/KBIP7/MOSI/ADP7
V
SS
V
DD
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTB4/MISO
PTB5/TPMCH1/SS
PTB6/SDA/XTAL
PTB7/SCL/EXTAL
PTA1/KBIP1/ADP1/ACMP
PTA2/KBIP2/SDA/ADP2
PTB1/KBIP5/TxD/ADP5
PTB5/TPMCH1/SS
PTB6/SDA/XTAL
16-PIN ASSIGNMENT
TSSOP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTB2/KBIP6/SPSCK/ADP6
PTA3/KBIP3/SCL/ADP3
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB0/KBIP4/RxD/ADP4
PTA5/IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
V
DD
V
SS
PTB7/SCL/EXTAL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
25
2.2
Recommended System Connections
Figure 2-3
shows pin connections that are common to almost all MC9S08QG8/4 application systems.
Figure 2-3. Basic System Connections
2.2.1
Power
V
DD
and V
SS
are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry, ACMP and ADC modules, and to an internal voltage regulator. The internal voltage
regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.
V
DD
V
SS
RESET/IRQ
OPTIONAL
MANUAL
RESET
PORT
A
V
DD
BACKGROUND HEADER
C
BY
0.1
F
C
BLK
10
F
+
3 V
+
SYSTEM
POWER
I/O AND
PERIPHERAL
INTERFACE TO
SYSTEM
APPLICATION
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/ADP1/ACMP
PTA2/KBIP2/SDA/ADP2
PTA3/KBIP3/SCL/ADP3
V
DD
PORT
B
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
PTB2/KBIP6/SPSCK/ADP6
MC9S08QG8/4
PTB3/KBIP7/MOSI/ADP7
PTB4/MISO
PTB5/TPMCH1/SS
BKGD
PTB6/SDA/XTAL
PTB7/SCL/EXTAL
XTAL
EXTAL
C2
C1
X1
R
F
R
S
NOTE 1
NOTE 2
NOTES:
1. Not required if using the internal clock option.
2. XTAL is the same pin as PTB6; EXTAL the same pin as PTB7.
3. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can
be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM
command.
4. IRQ feature has optional internal pullup device.
5. RC filter on RESET/IRQ pin recommended for noisy environments.
ASYNCHRONOUS
INTERRUPT
INPUT
NOTE 2
V
DD
4.7 k
10 k
0.1
F
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
26
Freescale Semiconductor
Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic
capacitor, such as a 10-
F tantalum capacitor, to provide bulk charge storage for the overall system, and a
bypass capacitor, such as a 0.1-
F ceramic capacitor, located as near to the MCU power pins as practical
to suppress high-frequency noise.
2.2.2
Oscillator (XOSC)
Out of reset, the MCU uses an internally generated clock provided by the internal clock source (ICS)
module. The internal frequency is nominally 16-MHz and the default ICS settings will provide for a
4-MHz bus out of reset. For more information on the ICS, see
Chapter 10, "Internal Clock Source
(S08ICSV1)
."
The oscillator module (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or
ceramic resonator in either of two frequency ranges selected by the RANGE bit in ICSC2. Rather than a
crystal or ceramic resonator, an external clock source can be connected to the EXTAL input pin.
Refer to
Figure 2-3
for the following discussion. R
S
(when used) and R
F
should be low-inductance
resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have
too much inductance. C1 and C2 normally should be high-quality ceramic capacitors that are specifically
designed for high-frequency applications.
R
F
is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup and its
value is not generally critical. Typical systems use 1 M
to 10 M. Higher values are sensitive to humidity
and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin
capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C1 and C2, which are usually the same size. As a first-order approximation,
use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and
XTAL).
2.2.3
Reset (Input Only)
After a power-on reset (POR), the PTA5/IRQ/TCLK/RESET pin defaults to a general-purpose input port
pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET input pin. After configured as
RESET, the pin will remain RESET until the next POR. The RESET pin can be used to reset the MCU
from an external source when the pin is driven low. When enabled as the RESET pin (RSTPE = 1), an
internal pullup device is automatically enabled.
NOTE
This pin does not contain a clamp diode to V
DD
and should not be driven
above V
DD
.
The voltage measured on the internally pulled up RESET pin will not be
pulled to V
DD
. The internal gates connected to this pin are pulled to V
DD
.
The RESET pullup should not be used to pullup components external to the
MCU.
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
27
NOTE
In EMC-sensitive applications, an external RC filter is recommended on the
RESET pin, if enabled. See
Figure 2-3
for an example.
2.2.4
Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see
5.8.3, "System Background Debug
Force Reset Register (SBDFR)
," for more information), the PTA4/ACMPO/BKGD/MS pin functions as a
mode select pin. Immediately after any reset, the pin functions as the background pin and can be used for
background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal
pullup device is automatically enabled.
The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is
set following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pin's
alternative pin functions.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the
internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard
background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a
background debug force reset, which will force the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU's BDC clock per bit time. The target MCU's BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5
General-Purpose I/O and Peripheral Ports
The MC9S08QG8/4 series of MCUs support up to 12 general-purpose I/O pins, 1 input-only pin, and 1
output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard
interrupts, etc.). On each MC9S08QG8/4 device, there is one input-only and one output-only port pin.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
For information about controlling these pins as general-purpose I/O pins, see the
Chapter 6, "Parallel
Input/Output Control
."
For information about how and when on-chip peripheral systems use these pins,
see the appropriate chapter referenced in
Table 2-2
.
Immediately after reset, all pins that are not output-only are configured as high-impedance
general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
28
Freescale Semiconductor
not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin
defaults to BKGD/MS on any reset.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unused pins to outputs so the pins do not float.
When using the 8-pin devices, the user must either enable on-chip pullup
devices or change the direction of non-bonded out port B pins to outputs so
the pins do not float.
2.2.5.1
Pin Control Registers
To select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin
control register located in the high page register block of the memory map. The pin control registers
operate independently of the parallel I/O registers and allow control of a port on an individual pin basis.
2.2.5.1.1
Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the
pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral function, regardless of the state of the corresponding
pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
The KBI module, when enabled for rising edge detection, causes an enabled internal pull device to be
configured as a pulldown.
2.2.5.2
Output Slew Rate Control
Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate
control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in
order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
2.2.5.3
Output Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in one of
the drive strength select registers (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
29
Table 2-1. Pin Sharing Priority
Pin Number
Priority
16-pin
8-pin
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
PTA5
1
1
Pin does not contain a clamp diode to V
DD
and should not be driven above V
DD
.
The voltage measured on the internally pulled up RESET in will not be pulled
to V
DD
. The internal gates connected to this pin are pulled to V
DD
.
IRQ
TCLK
RESET
2
2
PTA4
ACMPO
BKGD
MS
3
3
V
DD
4
4
V
SS
5
--
PTB7
SCL
2
2
IIC pins can be repositioned using IICPS in SOPT2, default reset locations are
on PTA2 and PTA3.
EXTAL
6
--
PTB6
SDA
2
XTAL
7
--
PTB5
TPMCH1
SS
8
--
PTB4
MISO
9
--
PTB3
KBIP7
MOSI
ADP7
10
--
PTB2
KBIP6
SPSCK
ADP6
11
--
PTB1
KBIP5
TxD
ADP5
12
--
PTB0
KBIP4
RxD
ADP4
13
5
PTA3
KBIP3
SCL
2
ADP3
14
6
PTA2
KBIP2
SDA
2
ADP2
15
7
PTA1
KBIP1
ADP1
3
3
If ACMP and ADC are both enabled, both will have access to the pin.
ACMP
3
16
8
PTA0
KBIP0
TPMCH0
ADP0
3
ACMP+
3
Table 2-2. Pin Function Reference
Signal Function
Example(s)
Reference
Port Pins
PTAx, PTBx
Chapter 6, "Parallel Input/Output Control
"
Analog comparator
ACMPO, ACMP, ACMP+
Chapter 8, "Analog Comparator (S08ACMPV2)
"
Serial peripheral interface
SS, MISO, MOSI, SPSCK
Chapter 15, "Serial Peripheral Interface (S08SPIV3)
Keyboard interrupts
KBIPx
Chapter 12, "Keyboard Interrupt (S08KBIV2)
"
Timer/PWM
TCLK, TPMCHx
Chapter 16, "Timer/Pulse-Width Modulator (S08TPMV2)
"
Inter-integrated circuit
SCL, SDA
Chapter 11, "Inter-Integrated Circuit (S08IICV1)
"
Serial communications interface
TxD, RxD
Chapter 14, "Serial Communications Interface (S08SCIV3)
Oscillator/clocking
EXTAL, XTAL
Chapter 10, "Internal Clock Source (S08ICSV1)
"
Analog-to-digital
ADPx
Chapter 9, "Analog-to-Digital Converter (S08ADC10V1)
"
Power/core
BKGD/MS, V
DD
, V
SS
Chapter 2, "External Signal Description
"
Reset and interrupts
RESET, IRQ
Chapter 5, "Resets, Interrupts, and General System Control
"
Lowest
Highest
Chapter 2 External Signal Description
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
30
Freescale Semiconductor
NOTE
When an alternative function is first enabled, it is possible to get a spurious
edge to the module. User software should clear out any associated flags
before interrupts are enabled.
Table 2-1
shows the priority if multiple
modules are enabled. The highest priority module will have control over the
pin. Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module. It is
recommended that all modules that share a pin be disabled before enabling
anther module.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
31
Chapter 3
Modes of Operation
3.1
Introduction
The operating modes of the MC9S08QG8/4 are described in this section. Entry into each mode, exit from
each mode, and functionality while in each mode are described.
3.2
Features
Active background mode for code development
Wait mode:
-- CPU halts operation to conserve power
-- System clocks running
-- Full voltage regulation is maintained
Stop modes: CPU and bus clocks stopped
-- Stop1: Full powerdown of internal circuits for maximum power savings
-- Stop2: Partial powerdown of internal circuits; RAM contents retained
-- Stop3: All internal circuits powered for fast recovery; RAM and register contents are retained
3.3
Run Mode
Run is the normal operating mode for the MC9S08QG8/4. This mode is selected upon the MCU exiting
reset if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with
execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4
Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip debug module (DBG), provides the means for
analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
When the BKGD/MS pin is low during POR or immediately after issuing a background debug
force reset (see
5.8.3, "System Background Debug Force Reset Register (SBDFR)
")
When a BACKGROUND command is received through the BKGD pin
When a BGND instruction is executed
When encountering a BDC breakpoint
When encountering a DBG breakpoint
Chapter 3 Modes of Operation
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
32
Freescale Semiconductor
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user application program.
Background commands are of two types:
Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
-- Memory access commands
-- Memory-access-with-status commands
-- BDC register access commands
-- The BACKGROUND command
Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
-- Read or write CPU registers
-- Trace one user program instruction at a time
-- Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the FLASH
program memory before the MCU is operated in run mode for the first time. When the MC9S08QG8/4 is
shipped from the Freescale factory, the FLASH program memory is erased by default unless specifically
noted, so there is no program that could be executed in run mode until the FLASH memory is initially
programmed. The active background mode can also be used to erase and reprogram the FLASH memory
after it has been previously programmed.
For additional information about the active background mode, refer to the
Development Support
chapter.
3.5
Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in the condition code register (CCR) is cleared
when the CPU enters wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits wait
mode and resumes processing, beginning with the stacking operations leading to the interrupt service
routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
while the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
Chapter 3 Modes of Operation
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
33
3.6
Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set.
In any stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the
reference clocks running. See
Chapter 10, "Internal Clock Source (S08ICSV1)
," for more information.
Table 3-1
shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1
Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
Table 3-1
. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
interrupt (RTI), LVD, ADC, IRQ, or the KBI.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.1.1
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.
For the ADC to operate the LVD must be left enabled when entering stop3.
3.6.1.2
Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This
register is described in
Chapter 17, "Development Support
." If ENBDM is set when the CPU executes a
Table 3-1. Stop Mode Selection
STOPE
ENBDM
1
1
ENBDM is located in the BDCSCR which is only accessible through BDC commands, see
Section 17.4.1.1, "BDC
Status and Control Register (BDCSCR)
".
LVDE
LVDSE
PDC
PPDC
Stop Mode
0
x
x
x
x
Stop modes disabled; illegal opcode reset if STOP
instruction executed
1
1
x
x
x
Stop3 with BDM enabled
2
2
When in Stop3 mode with BDM enabled, The S
IDD
will be near R
IDD
levels because internal clocks are enabled.
1
0
Both bits must be 1
x
x
Stop3 with voltage regulator active
1
0
Either bit a 0
0
x
Stop3
1
0
Either bit a 0
1
1
Stop2
1
0
Either bit a 0
1
0
Stop1
Chapter 3 Modes of Operation
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
34
Freescale Semiconductor
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
stop mode. Because of this, background debug communication remains possible. In addition, the voltage
regulator does not enter its low-power standby state but maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available.
3.6.2
Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in
Table 3-1
. Most
of the internal circuitry of the MCU is powered off in stop2 as in stop1 with the exception of the RAM.
Upon entering stop2, all I/O pin control signals are latched so that the pins retain their states during stop2.
Exit from stop2 is performed by asserting the wake-up pin (PTA5) on the MCU.
NOTE
PTA5/IRQ/TCLK/RESET always functions as an active-low wakeup input
when the MCU is in stop2, regardless of how the pin is configured before
entering stop2. The pullup on this pin is always disabled in stop2. This pin
must be driven or pulled high externally while in stop2 mode.
In addition, the real-time interrupt (RTI) can wake the MCU from stop2, if enabled.
Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):
All module control and status registers are reset
The LVD reset function is enabled and the MCU remains in the reset state if V
DD
is below the LVD
trip point (low trip point selected due to POR)
The CPU takes the reset vector
In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
Chapter 3 Modes of Operation
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
35
3.6.3
Stop1 Mode
Stop1 mode is entered by executing a STOP instruction under the conditions as shown in
Table 3-1
. Most
of the internal circuitry of the MCU is powered off in stop1, providing the lowest possible standby current.
Upon entering stop1, all I/O pins automatically transition to their default reset states.
Exit from stop1 is performed by asserting the wake-up pin (PTA5) on the MCU.
NOTE
PTA5/IRQ/TCLK/RESET always functions as an active-low wakeup input
when the MCU is in stop1, regardless of how the pin is configured before
entering stop1. The pullup on this pin is always disabled in stop1. This pin
must be driven or pulled high externally while in stop1 mode.
In addition, the real-time interrupt (RTI) can wake the MCU from stop1 if enabled.
Upon wake-up from stop1 mode, the MCU starts up as from a power-on reset (POR):
All module control and status registers are reset
The LVD reset function is enabled and the MCU remains in the reset state if V
DD
is below the LVD
trip point (low trip point selected due to POR)
The CPU takes the reset vector
In addition to the above, upon waking up from stop1, the PDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop1 recovery routine. PDF remains set until a 1 is written to PPDACK in
SPMSC2.
3.6.4
On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Section 3.6.3, "Stop1
Mode
,"
Section 3.6.2, "Stop2 Mode
," and
Section 3.6.1, "Stop3 Mode
," for specific information on system
behavior in stop modes.
Table 3-2. Stop Mode Behavior
Peripheral
Mode
Stop1
Stop2
Stop3
CPU
Off
Off
Standby
RAM
Off
Standby
Standby
FLASH
Off
Off
Standby
Parallel Port Registers
Off
Off
Standby
ADC
Off
Off
Optionally On
1
ACMP
Off
Off
Standby
ICS
Off
Off
Optionally On
2
IIC
Off
Off
Standby
Chapter 3 Modes of Operation
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
36
Freescale Semiconductor
MTIM
Off
Off
Standby
SCI
Off
Off
Standby
SPI
Off
Off
Standby
TPM
Off
Off
Standby
Voltage Regulator
Off
Standby
Standby
XOSC
Off
Off
Optionally On
3
I/O Pins
Hi-Z
States Held
States Held
1
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
2
IRCLKEN and IREFSTEN set in ICSC1, else in standby.
3
ERCLKEN and EREFSTEN set in ICSC2 for, else in standby. For high frequency range (RANGE in
ICSC2 set) requires the LVD to also be enabled in stop3.
Table 3-2. Stop Mode Behavior (continued)
Peripheral
Mode
Stop1
Stop2
Stop3
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
37
Chapter 4
Memory Map and Register Definition
4.1
MC9S08QG8/4 Memory Map
As shown in
Figure 4-1
, on-chip memory in the MC9S08QG8/4 series of MCUs consists of RAM, FLASH
program memory for nonvolatile data storage, and I/O and control/status registers. The registers are
divided into these groups:
Direct-page registers (0x0000 through 0x005F)
High-page registers (0x1800 through 0x184F)
Nonvolatile registers (0xFFB0 through 0xFFBF)
Figure 4-1. MC9S08QG8/4 Memory Map
DIRECT PAGE REGISTERS
RAM
HIGH PAGE REGISTERS
512 BYTES
0x0000
0x005F
0x0060
0x025F
0x1800
0x17FF
0x184F
0xFFFF
0x0260
MC9S08QG8
FLASH
8192 BYTES
0x1850
MC9S08QG4
UNIMPLEMENTED
51,120 BYTES
0xE000
0xDFFF
DIRECT PAGE REGISTERS
RAM
HIGH PAGE REGISTERS
256 BYTES
0x0000
0x005F
0x0060
0x1800
0x17FF
0x184F
0xFFFF
FLASH
4096 BYTES
0x1850
0x015F
0x0160
0xF000
0xEFFF
UNIMPLEMENTED
5536 BYTES
0x025F
0x0260
UNIMPLEMENTED
5536 BYTES
RESERVED
256 BYTES
UNIMPLEMENTED
51,120 BYTES
0xE000
0xDFFF
RESERVED
4096 BYTES
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
38
Freescale Semiconductor
4.2
Reset and Interrupt Vector Assignments
Table 4-1
shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QG8/4.
Table 4-1. Reset and Interrupt Vectors
Address
(High:Low)
Vector
Vector Name
0xFFC0:FFC1
0xFFCE:FFCF
Unused Vector Space
(available for user program)
0xFFD0:FFD1
RTI
Vrti
0xFFD2:FFD3
Reserved
--
0xFFD4:FFD5
Reserved
--
0xFFD6:FFD7
ACMP
Vacmp
0xFFD8:FFD9
ADC Conversion
Vadc
0xFFDA:FFDB
KBI Interrupt
Vkeyboard
0xFFDC:FFDD
IIC
Viic
0xFFDE:FFDF
SCI Transmit
Vscitx
0xFFE0:FFE1
SCI Receive
Vscirx
0xFFE2:FFE3
SCI Error
Vscierr
0xFFE4:FFE5
SPI
Vspi
0xFFE6:FFE7
MTIM Overflow
Vmtim
0xFFE8:FFE9
Reserved
--
0xFFEA:FFEB
Reserved
--
0xFFEC:FFED
Reserved
--
0xFFEE:FFEF
Reserved
--
0xFFF0:FFF1
TPM Overflow
Vtpmovf
0xFFF2:FFF3
TPM Channel 1
Vtpmch1
0xFFF4:FFF5
TPM Channel 0
Vtpmch0
0xFFF6:FFF7
Reserved
--
0xFFF8:FFF9
Low Voltage Detect
Vlvd
0xFFFA:FFFB
IRQ
Virq
0xFFFC:FFFD
SWI
Vswi
0xFFFE:FFFF
Reset
Vreset
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
39
4.3
Register Addresses and Bit Assignments
The registers in the MC9S08QG8/4 are divided into these groups:
Direct-page registers are located in the first 96 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
The nonvolatile register area consists of a block of 16 locations in FLASH memory at
0xFFB00xFFBF. Nonvolatile register locations include:
-- NVPROT and NVOPT are loaded into working registers at reset.
-- An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory.
Because the nonvolatile register locations are FLASH memory, they must be erased and
programmed like other FLASH memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register.
Table 4-2
is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in
Table 4-2
can use the more efficient direct addressing mode that requires only
the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold
text. In
Table 4-3
and
Table 4-4
, the whole address in column one is shown in bold. In
Table 4-2
,
Table 4-3
,
and
Table 4-4
, the register names in column two are shown in bold to set them apart from the bit names to
the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this
unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could
read as 1s or 0s.
Table 4-2. Direct-Page Register Summary
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
PTAD
0
0
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
0x0001
PTADD
0
0
PTADD5
PTADD4
PTADD3
PTADD2
PTADD1
PTADD0
0x0002
PTBD
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
0x0003
PTBDD
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
0x0004
0x000B
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0x000C
KBISC
0
0
0
0
KBF
KBACK
KBIE
KBIMOD
0x000D
KBIPE
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
0x000E
KBIES
KBEDG7
KBEDG6
KBEDG5
KBEDG4
KBEDG3
KBEDG2
KBEDG1
KBEDG0
0x000F
IRQSC
0
IRQPDD
0
IRQPE
IRQF
IRQACK
IRQIE
IRQMOD
0x0010
ADCSC1
COCO
AIEN
ADCO
ADCH
0x0011
ADCSC2
ADACT
ADTRG
ACFE
ACFGT
--
--
--
--
0x0012
ADCRH
0
0
0
0
0
0
ADR9
ADR8
0x0013
ADCRL
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
0x0014
ADCCVH
0
0
0
0
0
0
ADCV9
ADCV8
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
40
Freescale Semiconductor
0x0015
ADCCVL
ADCV7
ADCV6
ADCV5
ADCV4
ADCV3
ADCV2
ADCV1
ADCV0
0x0016
ADCCFG
ADLPC
ADIV
ADLSMP
MODE
ADICLK
0x0017
APCTL1
ADPC7
ADPC6
ADPC5
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
0x0018
Reserved
0
0
0
0
0
0
0
0
0x0019
Reserved
0
0
0
0
0
0
0
0
0x001A
ACMPSC
ACME
ACBGS
ACF
ACIE
ACO
ACOPE
ACMOD
0x001B
0x001F
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0x0020
SCIBDH
0
0
0
SBR12
SBR11
SBR10
SBR9
SBR8
0x0021
SCIBDL
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0x0022
SCIC1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
0x0023
SCIC2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0x0024
SCIS1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0x0025
SCIS2
0
0
0
0
0
BRK13
0
RAF
0x0026
SCIC3
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
0x0027
SCID
Bit 7
6
5
4
3
2
1
Bit 0
0x0028
SPIC1
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
0x0029
SPIC2
0
0
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
0x002A
SPIBR
0
SPPR2
SPPR1
SPPR0
0
SPR2
SPR1
SPR0
0x002B
SPIS
SPRF
0
SPTEF
MODF
0
0
0
0
0x002C
Reserved
0
0
0
0
0
0
0
0
0x002D
SPID
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
Reserved
--
--
--
--
--
--
--
--
0x002F
Reserved
--
--
--
--
--
--
--
--
0x0030
IICA
ADDR
0
0x0031
IICF
MULT
ICR
0x0032
IICC
IICEN
IICIE
MST
TX
TXAK
RSTA
0
0
0x0033
IICS
TCF
IAAS
BUSY
ARBL
0
SRW
IICIF
RXAK
0x0034
IICD
DATA
0x0035
Reserved
--
--
--
--
--
--
--
--
0x0036
Reserved
--
--
--
--
--
--
--
--
0x0037
Reserved
--
--
--
--
--
--
--
--
0x0038
ICSC1
CLKS
RDIV
IREFS
IRCLKEN
IREFSTEN
0x0039
ICSC2
BDIV
RANGE
HGO
LP
EREFS
ERCLKEN EREFSTEN
0x003A
ICSTRM
TRIM
0x003B
ICSSC
0
0
0
0
CLKST
OSCINIT
FTRIM
0x003C
MTIMSC
TOF
TOIE
TRST
TSTP
0
0
0
0
0x003D
MTIMCLK
0
0
CLKS
PS
0x003E
MTIMCNT
COUNT
0x003F
MTIMMOD
MOD
Table 4-2. Direct-Page Register Summary (continued)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
41
High-page registers, shown in
Table 4-3
, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
0x0040
TPMSC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
0x0041
TPMCNTH
Bit 15
14
13
12
11
10
9
Bit 8
0x0042
TPMCNTL
Bit 7
6
5
4
3
2
1
Bit 0
0x0043
TPMMODH
Bit 15
14
13
12
11
10
9
Bit 8
0x0044
TPMMODL
Bit 7
6
5
4
3
2
1
Bit 0
0x0045
TPMC0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
0x0046
TPMC0VH
Bit 15
14
13
12
11
10
9
Bit 8
0x0047
TPMC0VL
Bit 7
6
5
4
3
2
1
Bit 0
0x0048
TPMC1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
0x0049
TPMC1VH
Bit 15
14
13
12
11
10
9
Bit 8
0x004A
TPMC1VL
Bit 7
6
5
4
3
2
1
Bit 0
0x004B
0x005F
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Table 4-3. High-Page Register Summary
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0x1800
SRS
POR
PIN
COP
ILOP
ILAD
0
LVD
0
0x1801
SBDFR
0
0
0
0
0
0
0
BDFR
0x1802
SOPT1
COPE
COPT
STOPE
--
0
0
BKGDPE
RSTPE
0x1803
SOPT2
COPCLKS
0
0
0
0
0
IICPS
ACIC
0x1804
Reserved
--
--
--
--
--
--
--
--
0x1805
Reserved
--
--
--
--
--
--
--
--
0x1806
SDIDH
--
--
--
--
ID11
ID10
ID9
ID8
0x1807
SDIDL
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x1808
SRTISC
RTIF
RTIACK
RTICLKS
RTIE
0
RTIS
0x1809
SPMSC1
LVDF
LVDACK
LVDIE
LVDRE
LVDSE
LVDE
0
BGBE
0x180A
SPMSC2
0
0
0
PDF
PPDF
PPDACK
PDC
PPDC
0x180B
Reserved
--
--
--
--
--
--
--
--
0x180C
SPMSC3
LVWF
LVWACK
LVDV
LVWV
--
--
--
--
0x180D
0x180F
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0x1810
DBGCAH
Bit 15
14
13
12
11
10
9
Bit 8
0x1811
DBGCAL
Bit 7
6
5
4
3
2
1
Bit 0
0x1812
DBGCBH
Bit 15
14
13
12
11
10
9
Bit 8
0x1813
DBGCBL
Bit 7
6
5
4
3
2
1
Bit 0
0x1814
DBGFH
Bit 15
14
13
12
11
10
9
Bit 8
0x1815
DBGFL
Bit 7
6
5
4
3
2
1
Bit 0
0x1816
DBGC
DBGEN
ARM
TAG
BRKEN
RWA
RWAEN
RWB
RWBEN
Table 4-2. Direct-Page Register Summary (continued)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
42
Freescale Semiconductor
Nonvolatile FLASH registers, shown in
Table 4-4
, are located in the FLASH memory. These registers
include an 8-byte backdoor key that optionally can be used to gain access to secure memory resources.
During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH
memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers
to control security and block protection options.
0x1817
DBGT
TRGSEL
BEGIN
0
0
TRG3
TRG2
TRG1
TRG0
0x1818
DBGS
AF
BF
ARMF
0
CNT3
CNT2
CNT1
CNT0
0x1819
0x181F
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0x1820
FCDIV
DIVLD
PRDIV8
DIV
0x1821
FOPT
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
0x1822
Reserved
--
--
--
--
--
--
--
--
0x1823
FCNFG
0
0
KEYACC
0
0
0
0
0
0x1824
FPROT
FPS
FPDIS
0x1825
FSTAT
FCBEF
FCCF
FPVIOL
FACCERR
0
FBLANK
0
0
0x1826
FCMD
FCMD
0x1827
0x183F
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0x1840
PTAPE
0
0
PTAPE5
PTAPE4
PTAPE3
PTAPE2
PTAPE1
PTAPE0
0x1841
PTASE
0
0
PTASE5
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
0x1842
PTADS
0
0
PTADS5
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
0x1843
Reserved
--
--
--
--
--
--
--
--
0x1844
PTBPE
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
0x1845
PTBSE
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
0x1846
PTBDS
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
0x1847
Reserved
--
--
--
--
--
--
--
--
Table 4-4. Nonvolatile Register Summary
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
0xFFAE
Reserved for
Storage of FTRIM
0
0
0
0
0
0
0
FTRIM
0xFFAF
Reserved for
Storage of ICSTRM
TRIM
0xFFB0
0xFFB7
NVBACKKEY
8-Byte Comparison Key
0xFFB8
0xFFBC
Unused
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0xFFBD
NVPROT
FPS
FPDIS
0xFFBE
Unused
--
--
--
--
--
--
--
--
0xFFBF
NVOPT
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
Table 4-3. High-Page Register Summary (continued)
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
43
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the FLASH if needed (normally through the background
debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
4.4
RAM
The MC9S08QG8/4 includes static RAM. The locations in RAM below 0x0100 can be accessed using the
more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention (V
RAM
).
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08QG8/4, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct page
RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include
the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the
highest address of the RAM in the Freescale Semiconductor-provided equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See
Section 4.6, "Security
," for a detailed
description of the security feature.
The RAM array is not automatically initialized out of reset.
4.5
FLASH
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire background debug interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
44
Freescale Semiconductor
4.5.1
Features
Features of the FLASH memory include:
FLASH size
-- MC9S08QG8: 8,192 bytes (16 pages of 512 bytes each)
-- MC9S08QG4: 4,096 bytes (8 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
4.5.2
Program and Erase Times
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
FCLK
) between 150 kHz and
200 kHz (see
Section 4.7.1, "FLASH Clock Divider Register (FCDIV)
"). This register can be written only
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
FCLK
) is used by the command processor to time
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-5
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f
FCLK
). The time for one cycle of FCLK is t
FCLK
= 1/f
FCLK
. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where t
FCLK
= 5
s. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-5. Program and Erase Times
Parameter
Cycles of FCLK
Time if FCLK = 200 kHz
Byte program
9
45
s
Byte program (burst)
4
20
s
1
1
Excluding start/end overhead
Page erase
4000
20 ms
Mass erase
20,000
100 ms
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
45
4.5.3
Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the FLASH array. The address and data information from this
write is latched into the FLASH interface. This write is a required first step in any command
sequence. For erase and blank check commands, the value of the data is not important. For page
erase commands, the address may be any address in the 512-byte page of FLASH to be erased. For
mass erase and blank check commands, the address can be any address in the FLASH memory.
Whole pages of 512 bytes are the smallest block of FLASH that may be erased.
NOTE
Do not program any byte in the FLASH more than once after a successful
erase operation. Reprogramming bits to a byte that is already programmed
is not allowed without first erasing the page in which the byte resides or
mass erasing the entire FLASH memory. Programming without first erasing
may disturb data stored in the FLASH.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase
(0x41). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Aborting a command in this way sets the FACCERR access error flag, which must be cleared before
starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the
possibility of any unintended changes to the FLASH memory contents. The command complete flag
(FCCF) indicates when a command is complete. The command sequence must be completed by clearing
FCBEF to launch the command.
Figure 4-2
is a flowchart for executing all of the commands except for
burst programming. The FCDIV register must be initialized before using any FLASH commands. This
must be done only once following a reset.
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
46
Freescale Semiconductor
Figure 4-2. FLASH Program and Erase Flowchart
4.5.4
Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the FLASH
array does not need to be disabled between program operations. Ordinarily, when a program or erase
command is issued, an internal charge pump associated with the FLASH memory must be enabled to
supply high voltage to the array. Upon completion of the command, the charge pump is turned off. When
a burst program command is issued, the charge pump is enabled and then remains enabled after completion
of the burst program operation if these two conditions are met:
The next burst program command has been queued before the current program operation has
completed.
The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of FLASH memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIOL OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (Note 2)
1
0
FCCF ?
ERROR EXIT
DONE
Note 2: Wait at least four bus cycles
0
FACCERR ?
CLEAR ERROR
FACCERR ?
WRITE TO FCDIV (Note 1)
Note 1: Required only once after reset.
1
before checking FCBEF or FCCF.
FLASH PROGRAM AND
ERASE FLOW
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
47
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
program time provided that the conditions above are met. In the case the next sequential address is the
beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
Figure 4-3. FLASH Burst Program Flowchart
1
0
FCBEF ?
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND (0x25) TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (Note 2)
NO
YES
NEW BURST COMMAND ?
1
0
FCCF ?
ERROR EXIT
DONE
Note 2: Wait at least four bus cycles before
1
0
FACCERR ?
CLEAR ERROR
FACCERR ?
Note 1: Required only once after reset.
WRITE TO FCDIV (Note 1)
checking FCBEF or FCCF.
FLASH BURST
PROGRAM FLOW
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
48
Freescale Semiconductor
4.5.5
Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Writing to a FLASH address before the internal FLASH clock frequency has been set by writing
to the FCDIV register
Writing to a FLASH address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
Writing a second time to a FLASH address before launching the previous command (There is only
one write to FLASH for every command.)
Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
Writing to any FLASH control register other than FCMD after writing to a FLASH address
Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)
to FCMD
Accessing (read or write) any FLASH control register other than the write to FSTAT (to clear
FCBEF and launch the command) after writing the command to FCMD
The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
Writing 0 to FCBEF to cancel a partial command
4.5.6
FLASH Block Protection
The block protection feature prevents the protected region of FLASH from program or erase changes.
Block protection is controlled through the FLASH protection register (FPROT). When enabled, block
protection begins at any 512 byte boundary below the last address of FLASH, 0xFFFF. (See
Section 4.7.4,
"FLASH Protection Register (FPROT and NVPROT)
").
After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the
nonvolatile register block of the FLASH memory. FPROT cannot be changed directly from application
software so a runaway program cannot alter the block protection settings. Because NVPROT is within the
last 512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannot
be altered (intentionally or unintentionally) by the application software. FPROT can be written through
background debug commands, which allows a way to erase and reprogram a protected FLASH memory.
The block protection mechanism is illustrated in
Figure 4-4
. The FPS bits are used as the upper bits of the
last address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits
as shown. For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the
FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected
memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) must
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
49
be programmed to logic 0 to enable block protection. Therefore the value 0xF8 must be programmed into
NVPROT to protect addresses 0xFA00 through 0xFFFF.
Figure 4-4. Block Protection Mechanism
One use for block protection is to block protect an area of FLASH memory for a bootloader program. This
bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because
the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and
reprogram operation.
4.5.7
Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector
redirection allows users to modify interrupt vector information without unprotecting bootloader and reset
vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register
located at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the FLASH
memory must be block protected by programming the NVPROT register located at address 0xFFBD. All
of the interrupt vectors (memory locations 0xFFC00xFFFD) are redirected, though the reset vector
(0xFFFE:FFFF) is not.
For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through
0xFFFF. The interrupt vectors (0xFFC00xFFFD) are redirected to the locations 0xFDC00xFDFD. Now,
if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vector
instead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected
portion of the FLASH with new program code including new interrupt vector values while leaving the
protected area, which includes the default vector locations, unchanged.
4.6
Security
The MC9S08QG8/4 includes circuitry to prevent unauthorized access to the contents of FLASH and RAM
memory. When security is engaged, FLASH and RAM are considered secure resources. Direct-page
registers, high-page registers, and the background debug controller are considered unsecured resources.
Programs executing within secure memory have normal access to any MCU memory locations and
resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in
the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASH
into the working FOPT register in high-page register space. A user engages security by programming the
NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state
disengages security and the other three combinations engage security. Notice the erased state (1:1) makes
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
A15
A14
A13
A12
A11
A10
A9
A8
1
A7 A6 A5 A4 A3 A2 A1 A0
1
1
1
1
1
1
1
1
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
50
Freescale Semiconductor
the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately
program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain
unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
is no way to disengage security without completely erasing all FLASH locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to
the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to
be compared against the key rather than as the first step in a FLASH program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be done in order starting with the value for NVBACKKEY and ending with
NVBACKKEY+7. STHX should not be used for these writes because these writes cannot be done
on adjacent bus cycles. User software normally would get the key codes from outside the MCU
system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the
key stored in the FLASH locations, SEC01:SEC00 are automatically changed to 1:0 and security
will be disengaged until the next reset.
The security key can be written only from secure memory (either RAM or FLASH), so it cannot be entered
through background commands without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in FLASH memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other FLASH memory location. The nonvolatile registers are in the same 512-byte block of
FLASH as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by taking these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase FLASH if necessary.
3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next
reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
51
4.7
FLASH Registers and Control Bits
The FLASH module has nine 8-bit registers in the high-page register space, two locations (NVOPT,
NVPROT) in the nonvolatile register space in FLASH memory are copied into corresponding high-page
control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory.
Refer to
Table 4-3
and
Table 4-4
for the absolute address assignments for all FLASH registers. This section
refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or
header file normally is used to translate these names into the appropriate absolute addresses.
4.7.1
FLASH Clock Divider Register (FCDIV)
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.
if PRDIV8 = 0 -- f
FCLK
= f
Bus
(DIV + 1)
Eqn. 4-1
if PRDIV8 = 1 -- f
FCLK
= f
Bus
(8 (DIV + 1))
Eqn. 4-2
Table 4-7
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
7
6
5
4
3
2
1
0
R
DIVLD
PRDIV8
DIV
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-5. FLASH Clock Divider Register (FCDIV)
Table 4-6. FCDIV Register Field Descriptions
Field
Description
7
DIVLD
Divisor Loaded Status Flag -- When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
5:0
DIV
Divisor for FLASH Clock Divider -- The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal
FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase
timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5
s to 6.7 s. The
automated programming logic uses an integer number of these pulses to complete an erase or program
operation. See
Equation 4-1
and
Equation 4-2
.
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
52
Freescale Semiconductor
4.7.2
FLASH Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. To
change the value in this register, erase and reprogram the NVOPT location in FLASH memory as usual
and then issue a new MCU reset.
Table 4-7. FLASH Clock Divider Settings
f
Bus
PRDIV8
(Binary)
DIV
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5
s Min, 6.7 s Max)
20 MHz
1
12
192.3 kHz
5.2
s
10 MHz
0
49
200 kHz
5
s
8 MHz
0
39
200 kHz
5
s
4 MHz
0
19
200 kHz
5
s
2 MHz
0
9
200 kHz
5
s
1 MHz
0
4
200 kHz
5
s
200 kHz
0
0
200 kHz
5
s
150 kHz
0
0
150 kHz
6.7
s
7
6
5
4
3
2
1
0
R
KEYEN
FNORED
0
0
0
0
SEC01
SEC00
W
Reset
This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-6. FLASH Options Register (FOPT)
Table 4-8. FOPT Register Field Descriptions
Field
Description
7
KEYEN
Backdoor Key Mechanism Enable -- When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to
Section 4.6, "Security
."
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset.
6
FNORED
Vector Redirection Disable -- When this bit is 1, then vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
1:0
SEC0[1:0]
Security State Code -- This 2-bit field determines the security state of the MCU as shown in
Table 4-9
. When
the MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any
unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful
backdoor key entry or a successful blank check of FLASH.
For more detailed information about security, refer to
Section 4.6, "Security
."
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
53
4.7.3
FLASH Configuration Register (FCNFG)
4.7.4
FLASH Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from FLASH into FPROT. This
register can be read at any time, but user program writes have no meaning or effect.
Figure 4-8. FLASH Protection Register (FPROT)
Table 4-9. Security States
1
1
SEC01:SEC00 changes to 1:0 after successful backdoor
key entry or a successful blank check of FLASH.
SEC01:SEC00
Description
0:0
secure
0:1
secure
1:0
unsecured
1:1
secure
7
6
5
4
3
2
1
0
R
0
0
KEYACC
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-7. FLASH Configuration Register (FCNFG)
Table 4-10. FCNFG Register Field Descriptions
Field
Description
5
KEYACC
Enable Writing of Access Key -- This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to
Section 4.6, "Security
."
0 Writes to 0xFFB00xFFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY (0xFFB00xFFB7) are interpreted as comparison key writes.
7
6
5
4
3
2
1
0
R
FPS
(1)
1
Background commands can be used to change the contents of these bits in FPROT.
FPDIS
(1)
W
Reset
This register is loaded from nonvolatile location NVPROT during reset.
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
54
Freescale Semiconductor
4.7.5
FLASH Status Register (FSTAT)
Table 4-11. FPROT Register Field Descriptions
Field
Description
7:1
FPS
FLASH Protect Select Bits -- When FPDIS = 0, this 7-bit field determines the ending address of unprotected
FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or
programmed.
0
FPDIS
FLASH Protection Disable
0 FLASH block specified by FPS7:FPS1 is block protected (program and erase not allowed).
1 No FLASH block is protected.
7
6
5
4
3
2
1
0
R
FCBEF
FCCF
FPVIOL
FACCERR
0
FBLANK
0
0
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-9. FLASH Status Register (FSTAT)
Table 4-12. FSTAT Register Field Descriptions
Field
Description
7
FCBEF
FLASH Command Buffer Empty Flag -- The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command can be written to the command buffer.
6
FCCF
FLASH Command Complete Flag -- FCCF is set automatically when the command buffer is empty and no
command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
5
FPVIOL
Protection Violation Flag -- FPVIOL is set automatically when FCBEF is cleared to register a command that
attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is
cleared by writing a 1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
55
4.7.6
FLASH Command Register (FCMD)
Only five command codes are recognized in normal user modes as shown in
Table 4-13
. Refer to
Section 4.5.3, "Program and Erase Command Execution
," for a detailed discussion of FLASH
programming and erase operations.
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
4
FACCERR
Access Error Flag -- FACCERR is set automatically when the proper command sequence is not obeyed exactly
(the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has
been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of
the exact actions that are considered access errors, see
Section 4.5.5, "Access Errors
." FACCERR is cleared by
writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error.
1 An access error has occurred.
2
FBLANK
FLASH Verified as All Blank (erased) Flag -- FBLANK is set automatically at the conclusion of a blank check
command if the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a
new valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is
completely erased (all 0xFF).
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
FCMD
Reset
0
0
0
0
0
0
0
0
Figure 4-10. FLASH Command Register (FCMD)
Table 4-13. FLASH Commands
Command
FCMD
Equate File Label
Blank check
0x05
mBlank
Byte program
0x20
mByteProg
Byte program -- burst mode
0x25
mBurstProg
Page erase (512 bytes/page)
0x40
mPageErase
Mass erase (all FLASH)
0x41
mMassErase
Table 4-12. FSTAT Register Field Descriptions (continued)
Field
Description
Chapter 4 Memory Map and Register Definition
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
57
Chapter 5
Resets, Interrupts, and General System Control
5.1
Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08QG8/4. Some interrupt sources from peripheral modules are discussed in greater detail
within other sections of this data sheet. This section gathers basic information about all reset and interrupt
sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own chapters but are part of the system control logic.
5.2
Features
Reset and interrupt features include:
Multiple sources of reset for flexible system configuration and reliable operation
Reset status register (SRS) to indicate source of most recent reset
Separate interrupt vectors for each module (reduces polling overhead) (see
Table 5-2
)
5.3
MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose, high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08QG8/4 has the following sources for reset:
External pin reset (PIN) -- enabled using RSTPE in SOPT1
Power-on reset (POR)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect (ILOP)
Illegal address detect (ILAD)
Background debug force reset
Each of these sources, with the exception of the background debug force reset, has an associated bit in the
system reset status register.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Freescale Semiconductor
5.4
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT1 enabling the COP watchdog (see
Section 5.8.4, "System
Options Register 1 (SOPT1)
," for additional information). If the COP watchdog is not used in an
application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the
address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this
address is decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see
Section 5.8.5, "System Options Register 2 (SOPT2)
," for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1-kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT1.
Table 5-1
summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the associated long
time-out (2
8
cycles).
Even if the application will use the reset default settings of COPE, COPCLKS, and COPT, the user must
write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT1
and SOPT2 will reset the COP counter.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
In background debug mode, the COP counter will not increment.
When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes as soon as the MCU exits stop mode.
Table 5-1. COP Configuration Options
Control Bits
Clock Source
COP Overflow Count
COPCLKS
COPT
0
0
~1 kHz
2
5
cycles (32 ms)
1
1
Values are shown in this column based on t
RTI
= 1 ms. See t
RTI
in the appendix
Section A.8.1, "Control Timing
," for the tolerance of this value.
0
1
~1 kHz
2
8
cycles (256 ms)
1
1
0
Bus
2
13
cycles
1
1
Bus
2
18
cycles
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
59
When the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to stop mode.
The COP counter begins from zero after the MCU exits stop mode.
5.5
Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than
the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such
as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI under
certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is a 1 to enable the interrupt. The I bit in
the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset,
which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and
performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and
consists of:
Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit can be cleared
inside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be
serviced without waiting for the first service routine to finish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difficult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the
stack.
NOTE
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced
first (see
Table 5-2
).
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
60
Freescale Semiconductor
5.5.1
Interrupt Stack Frame
Figure 5-1
shows the content and organization of a stack frame. Before the interrupt, the stack pointer (SP)
points at the next available byte location on the stack. The current values of CPU registers are stored on
the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack, which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this
same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2
External Interrupt Request Pin (IRQ)
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1
Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 for the IRQ pin to act as the interrupt request
(IRQ) input. As an IRQ input, the user can choose whether the pin detects edges-only or edges and levels
(IRQMOD), and whether an event causes an interrupt or only sets the IRQF flag, which can be polled by
software.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
* High byte (H) of index register is not automatically stacked.
*
PROGRAM COUNTER LOW
7
0
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
61
The IRQ pin, when enabled, defaults to use an internal pullup device (IRQPDD = 0). If the user desires to
use an external pullup, the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
NOTE
This pin does not contain a clamp diode to V
DD
and should not be driven
above V
DD
.
The voltage measured on the internally pulled up IRQ pin will not be pulled
to V
DD
. The internal gates connected to this pin are pulled to V
DD
. The IRQ
pullup should not be used to pull up components external to the MCU. The
internal gates connected to this pin are pulled all the way to V
DD
.
5.5.2.2
Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3
Interrupt Vectors, Sources, and Local Masks
Table 5-2
provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
62
Freescale Semiconductor
Table 5-2. Vector Summary
Vector
Priority
Vector
Number
Address
(High:Low)
Vector
Name
Module
Source
Enable
Description
Lower
Higher
31
through
24
0xFFC0:FFC1
through
0xFFCE:FFCF
Unused Vector Space
(available for user program)
23
0xFFD0:FFD1
Vrti
System
control
RTIF
RTIE
Real-time interrupt
22
0xFFD2:FFD3
--
--
--
--
--
21
0xFFD4:FFD5
--
--
--
--
--
20
0xFFD6:FFD7
Vacmp
ACMP
ACF
ACIE
ACMP
19
0xFFD8:FFD9
Vadc
ADC
COCO
AIEN
ADC
18
0xFFDA:FFDB
Vkeyboard
KBI
KBF
KBIE
Keyboard pins
17
0xFFDC:FFDD
Viic
IIC
IICIF
IICIE
IIC control
16
0xFFDE:FFDF
Vscitx
SCI
TDRE
TC
TIE
TCIE
SCI transmit
15
0xFFE0:FFE1
Vscirx
SCI
IDLE
RDRF
ILIE
RIE
SCI receive
14
0xFFE2:FFE3
Vscierr
SCI
OR
NF
FE
PF
ORIE
NFIE
FEIE
PFIE
SCI error
13
0xFFE4:FFE5
Vspi
SPI
SPIF
MODF
SPTEF
SPIE
SPIE
SPTIE
SPI
12
0xFFE6:FFE7
Vmtim
MTIM
TOF
TOIE
MTIM
11
0xFFE8:FFE9
--
--
--
--
--
10
0xFFEA:FFEB
--
--
--
--
--
9
0xFFEC:FFED
--
--
--
--
--
8
0xFFEE:FFEF
--
--
--
--
--
7
0xFFF0:FFF1
Vtpmovf
TPM
TOF
TOIE
TPM overflow
6
0xFFF2:FFF3
Vtpmch1
TPM
CH1F
CH1IE
TPM channel 1
5
0xFFF4:FFF5
Vtpmch0
TPM
CH0F
CH0IE
TPM channel 0
4
0xFFF6:FFF7
--
--
--
--
--
3
0xFFF8:FFF9
Vlvd
System
control
LVDF
LVDIE
Low-voltage detect
2
0xFFFA:FFFB
Virq
IRQ
IRQF
IRQIE
IRQ pin
1
0xFFFC:FFFD
Vswi
CPU
SWI
Instruction
--
Software interrupt
0
0xFFFE:FFFF
Vreset
System
control
COP
LVD
RESET pin
Illegal opcode
Illegal address
POR
COPE
LVDRE
RSTPE
--
--
--
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
Illegal address
power-on-reset
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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63
5.6
Low-Voltage Detect (LVD) System
The MC9S08QG8/4 includes a system to protect against low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system is comprised of a
power-on reset (POR) circuit and a LVD circuit with a user selectable trip voltage, either high (V
LVDH
) or
low (V
LVDL
). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected
by LVDV in SPMSC3. The LVD is disabled upon entering any of the stop modes unless LVDSE is set in
SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current
consumption in stop3 with the LVD enabled will be greater.
5.6.1
Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR
level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU
in reset until the supply has risen above the V
LVDL
level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur.
5.6.4
Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is above, the LVD voltage. The LVW does not have an interrupt associated with it. There
are two user selectable trip voltages for the LVW, one high (V
LVWH
) and one low (V
LVWL
). The trip
voltage is selected by LVWV in SPMSC3.
5.7
Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two
sources of clocks, the 1-kHz internal clock or an external clock if available. External clock input requires
the XOSC module, consult
Table 1-1
to see if your MCU contains this module. The RTICLKS bit in
SRTISC is used to select the RTI clock source.
Either RTI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external
oscillator in stop3, it must be enabled in stop (EREFSTEN = 1) and configured for low frequency operation
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Freescale Semiconductor
(RANGE = 0). Only the internal 1-kHz clock source can be selected to wake the MCU from stop1 or stop2
modes.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS) used to select one of seven wakeup periods. The RTI has a local interrupt enable, RTIE, to
allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to 0s, and
no interrupts will be generated. See
Section 5.8.7, "System Real-Time Interrupt Status and Control
Register (SRTISC)
," for detailed information about this register.
5.8
Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in
Chapter 4, "Memory Map and Register Definition
," for the
absolute address assignments for all registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
Some control bits in the SOPT1, SOPT2, and SPMSC2 registers are related to modes of operation.
Although brief descriptions of these bits are provided here, the related functions are discussed in greater
detail in
Chapter 3, "Modes of Operation
."
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
65
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits, which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
7
6
5
1
1
Bit 5 is a reserved bit that must always be written to 0.
4
3
2
1
0
R
0
IRQPDD
0
IRQPE
IRQF
0
IRQIE
IRQMOD
W
IRQACK
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-3. IRQSC Register Field Descriptions
Field
Description
6
IRQPDD
Interrupt Request (IRQ) Pull Device Disable -- This read/write control bit is used to disable the internal pullup
device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
4
IRQPE
IRQ Pin Enable -- This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3
IRQF
IRQ Flag -- This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
2
IRQACK
IRQ Acknowledge -- This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE
IRQ Interrupt Enable -- This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
0
IRQMOD
IRQ Detection Mode -- This read/write control bit selects either edge-only detection or edge-and-level
detection. See
Section 5.5.2.2, "Edge and Level Sensitivity
," for more details.
0 IRQ event on falling edges only.
1 IRQ event on falling edges and low levels.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
66
Freescale Semiconductor
5.8.2
System Reset Status Register (SRS)
This high page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, all of the status bits in SRS will be
cleared. Writing any value to this register address clears the COP watchdog timer without affecting the
contents of this register. The reset state of these bits depends on what caused the MCU to reset.
7
6
5
4
3
2
1
0
R
POR
PIN
COP
ILOP
ILAD
0
LVD
0
W
Writing any value to SRS address clears COP watchdog timer.
POR:
1
0
0
0
0
0
1
0
LVR:
u
(1)
1
u = unaffected
0
0
0
0
0
1
0
Any other
reset:
0
Note
(2)
2
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
Note
(2)
Note
(2)
Note
(2)
0
0
0
Figure 5-3. System Reset Status (SRS)
Table 5-4. SRS Register Field Descriptions
Field
Description
7
POR
Power-On Reset -- Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin -- Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
COP
Computer Operating Properly (COP) Watchdog -- Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode -- Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
ILAD
Illegal Address -- Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
1
LVD
Low Voltage Detect -- If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
67
5.8.3
System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR
1
1
BDFR is writable only through serial background debug commands, not from user programs.
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-5. SBDFR Register Field Descriptions
Field
Description
0
BDFR
Background Debug Force Reset -- A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/ACMPO/BKGD/MS must be high immediately after
issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing
WRITE_BYTE command. See
Table A-8., "Control Timing
," for more information.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
68
Freescale Semiconductor
5.8.4
System Options Register 1 (SOPT1)
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 must be written during the user reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7
6
5
4
1
1
Bit 4 is reserved, writes will change the value but will have no effect on this MCU.
3
2
1
0
R
COPE
COPT
STOPE
0
0
BKGDPE
RSTPE
W
Reset:
1
1
0
1
0
0
1
u
(2)
2
u = unaffected
POR:
1
1
0
1
0
0
1
0
LVR:
1
1
0
1
0
0
1
0
= Unimplemented or Reserved
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-6. SOPT1 Register Field Descriptions
Field
Description
7
COPE
COP Watchdog Enable -- This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout -- This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable -- This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE
Background Debug Mode Pin Enable -- This write-once bit when set enables the PTA4/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA4/ACMPO/BKGD/MS pin functions as PTA4 or ACMPO.
1 PTA4/ACMPO/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
RESET Pin Enable -- This write-once bit when set enables the PTA5/IRQ/TCLK/RESET pin to function as
RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its
input-only port function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on
RESET.
0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ or TCLK.
1 PTA5/IRQ/TCLK/RESET pin functions as RESET.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
69
5.8.5
System Options Register 2 (SOPT2)
This high page register contains bits to configure MCU specific features on the MC9S08QG8/4 devices.
7
6
5
4
3
2
1
0
R
COPCLKS
1
1
This bit can be written only one time after reset. Additional writes are ignored.
0
0
0
0
0
IICPS
ACIC
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field
Description
7
COPCLKS
COP Watchdog Clock Select -- This write-once bit selects the clock source of the COP watchdog.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
1
IICPS
IIC Pin Select-- This bit selects the location of the SDA and SCL pins of the IIC module.
0 SDA on PTA2, SCL on PTA3.
1 SDA on PTB6, SCL on PTB7.
0
ACIC
Analog Comparator to Input Capture Enable-- This bit connects the output of ACMP to TPM input channel 0.
0 ACMP output not connected to TPM input channel 0.
1 ACMP output connected to TPM input channel 0.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
70
Freescale Semiconductor
5.8.6
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the HCS08
derivative and revision number. This allows the development software to recognize where specific memory
blocks, registers, and control bits are located in a target MCU.
Figure 5-7. System Device Identification Register -- High (SDIDH)
7
6
5
4
3
2
1
0
R
ID11
ID10
ID9
ID8
W
Reset:
--
--
--
--
0
0
0
0
= Unimplemented or Reserved
Table 5-8. SDIDH Register Field Descriptions
Field
Description
7:4
Reserved
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
3:0
ID[11:8]
Part Identification Number -- Each derivative in the HCS08 Family has a unique identification number. The
MC9S08QG8 is hard coded to the value 0x009. See also ID bits in
Table 5-9
.
7
6
5
4
3
2
1
0
R
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
W
Reset:
0
0
0
0
1
0
0
1
= Unimplemented or Reserved
Figure 5-8. System Device Identification Register -- Low (SDIDL)
Table 5-9. SDIDL Register Field Descriptions
Field
Description
7:0
ID[7:0]
Part Identification Number -- Each derivative in the HCS08 Family has a unique identification number. The
MC9S08QG8 is hard coded to the value 0x009. See also ID bits in
Table 5-8
.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
71
5.8.7
System Real-Time Interrupt Status and Control Register (SRTISC)
This high page register contains status and control bits for the RTI.
7
6
5
4
3
2
1
0
R
RTIF
0
RTICLKS
RTIE
0
RTIS
W
RTIACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-9. System RTI Status and Control Register (SRTISC)
Table 5-10. SRTISC Register Field Descriptions
Field
Description
7
RTIF
Real-Time Interrupt Flag -- This read-only status bit indicates the periodic wakeup timer has timed out.
0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
6
RTIACK
Real-Time Interrupt Acknowledge -- This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.
5
RTICLKS
Real-Time Interrupt Clock Select -- This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal 1-kHz oscillator.
1 Real-time interrupt request clock source is external clock.
4
RTIE
Real-Time Interrupt Enable -- This read-write bit enables real-time interrupts.
0 Real-time interrupts disabled.
1 Real-time interrupts enabled.
2:0
RTIS
Real-Time Interrupt Delay Selects -- These read/write bits select the period for the RTI. See
Table 5-11
.
Table 5-11. Real-Time Interrupt Period
RTIS2:RTIS1:RTIS0
Using Internal 1-kHz Clock Source
1 2
1
Values are shown in this column based on t
RTI
= 1 ms. See t
RTI
in the appendix
Section A.8.1, "Control Timing
," for the
tolerance of this value.
2
The initial RTI timeout period will be up to one 1-kHz clock period less than the time specified.
Using External Clock Source
Period = t
ext
3
3
t
ext
is the period of the external crystal frequency.
0:0:0
Disable RTI
Disable RTI
0:0:1
8 ms
t
ext
x 256
0:1:0
32 ms
t
ext
x 1024
0:1:1
64 ms
t
ext
x 2048
1:0:0
128 ms
t
ext
x 4096
1:0:1
256 ms
t
ext
x 8192
1:1:0
512 ms
t
ext
x 16384
1:1:1
1.024 s
t
ext
x 32768
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
72
Freescale Semiconductor
5.8.8
System Power Management Status and Control 1 Register
(SPMSC1)
This high page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip
voltage, see
Table 5-14
for the LVDV bit description in SPMSC3.
7
6
5
4
3
2
1
1
1
Bit 1 is a reserved bit that must always be written to 0.
0
R
LVDF
0
LVDIE
LVDRE
2
2
This bit can be written only one time after reset. Additional writes are ignored.
LVDSE
LVDE
2
0
BGBE
W
LVDACK
Reset:
0
0
0
1
1
1
0
0
= Unimplemented or Reserved
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-12. SPMSC1 Register Field Descriptions
Field
Description
7
LVDF
Low-Voltage Detect Flag -- Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge -- This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable -- This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable -- This write-once bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3
LVDSE
Low-Voltage Detect Stop Enable -- Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable -- This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable -- This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC module on one of its internal channels or as a voltage reference for ACMP module.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
73
5.8.9
System Power Management Status and Control 2 Register
(SPMSC2)
This high page register contains status and control bits to configure the stop mode behavior of the MCU.
See
Section 3.6, "Stop Modes
," for more information on stop modes.
7
6
5
4
3
2
1
0
R
0
0
0
PDF
PPDF
0
PDC
1
1
This bit can be written only one time after reset. Additional writes are ignored.
PPDC
1
W
PPDACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-13. SPMSC2 Register Field Descriptions
Field
Description
4
PDF
Power Down Flag -- This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
3
PPDF
Partial Power Down Flag -- This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
2
PPDACK
Partial Power Down Acknowledge -- Writing a 1 to PPDACK clears the PPDF and the PDF bits.
1
PDC
Power Down Control -- The PDC bit controls entry into the power down (stop2 and stop1) modes
0 Power down modes are disabled.
1 Power down modes are enabled.
0
PPDC
Partial Power Down Control -- The PPDC bit controls which power down mode is selected.
0 Stop1 full power down mode enabled if PDC set.
1 Stop2 partial power down mode enabled if PDC set.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
74
Freescale Semiconductor
5.8.10
System Power Management Status and Control 3 Register
(SPMSC3)
This high page register is used to report the status of the low voltage warning function and to select the low
voltage detect trip voltage.
7
6
5
4
3
2
1
0
R
LVWF
0
LVDV
LVWV
0
0
0
0
W
LVWACK
POR:
0
1
1
LVWF will be set in the case when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
.
0
0
0
0
0
0
0
LVR:
0
1
0
U
U
0
0
0
0
Any other
reset:
0
1
0
U
U
0
0
0
0
= Unimplemented or Reserved
U= Unaffected by reset
Figure 5-12. System Power Management Status and Control 3 Register (SPMSC3)
Table 5-14. SPMSC3 Register Field Descriptions
Field
Description
7
LVWF
Low-Voltage Warning Flag -- The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge -- The LVWF bit indicates the low voltage warning status. Writing a 1 to
LVWACK clears LVWF to a 0 if a low voltage warning is not present.
5
LVDV
Low-Voltage Detect Voltage Select -- The LVDV bit selects the LVD trip point voltage (V
LVD
).
0 Low trip point selected (V
LVD
= V
LVDL
).
1 High trip point selected (V
LVD
= V
LVDH
).
4
LVWV
Low-Voltage Warning Voltage Select -- The LVWV bit selects the LVW trip point voltage (V
LVW
).
0 Low trip point selected (V
LVW
= V
LVWL
).
1 High trip point selected (V
LVW
= V
LVWH
).
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
75
Chapter 6
Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08QG8 has two parallel I/O ports which include a total of 12 I/O pins, one output-only pin and one
input-only pin. See
Section Chapter 2, "External Signal Description
," for more information about pin
assignments and external hardware considerations of these pins. Not all pins are available on all devices
of the MC9S08QG8/4 Family, consult
Table 1-1
for the number of general-purpose pins available on your
device.
All of these I/O pins are shared with on-chip peripheral functions as shown in
Table 2-2
. The peripheral
modules have priority over the I/Os so that when a peripheral is enabled, the I/O functions associated with
the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are
controlled by the I/O. All of the I/Os are configured as inputs (PTxDDn = 0) with pullup devices disabled
(PTxPEn = 0), except for output-only pin PTA4 which defaults to BKGD/MS pin.
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unconnected pins to outputs so the pins do not
float.
6.1
Port Data and Data Direction
Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input
or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in
Figure 6-1
.
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
76
Freescale Semiconductor
Figure 6-1. Parallel I/O Block Diagram
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled.
In general, whenever a pin is shared with both an alternate digital function and an analog function, the
analog function has priority such that if both the digital and analog functions are enabled, the analog
function controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.2
Pin Control -- Pullup, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pullups, slew rate and drive
strength for the pins.
Q
D
Q
D
1
0
Port Read
PTxDDn
PTxDn
Output Enable
Output Data
Input Data
Synchronizer
Data
BUSCLK
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
77
6.3
Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
In stop1 mode, all internal registers including parallel I/O control and data registers are powered
off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled).
Upon exit from stop1, all pins must be re-configured the same as if the MCU had been reset by
POR.
Stop2 mode is a partial power-down mode, whereby latches maintain the pin state as before the
STOP instruction was executed. CPU register status and the state of I/O registers must be saved in
RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery
from stop2 mode, before accessing any I/O, the user must examine the state of the PPDF bit in the
SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had occurred.
If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was executed,
peripherals previously enabled will require being initialized and restored to their pre-stop
condition. The user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access of pins
is now permitted again in the user application program.
In stop3 mode, all pin states are maintained because internal logic stays powered up. Upon
recovery, all pin functions are the same as before entering stop3.
6.4
Parallel I/O Registers
6.4.1
Port A Registers
This section provides information about the registers associated with the parallel I/O ports.
Refer to tables in
Chapter 4, "Memory Map and Register Definition
," for the absolute address assignments
for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.4.1.1
Port A Data (PTAD)
7
6
5
4
3
2
1
0
R
0
0
PTAD5
1
1
Reads of bit PTAD5 always return the pin value of PTA5, regardless of the value stored in bit PTADD5.
PTAD4
2
2
Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.
PTAD3
PTAD2
PTAD1
PTAD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-2. Port A Data Register (PTAD)
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Freescale Semiconductor
6.4.1.2
Port A Data Direction (PTADD)
6.4.2
Port A Control Registers
The pins associated with port A are controlled by the registers in this section. These registers control the
pin pullup, slew rate, and drive strength of the port A pins independent of the parallel I/O register.
Table 6-1. PTAD Register Field Descriptions
Field
Description
5:0
PTAD[5:0]
Port A Data Register Bits -- For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
6
5
4
3
2
1
0
R
0
0
PTADD5
1
1
PTADD5 has no effect on the input-only PTA5 pin.
PTADD4
2
2
PTADD4 has no effect on the output-only PTA4 pin.
PTADD3
PTADD2
PTADD1
PTADD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-3. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field
Description
5:0
PTADD[5:0]
Data Direction for Port A Bits -- These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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79
6.4.2.1
Port A Internal Pullup Enable (PTAPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.4.2.2
Port A Slew Rate Enable (PTASE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTASEn). When enabled, slew control limits the rate at which an output can transition to reduce
EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
7
6
5
4
3
2
1
0
R
0
0
PTAPE5
PTAPE4
1
1
PTAPE4 has no effect on the output-only PTA4 pin.
PTAPE3
PTAPE2
PTAPE1
PTAPE0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-4. Internal Pullup Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
Field
Description
5:0
PTAPE[5:0]
Internal Pullup Enable for Port A Bits -- Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
7
6
5
4
3
2
1
0
R
0
0
PTASE5
1
1
PTASE5 has no effect on the input-only PTA5 pin.
PTASE4
PTASE3
PTASE2
PTASE1
PTASE0
W
Reset:
0
0
1
1
1
1
1
1
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field
Description
5:0
PTASE[5:0]
Output Slew Rate Enable for Port A Bits -- Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
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MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Freescale Semiconductor
6.4.2.3
Port A Drive Strength Select (PTADS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTADS). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
6.4.2.4
Port A Drive Strength Select (PTADS)
7
6
5
4
3
2
1
0
R
0
0
PTADS5
1
1
PTADS5 has no effect on the input-only PTA5 pin.
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-8. Drive Strength Selection for Port A Register (PTADS)
Table 6-5. PTADS Register Field Descriptions
Field
Description
5:0
PTADS[5:0]
Output Drive Strength Selection for Port A Bits -- Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
81
6.4.3
Port B Registers
This section provides information about the registers associated with the parallel I/O ports.
Refer to tables in
Chapter 4, "Memory Map and Register Definition
," for the absolute address assignments
for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.4.3.1
Port B Data (PTBD)
6.4.3.2
Port B Data Direction (PTBDD)
7
6
5
4
3
2
1
0
R
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-10. Port B Data Register (PTBD)
Table 6-6. PTBD Register Field Descriptions
Field
Description
7:0
PTBD[7:0]
Port B Data Register Bits -- For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
6
5
4
3
2
1
0
R
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-11. Data Direction for Port B (PTBDD)
Table 6-7. PTBDD Register Field Descriptions
Field
Description
7:0
PTBDD[7:0]
Data Direction for Port B Bits -- These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.
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MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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Freescale Semiconductor
6.4.4
Port B Control Registers
The pins associated with port B are controlled by the registers in this section. These registers control the
pin pullup, slew rate and drive strength of the port B pins independent of the parallel I/O register.
6.4.4.1
Port B Internal Pullup Enable (PTBPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTBPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.4.4.2
Port B Slew Rate Enable (PTBSE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTBSEn). When enabled, slew control limits the rate at which an output can transition in order
to reduce EMC emissions. Slew rate control has no effect on pins which are configured as input.
7
6
5
4
3
2
1
0
R
PTBPE7
PTBPE6
PTBPE5
PTBPE4
PTBPE3
PTBPE2
PTBPE1
PTBPE0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-12. Internal Pullup Enable for Port B Register (PTBPE)
Table 6-8. PTBPE Register Field Descriptions
Field
Description
7:0
PTBPE[7:0]
Internal Pullup Enable for Port B Bits -- Each of these control bits determines if the internal pullup device is
enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port B bit n.
1 Internal pullup device enabled for port B bit n.
7
6
5
4
3
2
1
0
R
PTBSE7
PTBSE6
PTBSE5
PTBSE4
PTBSE3
PTBSE2
PTBSE1
PTBSE0
W
Reset:
1
1
1
1
1
1
1
1
Figure 6-14. Slew Rate Enable for Port B Register (PTBSE)
Table 6-9. PTBSE Register Field Descriptions
Field
Description
7:0
PTBSE[7:0]
Output Slew Rate Enable for Port B Bits -- Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port B bit n.
1 Output slew rate control enabled for port B bit n.
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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83
6.4.4.3
Port B Drive Strength Select (PTBDS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTBDSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
7
6
5
4
3
2
1
0
R
PTBDS7
PTBDS6
PTBDS5
PTBDS4
PTBDS3
PTBDS2
PTBDS1
PTBDS0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-16. Drive Strength Selection for Port B Register (PTBDS)
Table 6-10. PTBDS Register Field Descriptions
Field
Description
7:0
PTBDS[7:0]
Output Drive Strength Selection for Port B Bits -- Each of these control bits selects between low and high
output drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.
Chapter 6 Parallel Input/Output Control
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
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85
Chapter 7
Central Processor Unit (S08CPUV2)
7.1
Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
7.1.1
Features
Features of the HCS08 CPU include:
Object code fully upward-compatible with M68HC05 and M68HC08 Families
All registers and memory are mapped to a single 64-Kbyte address space
16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
-- Inherent -- Operands in internal registers
-- Relative -- 8-bit signed offset to branch destination
-- Immediate -- Operand in next object code byte(s)
-- Direct -- Operand in memory at 0x00000x00FF
-- Extended -- Operand anywhere in 64-Kbyte address space
-- Indexed relative to H:X -- Five submodes including auto increment
-- Indexed relative to SP -- Improves C efficiency dramatically
Memory-to-memory data move instructions with four address mode combinations
Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
Efficient bit manipulation instructions
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
STOP and WAIT instructions to invoke low-power operating modes
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7.2
Programmer's Model and CPU Registers
Figure 7-1
shows the five CPU registers. CPU registers are not part of the memory map.
Figure 7-1. CPU Registers
7.2.1
Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.
7.2.2
Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.
SP
PC
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO'S COMPLEMENT OVERFLOW
H
X
0
0
0
7
15
15
7
0
ACCUMULATOR
A
INDEX REGISTER (LOW)
INDEX REGISTER (HIGH)
STACK POINTER
8
7
PROGRAM COUNTER
16-BIT INDEX REGISTER H:X
CCR
C
V 1 1 H
I
N Z
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7.2.3
Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
7.2.4
Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at $FFFE and $FFFF. The
vector stored there is the address of the first instruction that will be executed after exiting the reset state.
7.2.5
Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1/D.
Figure 7-2. Condition Code Register
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO'S COMPLEMENT OVERFLOW
7
0
CCR
C
V 1 1 H
I
N Z
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7.3
Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
Table 7-1. CCR Register Field Descriptions
Field
Description
7
V
Two's Complement Overflow Flag -- The CPU sets the overflow flag when a two's complement overflow occurs.
The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1 Overflow
4
H
Half-Carry Flag -- The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit -- When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag -- The CPU sets the negative flag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
1
Z
Zero Flag -- The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
0
C
Carry/Borrow Flag -- The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and
branch, shift, and rotate -- also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7
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of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
7.3.1
Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
7.3.2
Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
7.3.3
Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.
7.3.4
Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x00000x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
7.3.5
Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
7.3.6
Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.
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7.3.6.1
Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
7.3.6.2
Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
7.3.6.3
Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.4
Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
7.3.6.5
Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6
SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.7
SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.4
Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
91
7.4.1
Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the
Resets, Interrupts, and System Configuration
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
7.4.2
Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine
does not use any instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
92
Freescale Semiconductor
7.4.3
Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.
7.4.4
Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the
Modes of Operation
chapter for more details.
7.4.5
BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background
mode rather than continuing the user program.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
93
7.5
HCS08 Instruction Set Summary
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in
Table 7-2
.
Operators
( )
=
Contents of register or memory location shown inside parentheses
= Is loaded with (read: "gets")
&
=
Boolean AND
|
=
Boolean OR
= Boolean exclusive-OR
= Multiply
= Divide
:
=
Concatenate
+
=
Add
=
Negate (two's complement)
CPU registers
A
=
Accumulator
CCR
=
Condition code register
H
=
Index register, higher order (most significant) 8 bits
X
=
Index register, lower order (least significant) 8 bits
PC
=
Program counter
PCH
=
Program counter, higher order (most significant) 8 bits
PCL
=
Program counter, lower order (least significant) 8 bits
SP
=
Stack pointer
Memory and addressing
M
=
A memory location or absolute data, depending on addressing mode
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
Condition code register (CCR) bits
V
=
Two's complement overflow indicator, bit 7
H
=
Half carry, bit 4
I
=
Interrupt mask, bit 3
N
=
Negative indicator, bit 2
Z
=
Zero indicator, bit 1
C
=
Carry/borrow, bit 0 (carry out of bit 7)
CCR activity notation
=
Bit not affected
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
94
Freescale Semiconductor
0
=
Bit forced to 0
1
=
Bit forced to 1
=
Bit set or cleared according to results of operation
U
=
Undefined after the operation
Machine coding notation
dd
=
Low-order 8 bits of a direct address 0x00000x00FF (high byte assumed to be 0x00)
ee
=
Upper 8 bits of 16-bit offset
ff
=
Lower 8 bits of 16-bit offset or 8-bit offset
ii
=
One byte of immediate data
jj
=
High-order byte of a 16-bit immediate data value
kk
=
Low-order byte of a 16-bit immediate data value
hh
=
High-order byte of 16-bit extended address
ll
=
Low-order byte of 16-bit extended address
rr
=
Relative offset
Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that
must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a
literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.
n
--
Any label or expression that evaluates to a single integer in the range 07
opr8i
--
Any label or expression that evaluates to an 8-bit immediate value
opr16i
--
Any label or expression that evaluates to a 16-bit immediate value
opr8a
--
Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit
value as the low order 8 bits of an address in the direct page of the 64-Kbyte address
space (0x00xx).
opr16a
--
Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8
--
Any label or expression that evaluates to an unsigned 8-bit value, used for indexed
addressing
oprx16
--
Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a
16-bit address bus, this can be either a signed or an unsigned value.
rel
--
Any label or expression that refers to an address that is within 128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.
Address modes
INH
=
Inherent (no operands)
IMM
=
8-bit or 16-bit immediate
DIR
=
8-bit direct
EXT
=
16-bit extended
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
95
IX
=
16-bit indexed no offset
IX+
=
16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1
=
16-bit indexed with 8-bit offset from H:X
IX1+
=
16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX2
=
16-bit indexed with 16-bit offset from H:X
REL
=
8-bit relative offset
SP1
=
Stack pointer with 8-bit offset
SP2
=
Stack pointer with 16-bit offset
Table 7-2. HCS08 Instruction Set Summary (Sheet 1 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
Add with Carry
A
(A) + (M) + (C)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A9
B9
C9
D9
E9
F9
9ED9
9EE9
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
Add without Carry
A
(A) + (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AB
BB
CB
DB
EB
FB
9EDB
9EEB
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
AIS #opr8i
Add Immediate Value
(Signed) to Stack Pointer
SP
(SP) + (M)
M is sign extended to a 16-bit value
IMM
A7 ii
2
AIX #opr8i
Add Immediate Value
(Signed) to Index
Register (H:X)
H:X
(H:X) + (M)
M is sign extended to a 16-bit value
IMM
AF ii
2
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Logical AND
A
(A) & (M)
0
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A4
B4
C4
D4
E4
F4
9ED4
9EE4
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL)
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
5
1
1
5
4
6
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
5
1
1
5
4
6
BCC rel
Branch if Carry Bit Clear
Branch if (C) = 0
REL
24 rr
3
C
b0
b7
0
b0
b7
C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
96
Freescale Semiconductor
BCLR n,opr8a
Clear Bit n in Memory
Mn
0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BCS rel
Branch if Carry Bit Set
(Same as BLO)
Branch if (C) = 1
REL
25 rr
3
BEQ rel
Branch if Equal
Branch if (Z) = 1
REL
27 rr
3
BGE rel
Branch if Greater Than or
Equal To
(Signed Operands)
Branch if (N
V) = 0
REL
90 rr
3
BGND
Enter Active Background
if ENBDM = 1
Waits For and Processes BDM
Commands Until GO, TRACE1, or
TAGGO
INH
82
5+
BGT rel
Branch if Greater Than
(Signed Operands)
Branch if (Z) | (N
V) = 0
REL
92 rr
3
BHCC rel
Branch if Half Carry Bit
Clear
Branch if (H) = 0
REL
28 rr
3
BHCS rel
Branch if Half Carry Bit
Set
Branch if (H) = 1
REL
29 rr
3
BHI rel
Branch if Higher
Branch if (C) | (Z) = 0
REL
22 rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
Branch if (C) = 0
REL
24 rr
3
BIH rel
Branch if IRQ Pin High
Branch if IRQ pin = 1
REL
2F rr
3
BIL rel
Branch if IRQ Pin Low
Branch if IRQ pin = 0
REL
2E rr
3
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test
(A) & (M)
(CCR Updated but Operands
Not Changed)
0
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9ED5
9EE5
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
BLE rel
Branch if Less Than
or Equal To
(Signed Operands)
Branch if (Z) | (N
V) = 1
REL
93 rr
3
BLO rel
Branch if Lower
(Same as BCS)
Branch if (C) = 1
REL
25 rr
3
BLS rel
Branch if Lower or Same
Branch if (C) | (Z) = 1
REL
23 rr
3
BLT rel
Branch if Less Than
(Signed Operands)
Branch if (N
V ) = 1
REL
91 rr
3
BMC rel
Branch if Interrupt Mask
Clear
Branch if (I) = 0
REL
2C rr
3
BMI rel
Branch if Minus
Branch if (N) = 1
REL
2B rr
3
BMS rel
Branch if Interrupt Mask
Set
Branch if (I) = 1
REL
2D rr
3
BNE rel
Branch if Not Equal
Branch if (Z) = 0
REL
26 rr
3
BPL rel
Branch if Plus
Branch if (N) = 0
REL
2A rr
3
BRA rel
Branch Always
No Test
REL
20 rr
3
Table 7-2. HCS08 Instruction Set Summary (Sheet 2 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
97
BRCLR n,opr8a,rel
Branch if Bit n in Memory
Clear
Branch if (Mn) = 0
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel
Branch Never
Uses 3 Bus Cycles
REL
21 rr
3
BRSET n,opr8a,rel
Branch if Bit n in Memory
Set
Branch if (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr8a
Set Bit n in Memory
Mn
1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BSR rel
Branch to Subroutine
PC
(PC) + 0x0002
push (PCL); SP
(SP) 0x0001
push (PCH); SP
(SP) 0x0001
PC
(PC) + rel
REL
AD rr
5
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and Branch if
Equal
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii
rr
ii
rr
ff
rr
rr
ff
rr
5
4
4
5
5
6
CLC
Clear Carry Bit
C
0
0
INH
98
1
CLI
Clear Interrupt Mask Bit
I
0
0
INH
9A
1
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear
M
0x00
A
0x00
X
0x00
H
0x00
M
0x00
M
0x00
M
0x00
0 0 1
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
5
1
1
1
5
4
6
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator
with Memory
(A) (M)
(CCR Updated But Operands Not
Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9ED1
9EE1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
(One's Complement)
M
(M)= 0xFF (M)
A
(A) = 0xFF (A)
X
(X) = 0xFF (X)
M
(M) = 0xFF (M)
M
(M) = 0xFF (M)
M
(M) = 0xFF (M)
0
1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
5
1
1
5
4
6
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Compare Index Register
(H:X) with Memory
(H:X) (M:M + 0x0001)
(CCR Updated But Operands Not
Changed)
EXT
IMM
DIR
SP1
3E
65
75
9EF3
hh ll
jj
kk
dd
ff
6
3
5
6
Table 7-2. HCS08 Instruction Set Summary (Sheet 3 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
98
Freescale Semiconductor
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
Compare X (Index
Register Low) with
Memory
(X) (M)
(CCR Updated But Operands Not
Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9ED3
9EE3
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
DAA
Decimal Adjust
Accumulator After ADD or
ADC of BCD Values
(A)
10
U
INH
72
1
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
Decrement and Branch if
Not Zero
Decrement A, X, or M
Branch if (result)
0
DBNZX Affects X Not H
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff
rr
rr
ff
rr
7
4
4
7
6
8
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement
M
(M) 0x01
A
(A) 0x01
X
(X) 0x01
M
(M) 0x01
M
(M) 0x01
M
(M) 0x01
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
5
1
1
5
4
6
DIV
Divide
A
(H:A)(X)
H
Remainder
INH
52
6
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR
Memory with
Accumulator
A
(A M)
0
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A8
B8
C8
D8
E8
F8
9ED8
9EE8
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment
M
(M) + 0x01
A
(A) + 0x01
X
(X) + 0x01
M
(M) + 0x01
M
(M) + 0x01
M
(M) + 0x01
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
5
1
1
5
4
6
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump
PC
Jump Address
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
3
4
4
3
3
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC
(PC) + n (n = 1, 2, or 3)
Push (PCL); SP
(SP) 0x0001
Push (PCH); SP
(SP) 0x0001
PC
Unconditional Address
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
6
5
5
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from
Memory
A
(M)
0
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9ED6
9EE6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Load Index Register (H:X)
from Memory
H:X
(M:M + 0x0001)
0
IMM
DIR
EXT
IX
IX2
IX1
SP1
45
55
32
9EAE
9EBE
9ECE
9EFE
jj
kk
dd
hh ll
ee ff
ff
ff
3
4
5
5
6
5
5
Table 7-2. HCS08 Instruction Set Summary (Sheet 4 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
99
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register
Low) from Memory
X
(M)
0
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9EDE
9EEE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
5
1
1
5
4
6
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right
0
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
ff
5
1
1
5
4
6
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)
destination
(M)
source
H:X
(H:X) + 0x0001 in
IX+/DIR and DIR/IX+ Modes
0
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii
dd
dd
5
5
4
5
MUL
Unsigned multiply
X:A
(X) (A)
0 0
INH
42
5
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate
(Two's Complement)
M
(M) = 0x00 (M)
A
(A) = 0x00 (A)
X
(X) = 0x00 (X)
M
(M) = 0x00 (M)
M
(M) = 0x00 (M)
M
(M) = 0x00 (M)
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
ff
5
1
1
5
4
6
NOP
No Operation
Uses 1 Bus Cycle
INH
9D
1
NSA
Nibble Swap
Accumulator
A
(A[3:0]:A[7:4])
INH
62
1
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
Inclusive OR Accumulator
and Memory
A
(A) | (M)
0
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9EDA
9EEA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
PSHA
Push Accumulator onto
Stack
Push (A); SP
(SP) 0x0001
INH
87
2
PSHH
Push H (Index Register
High) onto Stack
Push (H); SP
(SP) 0x0001
INH
8B
2
PSHX
Push X (Index Register
Low) onto Stack
Push (X); SP
(SP) 0x0001
INH
89
2
PULA
Pull Accumulator from
Stack
SP
(SP + 0x0001); Pull (A)
INH
86
3
PULH
Pull H (Index Register
High) from Stack
SP
(SP + 0x0001); Pull (H)
INH
8A
3
PULX
Pull X (Index Register
Low) from Stack
SP
(SP + 0x0001); Pull (X)
INH
88
3
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Rotate Left through Carry
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
dd
ff
ff
5
1
1
5
4
6
Table 7-2. HCS08 Instruction Set Summary (Sheet 5 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
C
b0
b7
0
b0
b7
C
0
C
b0
b7
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
100
Freescale Semiconductor
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Rotate Right through
Carry
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
5
1
1
5
4
6
RSP
Reset Stack Pointer
SP
0xFF
(High Byte Not Affected)
INH
9C
1
RTI
Return from Interrupt
SP
(SP) + 0x0001; Pull (CCR)
SP
(SP) + 0x0001; Pull (A)
SP
(SP) + 0x0001; Pull (X)
SP
(SP) + 0x0001; Pull (PCH)
SP
(SP) + 0x0001; Pull (PCL)
INH
80
9
RTS
Return from Subroutine
SP
SP + 0x0001; Pull (PCH)
SP
SP + 0x0001; Pull (PCL)
INH
81
6
SBC #opr8i
SBC opr8a
SBC opr16a
SBC oprx16,X
SBC oprx8,X
SBC ,X
SBC oprx16,SP
SBC oprx8,SP
Subtract with Carry
A
(A) (M) (C)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A2
B2
C2
D2
E2
F2
9ED2
9EE2
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
SEC
Set Carry Bit
C
1
1
INH
99
1
SEI
Set Interrupt Mask Bit
I
1
1
INH
9B
1
STA opr8a
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
Store Accumulator in
Memory
M
(A)
0
DIR
EXT
IX2
IX1
IX
SP2
SP1
B7
C7
D7
E7
F7
9ED7
9EE7
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
STHX opr8a
STHX opr16a
STHX oprx8,SP
Store H:X (Index Reg.)
(M:M + 0x0001)
(H:X)
0
DIR
EXT
SP1
35
96
9EFF
dd
hh ll
ff
4
5
5
STOP
Enable Interrupts:
Stop Processing
Refer to MCU
Documentation
I bit
0; Stop Processing
0
INH
8E
2+
STX opr8a
STX opr16a
STX oprx16,X
STX oprx8,X
STX ,X
STX oprx16,SP
STX oprx8,SP
Store X (Low 8 Bits of
Index Register)
in Memory
M
(X)
0
DIR
EXT
IX2
IX1
IX
SP2
SP1
BF
CF
DF
EF
FF
9EDF
9EEF
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
Subtract
A
(A) (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A0
B0
C0
D0
E0
F0
9ED0
9EE0
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
SWI
Software Interrupt
PC
(PC) + 0x0001
Push (PCL); SP
(SP) 0x0001
Push (PCH); SP
(SP) 0x0001
Push (X); SP
(SP) 0x0001
Push (A); SP
(SP) 0x0001
Push (CCR); SP
(SP) 0x0001
I
1;
PCH
Interrupt Vector High Byte
PCL
Interrupt Vector Low Byte
1
INH
83
11
Table 7-2. HCS08 Instruction Set Summary (Sheet 6 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
b0
b7
C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
101
TAP
Transfer Accumulator to
CCR
CCR
(A)
INH
84
1
TAX
Transfer Accumulator to
X (Index Register Low)
X
(A)
INH
97
1
TPA
Transfer CCR to
Accumulator
A
(CCR)
INH
85
1
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero
(M) 0x00
(A) 0x00
(X) 0x00
(M) 0x00
(M) 0x00
(M) 0x00
0
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
4
1
1
4
3
5
TSX
Transfer SP to Index Reg.
H:X
(SP) + 0x0001
INH
95
2
TXA
Transfer X (Index Reg.
Low) to Accumulator
A
(X)
INH
9F
1
TXS
Transfer Index Reg. to SP
SP
(H:X) 0x0001
INH
94
2
WAIT
Enable Interrupts; Wait
for Interrupt
I bit
0; Halt CPU
0
INH
8F
2+
1
Bus clock frequency is one-half of the CPU clock frequency.
Table 7-2. HCS08 Instruction Set Summary (Sheet 7 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus Cyc
les
1
V H I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
102
Freescale Semiconductor
Table 7-3. Opcode Map (Sheet 1 of 2)
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
00
5
BRSET0
3
DIR
10
5
BSET0
2
DIR
20
3
BRA
2
REL
30
5
NEG
2
DIR
40
1
NEGA
1
INH
50
1
NEGX
1
INH
60
5
NEG
2
IX1
70
4
NEG
1
IX
80
9
RTI
1
INH
90
3
BGE
2
REL
A0
2
SUB
2
IMM
B0
3
SUB
2
DIR
C0
4
SUB
3
EXT
D0
4
SUB
3
IX2
E0
3
SUB
2
IX1
F0
3
SUB
1
IX
01
5
BRCLR0
3
DIR
11
5
BCLR0
2
DIR
21
3
BRN
2
REL
31
5
CBEQ
3
DIR
41
4
CBEQA
3
IMM
51
4
CBEQX
3
IMM
61
5
CBEQ
3
IX1+
71
5
CBEQ
2
IX+
81
6
RTS
1
INH
91
3
BLT
2
REL
A1
2
CMP
2
IMM
B1
3
CMP
2
DIR
C1
4
CMP
3
EXT
D1
4
CMP
3
IX2
E1
3
CMP
2
IX1
F1
3
CMP
1
IX
02
5
BRSET1
3
DIR
12
5
BSET1
2
DIR
22
3
BHI
2
REL
32
5
LDHX
3
EXT
42
5
MUL
1
INH
52
6
DIV
1
INH
62
1
NSA
1
INH
72
1
DAA
1
INH
82
5+
BGND
1
INH
92
3
BGT
2
REL
A2
2
SBC
2
IMM
B2
3
SBC
2
DIR
C2
4
SBC
3
EXT
D2
4
SBC
3
IX2
E2
3
SBC
2
IX1
F2
3
SBC
1
IX
03
5
BRCLR1
3
DIR
13
5
BCLR1
2
DIR
23
3
BLS
2
REL
33
5
COM
2
DIR
43
1
COMA
1
INH
53
1
COMX
1
INH
63
5
COM
2
IX1
73
4
COM
1
IX
83
11
SWI
1
INH
93
3
BLE
2
REL
A3
2
CPX
2
IMM
B3
3
CPX
2
DIR
C3
4
CPX
3
EXT
D3
4
CPX
3
IX2
E3
3
CPX
2
IX1
F3
3
CPX
1
IX
04
5
BRSET2
3
DIR
14
5
BSET2
2
DIR
24
3
BCC
2
REL
34
5
LSR
2
DIR
44
1
LSRA
1
INH
54
1
LSRX
1
INH
64
5
LSR
2
IX1
74
4
LSR
1
IX
84
1
TAP
1
INH
94
2
TXS
1
INH
A4
2
AND
2
IMM
B4
3
AND
2
DIR
C4
4
AND
3
EXT
D4
4
AND
3
IX2
E4
3
AND
2
IX1
F4
3
AND
1
IX
05
5
BRCLR2
3
DIR
15
5
BCLR2
2
DIR
25
3
BCS
2
REL
35
4
STHX
2
DIR
45
3
LDHX
3
IMM
55
4
LDHX
2
DIR
65
3
CPHX
3
IMM
75
5
CPHX
2
DIR
85
1
TPA
1
INH
95
2
TSX
1
INH
A5
2
BIT
2
IMM
B5
3
BIT
2
DIR
C5
4
BIT
3
EXT
D5
4
BIT
3
IX2
E5
3
BIT
2
IX1
F5
3
BIT
1
IX
06
5
BRSET3
3
DIR
16
5
BSET3
2
DIR
26
3
BNE
2
REL
36
5
ROR
2
DIR
46
1
RORA
1
INH
56
1
RORX
1
INH
66
5
ROR
2
IX1
76
4
ROR
1
IX
86
3
PULA
1
INH
96
5
STHX
3
EXT
A6
2
LDA
2
IMM
B6
3
LDA
2
DIR
C6
4
LDA
3
EXT
D6
4
LDA
3
IX2
E6
3
LDA
2
IX1
F6
3
LDA
1
IX
07
5
BRCLR3
3
DIR
17
5
BCLR3
2
DIR
27
3
BEQ
2
REL
37
5
ASR
2
DIR
47
1
ASRA
1
INH
57
1
ASRX
1
INH
67
5
ASR
2
IX1
77
4
ASR
1
IX
87
2
PSHA
1
INH
97
1
TAX
1
INH
A7
2
AIS
2
IMM
B7
3
STA
2
DIR
C7
4
STA
3
EXT
D7
4
STA
3
IX2
E7
3
STA
2
IX1
F7
2
STA
1
IX
08
5
BRSET4
3
DIR
18
5
BSET4
2
DIR
28
3
BHCC
2
REL
38
5
LSL
2
DIR
48
1
LSLA
1
INH
58
1
LSLX
1
INH
68
5
LSL
2
IX1
78
4
LSL
1
IX
88
3
PULX
1
INH
98
1
CLC
1
INH
A8
2
EOR
2
IMM
B8
3
EOR
2
DIR
C8
4
EOR
3
EXT
D8
4
EOR
3
IX2
E8
3
EOR
2
IX1
F8
3
EOR
1
IX
09
5
BRCLR4
3
DIR
19
5
BCLR4
2
DIR
29
3
BHCS
2
REL
39
5
ROL
2
DIR
49
1
ROLA
1
INH
59
1
ROLX
1
INH
69
5
ROL
2
IX1
79
4
ROL
1
IX
89
2
PSHX
1
INH
99
1
SEC
1
INH
A9
2
ADC
2
IMM
B9
3
ADC
2
DIR
C9
4
ADC
3
EXT
D9
4
ADC
3
IX2
E9
3
ADC
2
IX1
F9
3
ADC
1
IX
0A
5
BRSET5
3
DIR
1A
5
BSET5
2
DIR
2A
3
BPL
2
REL
3A
5
DEC
2
DIR
4A
1
DECA
1
INH
5A
1
DECX
1
INH
6A
5
DEC
2
IX1
7A
4
DEC
1
IX
8A
3
PULH
1
INH
9A
1
CLI
1
INH
AA
2
ORA
2
IMM
BA
3
ORA
2
DIR
CA
4
ORA
3
EXT
DA
4
ORA
3
IX2
EA
3
ORA
2
IX1
FA
3
ORA
1
IX
0B
5
BRCLR5
3
DIR
1B
5
BCLR5
2
DIR
2B
3
BMI
2
REL
3B
7
DBNZ
3
DIR
4B
4
DBNZA
2
INH
5B
4
DBNZX
2
INH
6B
7
DBNZ
3
IX1
7B
6
DBNZ
2
IX
8B
2
PSHH
1
INH
9B
1
SEI
1
INH
AB
2
ADD
2
IMM
BB
3
ADD
2
DIR
CB
4
ADD
3
EXT
DB
4
ADD
3
IX2
EB
3
ADD
2
IX1
FB
3
ADD
1
IX
0C
5
BRSET6
3
DIR
1C
5
BSET6
2
DIR
2C
3
BMC
2
REL
3C
5
INC
2
DIR
4C
1
INCA
1
INH
5C
1
INCX
1
INH
6C
5
INC
2
IX1
7C
4
INC
1
IX
8C
1
CLRH
1
INH
9C
1
RSP
1
INH
BC
3
JMP
2
DIR
CC
4
JMP
3
EXT
DC
4
JMP
3
IX2
EC
3
JMP
2
IX1
FC
3
JMP
1
IX
0D
5
BRCLR6
3
DIR
1D
5
BCLR6
2
DIR
2D
3
BMS
2
REL
3D
4
TST
2
DIR
4D
1
TSTA
1
INH
5D
1
TSTX
1
INH
6D
4
TST
2
IX1
7D
3
TST
1
IX
9D
1
NOP
1
INH
AD
5
BSR
2
REL
BD
5
JSR
2
DIR
CD
6
JSR
3
EXT
DD
6
JSR
3
IX2
ED
5
JSR
2
IX1
FD
5
JSR
1
IX
0E
5
BRSET7
3
DIR
1E
5
BSET7
2
DIR
2E
3
BIL
2
REL
3E
6
CPHX
3
EXT
4E
5
MOV
3
DD
5E
5
MOV
2
DIX+
6E
4
MOV
3
IMD
7E
5
MOV
2
IX+D
8E
2+
STOP
1
INH
9E
Page 2
AE
2
LDX
2
IMM
BE
3
LDX
2
DIR
CE
4
LDX
3
EXT
DE
4
LDX
3
IX2
EE
3
LDX
2
IX1
FE
3
LDX
1
IX
0F
5
BRCLR7
3
DIR
1F
5
BCLR7
2
DIR
2F
3
BIH
2
REL
3F
5
CLR
2
DIR
4F
1
CLRA
1
INH
5F
1
CLRX
1
INH
6F
5
CLR
2
IX1
7F
4
CLR
1
IX
8F
2+
WAIT
1
INH
9F
1
TXA
1
INH
AF
2
AIX
2
IMM
BF
3
STX
2
DIR
CF
4
STX
3
EXT
DF
4
STX
3
IX2
EF
3
STX
2
IX1
FF
2
STX
1
IX
INH
Inherent
REL
Relative
SP1
Stack Pointer, 8-Bit Offset
IMM
Immediate
IX
Indexed, No Offset
SP2
Stack Pointer, 16-Bit Offset
DIR
Direct
IX1
Indexed, 8-Bit Offset
IX+
Indexed, No Offset with
EXT
Extended
IX2
Indexed, 16-Bit Offset
Post Increment
DD
DIR to DIR
IMD
IMM to DIR
IX1+
Indexed, 1-Byte Offset with
IX+D
IX+ to DIR
DIX+
DIR to IX+
Post Increment
Opcode in
Hexadecimal
Number of Bytes
F0
3
SUB
1
IX
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
103
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
9E60
6
NEG
3
SP1
9ED0
5
SUB
4
SP2
9EE0
4
SUB
3
SP1
9E61
6
CBEQ
4
SP1
9ED1
5
CMP
4
SP2
9EE1
4
CMP
3
SP1
9ED2
5
SBC
4
SP2
9EE2
4
SBC
3
SP1
9E63
6
COM
3
SP1
9ED3
5
CPX
4
SP2
9EE3
4
CPX
3
SP1
9EF3
6
CPHX
3
SP1
9E64
6
LSR
3
SP1
9ED4
5
AND
4
SP2
9EE4
4
AND
3
SP1
9ED5
5
BIT
4
SP2
9EE5
4
BIT
3
SP1
9E66
6
ROR
3
SP1
9ED6
5
LDA
4
SP2
9EE6
4
LDA
3
SP1
9E67
6
ASR
3
SP1
9ED7
5
STA
4
SP2
9EE7
4
STA
3
SP1
9E68
6
LSL
3
SP1
9ED8
5
EOR
4
SP2
9EE8
4
EOR
3
SP1
9E69
6
ROL
3
SP1
9ED9
5
ADC
4
SP2
9EE9
4
ADC
3
SP1
9E6A
6
DEC
3
SP1
9EDA
5
ORA
4
SP2
9EEA
4
ORA
3
SP1
9E6B
8
DBNZ
4
SP1
9EDB
5
ADD
4
SP2
9EEB
4
ADD
3
SP1
9E6C
6
INC
3
SP1
9E6D
5
TST
3
SP1
9EAE
5
LDHX
2
IX
9EBE
6
LDHX
4
IX2
9ECE
5
LDHX
3
IX1
9EDE
5
LDX
4
SP2
9EEE
4
LDX
3
SP1
9EFE
5
LDHX
3
SP1
9E6F
6
CLR
3
SP1
9EDF
5
STX
4
SP2
9EEF
4
STX
3
SP1
9EFF
5
STHX
3
SP1
INH
Inherent
REL
Relative
SP1
Stack Pointer, 8-Bit Offset
IMM
Immediate
IX
Indexed, No Offset
SP2
Stack Pointer, 16-Bit Offset
DIR
Direct
IX1
Indexed, 8-Bit Offset
IX+
Indexed, No Offset with
EXT
Extended
IX2
Indexed, 16-Bit Offset
Post Increment
DD
DIR to DIR
IMD
IMM to DIR
IX1+
Indexed, 1-Byte Offset with
IX+D
IX+ to DIR
DIX+
DIR to IX+
Post Increment
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
Prebyte (9E) and Opcode in
Hexadecimal
Number of Bytes
9E60
6
NEG
3
SP1
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
Table 7-3. Opcode Map (Sheet 2 of 2)
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
104
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
105
Chapter 8
Analog Comparator (S08ACMPV2)
8.1
Introduction
The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for
comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to
operate across the full range of the supply voltage (rail-to-rail operation).
Figure 8-1
shows the MC9S08QG8/4 block diagram with the ACMP highlighted.
8.1.1
ACMP Configuration Information
When using the bandgap reference voltage for input to ACMP+, the user must enable the bandgap buffer
by setting BGBE =1 in SPMSC1 see
Section 5.8.8, "System Power Management Status and Control 1
Register (SPMSC1)
". For value of bandgap voltage reference see
Section A.5, "DC Characteristics
".
8.1.2
ACMP/TPM Configuration Information
The ACMP module can be configured to connect the output of the analog comparator to TPM input capture
channel 0 by setting ACIC in SOPT2. With ACIC set, the TPMCH0 pin is not available externally
regardless of the configuration of the TPM module.
Chapter 8 Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
106
Freescale Semiconductor
Figure 8-1. MC9S08QG8/4 Block Diagram Highlighting ACMP Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
TCLK
BKGD/MS
IRQ
4
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
ANALOG COMPARATOR
(ACMP)
ACMPO
ACMP
ACMP+
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
107
8.1.3
Features
The ACMP has the following features:
Full rail-to-rail supply operation.
Less than 40 mV of input offset.
Less than 15 mV of hysteresis.
Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator
output.
Option to compare to fixed internal bandgap reference voltage.
Option to allow comparator output to be visible on a pin, ACMPO.
8.1.4
Modes of Operation
This section defines the ACMP operation in wait, stop, and background debug modes.
8.1.4.1
ACMP in Wait Mode
The ACMP continues to run in wait mode if enabled before executing the WAIT instruction. Therefore,
the ACMP can be used to bring the MCU out of wait mode if the ACMP interrupt, ACIE, is enabled. For
lowest possible current consumption, the ACMP should be disabled by software if not required as an
interrupt source during wait mode.
8.1.4.2
ACMP in Stop Modes
The ACMP is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
Therefore, the ACMP cannot be used as a wake up source from stop modes.
During either stop1 or stop2 mode, the ACMP module will be fully powered down. Upon wake-up from
stop1 or stop2 mode, the ACMP module will be in the reset state.
During stop3 mode, clocks to the ACMP module are halted. No registers are affected. In addition, the
ACMP comparator circuit will enter a low power state. No compare operation will occur while in stop3.
If stop3 is exited with a reset, the ACMP will be put into its reset state. If stop3 is exited with an interrupt,
the ACMP continues from the state it was in when stop3 was entered.
8.1.4.3
ACMP in Active Background Mode
When the microcontroller is in active background mode, the ACMP will continue to operate normally.
8.1.5
Block Diagram
The block diagram for the analog comparator module is shown
Figure 8-2
.
Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
108
Freescale Semiconductor
Figure 8-2. Analog Comparator (ACMP) Block Diagram
+
Interrupt
Control
Internal
Reference
ACBGS
Internal Bus
Status & Control
Register
A
CMOD
set A
C
F
ACME
ACF
ACIE
ACOPE
Comparator
ACMP
INTERRUPT
REQUEST
ACMP+
ACMP
ACMPO
Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
109
8.2
External Signal Description
The ACMP has two analog input pins, ACMP+ and ACMP and one digital output pin ACMPO. Each of
these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As
shown in
Figure 8-2
, the ACMP pin is connected to the inverting input of the comparator, and the ACMP+
pin is connected to the comparator non-inverting input if ACBGS is a 0. As shown in
Figure 8-2
, the
ACMPO pin can be enabled to drive an external pin.
The signal properties of ACMP are shown in
Table 8-1
.
8.3
Register Definition
The ACMP includes one register:
An 8-bit status and control register
Refer to the direct-page register summary in the memory section of this data sheet for the absolute address
assignments for all ACMP registers.This section refers to registers and control bits only by their names and
relative address offsets.
Some MCUs may have more than one ACMP, so register names include placeholder characters to identify
which ACMP is being referenced.
Table 8-1. Signal Properties
Signal
Function
I/O
ACMP
Inverting analog input to the ACMP.
(Minus input)
I
ACMP+
Non-inverting analog input to the ACMP.
(Positive input)
I
ACMPO
Digital output of the ACMP.
O
Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
110
Freescale Semiconductor
8.3.1
ACMP Status and Control Register (ACMPSC)
ACMPSC contains the status flag and control bits which are used to enable and configure the ACMP.
7
6
5
4
3
2
1
0
R
ACME
ACBGS
ACF
ACIE
ACO
ACOPE
ACMOD
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. ACMP Status and Control Register
Table 8-2. ACMP Status and Control Register Field Descriptions
Field
Description
7
ACME
Analog Comparator Module Enable -- ACME enables the ACMP module.
0 ACMP not enabled
1 ACMP is enabled
6
ACBGS
Analog Comparator Bandgap Select -- ACBGS is used to select between the bandgap reference voltage or
the ACMP+ pin as the input to the non-inverting input of the analog comparatorr.
0 External pin ACMP+ selected as non-inverting input to comparator
1 Internal reference select as non-inverting input to comparator
5
ACF
Analog Comparator Flag -- ACF is set when a compare event occurs. Compare events are defined by ACMOD.
ACF is cleared by writing a one to ACF.
0 Compare event has not occurred
1 Compare event has occurred
4
ACIE
Analog Comparator Interrupt Enable -- ACIE enables the interrupt from the ACMP. When ACIE is set, an
interrupt will be asserted when ACF is set.
0 Interrupt disabled
1 Interrupt enabled
3
ACO
Analog Comparator Output -- Reading ACO will return the current value of the analog comparator output. ACO
is reset to a 0 and will read as a 0 when the ACMP is disabled (ACME = 0).
2
ACOPE
Analog Comparator Output Pin Enable -- ACOPE is used to enable the comparator output to be placed onto
the external pin, ACMPO.
0 Analog comparator output not available on ACMPO
1 Analog comparator output is driven out on ACMPO
1:0
ACMOD
Analog Comparator Mode -- ACMOD selects the type of compare event which sets ACF.
00 Encoding 0 -- Comparator output falling edge
01 Encoding 1 -- Comparator output rising edge
10 Encoding 2 -- Comparator output falling edge
11 Encoding 3 -- Comparator output rising or falling edge
Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
111
8.4
Functional Description
The analog comparator can be used to compare two analog input voltages applied to ACMP+ and ACMP;
or it can be used to compare an analog input voltage applied to ACMP with an internal bandgap reference
voltage. ACBGS is used to select between the bandgap reference voltage or the ACMP+ pin as the input
to the non-inverting input of the analog comparator. The comparator output is high when the non-inverting
input is greater than the inverting input, and is low when the non-inverting input is less than the inverting
input. ACMOD is used to select the condition which will cause ACF to be set. ACF can be set on a rising
edge of the comparator output, a falling edge of the comparator output, or either a rising or a falling edge
(toggle). The comparator output can be read directly through ACO. The comparator output can be driven
onto the ACMPO pin using ACOPE.
Analog Comparator (S08ACMPV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
112
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
113
Chapter 9
Analog-to-Digital Converter (S08ADC10V1)
9.1
Introduction
The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
Figure 9-1
shows the MC9S08QG8/4 with the ADC module and pins highlighted.
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
114
Freescale Semiconductor
Figure 9-1. MC9S08QG8/4 Block Diagram Highlighting ADC Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
115
9.1.1
Module Configurations
This section provides device-specific information for configuring the ADC on MC9S08QG8/4.
9.1.1.1
Analog Supply and Voltage Reference Connections
The V
DDAD
and V
REFH
sources for the ADC are internally connected to the V
DD
pin. The V
SSAD
and
V
REFL
sources for the ADC are internally connected to the V
SS
pin.
9.1.1.2
Channel Assignments
The ADC channel assignments for the MC9S08QG8/4 devices are shown in
Table 9-1
. Reserved channels
convert to an unknown value.
NOTE
Selecting the internal bandgap channel requires BGBE =1 in SPMSC1 see
Section 5.8.8, "System Power Management Status and Control 1 Register
(SPMSC1)
." For value of bandgap voltage reference see
Section A.5, "DC
Characteristics
."
Table 9-1. ADC Channel Assignment
ADCH
Channel
Input
Pin Control
ADCH
Channel
Input
Pin Control
00000
AD0
PTA0/ADP0
ADPC0
10000
AD16
V
SS
N/A
00001
AD1
PTA1/ADP1
ADPC1
10001
AD17
V
SS
N/A
00010
AD2
PTA2/ADP2
ADPC2
10010
AD18
V
SS
N/A
00011
AD3
PTA3/ADP3
ADPC3
10011
AD19
V
SS
N/A
00100
AD4
PTB0/ADP4
ADPC4
10100
AD20
V
SS
N/A
00101
AD5
PTB1/ADP5
ADPC5
10101
AD21
V
SS
N/A
00110
AD6
PTB2/ADP6
ADPC6
10110
AD22
Reserved
N/A
00111
AD7
PTB3/ADP7
ADPC7
10111
AD23
Reserved
N/A
01000
AD8
V
SS
N/A
11000
AD24
Reserved
N/A
01001
AD9
V
SS
N/A
11001
AD25
Reserved
N/A
01010
AD10
V
SS
N/A
11010
AD26
Temperature
Sensor
1
1
For information, see
Section 9.1.1.6, "Temperature Sensor
."
N/A
01011
AD11
V
SS
N/A
11011
AD27
Internal Bandgap
N/A
01100
AD12
V
SS
N/A
11100
--
Reserved
N/A
01101
AD13
V
SS
N/A
11101
V
REFH
V
DD
N/A
01110
AD14
V
SS
N/A
11110
V
REFL
V
SS
N/A
01111
AD15
V
SS
N/A
11111
Module
Disabled
None
N/A
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
116
Freescale Semiconductor
9.1.1.3
Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
or the local asynchronous clock (ADACK) within the module. The alternate clock, ALTCLK, input for the
MC9S08QG8/4 MCU devices is not implemented.
9.1.1.4
Hardware Trigger
The ADC hardware trigger, ADHWT, is output from the real-time interrupt (RTI) counter. The RTI counter
can be clocked by either ICSERCLK or a nominal 1-kHz clock source within the RTI block.
The period of the RTI is determined by the input clock frequency and the RTIS bits. The RTI counter is a
free running counter that generates an overflow at the RTI rate determined by the RTIS bits. When the ADC
hardware trigger is enabled, a conversion is initiated upon a RTI counter overflow.
The RTI can be configured to cause a hardware trigger in MCU run, wait, and stop3.
9.1.1.5
Analog Pin Enables
The ADC on MC9S08QG8 contains only one analog pin enable register, APCTL1.
9.1.1.6
Temperature Sensor
The ADC module includes a temperature sensor whose output is connected to one of the ADC analog
channel inputs.
Equation 9-1
provides an approximate transfer function of the temperature sensor.
Temp = 25 - ((V
TEMP
-V
TEMP25
)
m)
Eqn. 9-1
where:
-- V
TEMP
is the voltage of the temperature sensor channel at the ambient temperature.
-- V
TEMP25
is the voltage of the temperature sensor channel at 25
C.
-- m is the hot or cold voltage versus temperature slope in V/
C.
For temperature calculations, use the V
TEMP25
and m values from
Section A.10, "ADC Characteristics
,"
in
Appendix A, "Electrical Characteristics
."
In application code, the user reads the temperature sensor channel, calculates V
TEMP
, and compares to
V
TEMP25
. If V
TEMP
is greater than V
TEMP25
the cold slope value is applied in
Equation 9-1
. If V
TEMP
is
less than V
TEMP25
the hot slope value is applied in
Equation 9-1
.
For more information on using the temperature sensor, consult Freescale document AN3031.
9.1.1.7
Low-Power Mode Operation
The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
117
9.1.2
Features
Features of the ADC module include:
Linear successive approximation algorithm with 10 bits resolution.
Up to 28 analog inputs.
Output formatted in 10- or 8-bit right-justified format.
Single or continuous conversion (automatic return to idle after single conversion).
Configurable sample time and conversion speed/power.
Conversion complete flag and interrupt.
Input clock selectable from up to four sources.
Operation in wait or stop3 modes for lower noise operation.
Asynchronous clock source for lower noise operation.
Selectable asynchronous hardware conversion trigger.
Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value.
9.1.3
Block Diagram
Figure 9-2
provides a block diagram of the ADC module
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
118
Freescale Semiconductor
Figure 9-2. ADC Block Diagram
9.2
External Signal Description
The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground
connections.
Table 9-2. Signal Properties
Name
Function
AD27AD0
Analog Channel inputs
V
REFH
High reference voltage
V
REFL
Low reference voltage
V
DDAD
Analog power supply
V
SSAD
Analog ground
AD0
AD27
V
REFH
V
REFL
ADVIN
ADCH
Control Sequencer
initialize
sample
convert
transfer
abort
Clock
Divide
ADCK
2
Async
Clock Gen
Bus Clock
ALTCLK
ADICLK
ADIV
ADACK
ADCO
ADLSMP
ADLPC
MODE
complete
Data Registers
SAR Converter
Compare Value Registers
Compare
Value
Sum
AIEN
COCO
Interrupt
AIEN
COCO
ADTRG
1
2
1
2
MCU STOP
ADHWT
Logic
A
CFGT
3
Compare true
3
Compare true
ADCCFG
ADCSC1
ADCSC2
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
119
9.2.1
Analog Power (V
DDAD
)
The ADC analog portion uses V
DDAD
as its power connection. In some packages, V
DDAD
is connected
internally to V
DD
. If externally available, connect the V
DDAD
pin to the same voltage potential as V
DD
.
External filtering may be necessary to ensure clean V
DDAD
for good results.
9.2.2
Analog Ground (V
SSAD
)
The ADC analog portion uses V
SSAD
as its ground connection. In some packages, V
SSAD
is connected
internally to V
SS
. If externally available, connect the V
SSAD
pin to the same voltage potential as V
SS
.
9.2.3
Voltage Reference High (V
REFH
)
V
REFH
is the high reference voltage for the converter. In some packages, V
REFH
is connected internally to
V
DDAD
. If externally available, V
REFH
may be connected to the same potential as V
DDAD
, or may be
driven by an external source that is between the minimum V
DDAD
spec and the V
DDAD
potential (V
REFH
must never exceed V
DDAD
).
9.2.4
Voltage Reference Low (V
REFL
)
V
REFL
is the low reference voltage for the converter. In some packages, V
REFL
is connected internally to
V
SSAD
. If externally available, connect the V
REFL
pin to the same voltage potential as V
SSAD
.
9.2.5
Analog Channel Inputs (ADx)
The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through the
ADCH channel select bits.
9.3
Register Definition
These memory mapped registers control and monitor operation of the ADC:
Status and control register, ADCSC1
Status and control register, ADCSC2
Data result registers, ADCRH and ADCRL
Compare value registers, ADCCVH and ADCCVL
Configuration register, ADCCFG
Pin enable registers, APCTL1, APCTL2, APCTL3
9.3.1
Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
120
Freescale Semiconductor
7
6
5
4
3
2
1
0
R
COCO
AIEN
ADCO
ADCH
W
Reset:
0
0
0
1
1
1
1
1
= Unimplemented or Reserved
Figure 9-3. Status and Control Register (ADCSC1)
Table 9-3. ADCSC1 Register Field Descriptions
Field
Description
7
COCO
Conversion Complete Flag -- The COCO flag is a read-only bit which is set each time a conversion is
completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =
1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared
whenever ADCSC1 is written or whenever ADCRL is read.
0 Conversion not completed
1 Conversion completed
6
AIEN
Interrupt Enable -- AIEN is used to enable conversion complete interrupts. When COCO becomes set while
AIEN is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
5
ADCO
Continuous Conversion Enable -- ADCO is used to enable continuous conversions.
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
4:0
ADCH
Input Channel Select -- The ADCH bits form a 5-bit field which is used to select one of the input channels. The
input channels are detailed in
Figure 9-4
.
The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.
This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way will prevent an additional, single conversion from being performed.
It is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
Figure 9-4. Input Channel Select
ADCH
Input Select
ADCH
Input Select
00000
AD0
10000
AD16
00001
AD1
10001
AD17
00010
AD2
10010
AD18
00011
AD3
10011
AD19
00100
AD4
10100
AD20
00101
AD5
10101
AD21
00110
AD6
10110
AD22
00111
AD7
10111
AD23
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
121
9.3.2
Status and Control Register 2 (ADCSC2)
The ADCSC2 register is used to control the compare function, conversion trigger and conversion active of
the ADC module.
Figure 9-5. Status and Control Register 2 (ADCSC2)
01000
AD8
11000
AD24
01001
AD9
11001
AD25
01010
AD10
11010
AD26
01011
AD11
11011
AD27
01100
AD12
11100
Reserved
01101
AD13
11101
V
REFH
01110
AD14
11110
V
REFL
01111
AD15
11111
Module disabled
7
6
5
4
3
2
1
0
R
ADACT
ADTRG
ACFE
ACFGT
0
0
R
1
1
Bits 1 and 0 are reserved bits that must always be written to 0.
R
1
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 9-4. ADCSC2 Register Field Descriptions
Field
Description
7
ADACT
Conversion Active -- ADACT indicates that a conversion is in progress. ADACT is set when a conversion is
initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
6
ADTRG
Conversion Trigger Select -- ADTRG is used to select the type of trigger to be used for initiating a conversion.
Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a
conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated
following the assertion of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected
Figure 9-4. Input Channel Select (continued)
ADCH
Input Select
ADCH
Input Select
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
122
Freescale Semiconductor
9.3.3
Data Result High Register (ADCRH)
ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 8-bit
conversions both ADR8 and ADR9 are equal to zero. ADCRH is updated each time a conversion
completes except when automatic compare is enabled and the compare condition is not met. In 10-bit
MODE, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode there is no interlocking with ADCRL. In the case
that the MODE bits are changed, any data in ADCRH becomes invalid.
9.3.4
Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit
conversion. This register is updated each time a conversion completes except when automatic compare is
enabled and the compare condition is not met. In 10-bit mode, reading ADCRH prevents the ADC from
transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not
read until the after next conversion is completed, then the intermediate conversion results will be lost. In
8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data
in ADCRL becomes invalid.
5
ACFE
Compare Function Enable -- ACFE is used to enable the compare function.
0 Compare function disabled
1 Compare function enabled
4
ACFGT
Compare Function Greater Than Enable -- ACFGT is used to configure the compare function to trigger when
the result of the conversion of the input being monitored is greater than or equal to the compare value. The
compare function defaults to triggering when the result of the compare of the input being monitored is less than
the compare value.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
ADR9
ADR8
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-6. Data Result High Register (ADCRH)
Table 9-4. ADCSC2 Register Field Descriptions (continued)
Field
Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
123
9.3.5
Compare Value High Register (ADCCVH)
This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper
two bits of the result following a conversion in 10-bit mode when the compare function is enabled.In 8-bit
operation, ADCCVH is not used during compare.
9.3.6
Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value.
Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in either 10-bit
or 8-bit mode.
9.3.7
Configuration Register (ADCCFG)
ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
7
6
5
4
3
2
1
0
R
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-7. Data Result Low Register (ADCRL)
7
6
5
4
3
2
1
0
R
0
0
0
0
ADCV9
ADCV8
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-8. Compare Value High Register (ADCCVH)
7
6
5
4
3
2
1
0
R
ADCV7
ADCV6
ADCV5
ADCV4
ADCV3
ADCV2
ADCV1
ADCV0
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-9. Compare Value Low Register(ADCCVL)
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
124
Freescale Semiconductor
7
6
5
4
3
2
1
0
R
ADLPC
ADIV
ADLSMP
MODE
ADICLK
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-10. Configuration Register (ADCCFG)
Table 9-5. ADCCFG Register Field Descriptions
Field
Description
7
ADLPC
Low Power Configuration -- ADLPC controls the speed and power configuration of the successive
approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: The power is reduced at the expense of maximum clock speed.
6:5
ADIV
Clock Divide Select -- ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
Table 9-6
shows the available clock configurations.
4
ADLSMP
Long Sample Time Configuration -- ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
3:2
MODE
Conversion Mode Selection -- MODE bits are used to select between 10- or 8-bit operation. See
Table 9-7
.
1:0
ADICLK
Input Clock Select -- ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table 9-8
.
Table 9-6. Clock Divide Select
ADIV
Divide Ratio
Clock Rate
00
1
Input clock
01
2
Input clock
2
10
4
Input clock
4
11
8
Input clock
8
Table 9-7. Conversion Modes
MODE
Mode Description
00
8-bit conversion (N=8)
01
Reserved
10
10-bit conversion (N=10)
11
Reserved
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
125
9.3.8
Pin Control 1 Register (APCTL1)
The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs.
APCTL1 is used to control the pins associated with channels 07 of the ADC module.
Table 9-8. Input Clock Select
ADICLK
Selected Clock Source
00
Bus clock
01
Bus clock divided by 2
10
Alternate clock (ALTCLK)
11
Asynchronous clock (ADACK)
7
6
5
4
3
2
1
0
R
ADPC7
ADPC6
ADPC5
ADPC4
ADPC3
ADPC2
ADPC1
ADPC0
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-11. Pin Control 1 Register (APCTL1)
Table 9-9. APCTL1 Register Field Descriptions
Field
Description
7
ADPC7
ADC Pin Control 7 -- ADPC7 is used to control the pin associated with channel AD7.
0 AD7 pin I/O control enabled
1 AD7 pin I/O control disabled
6
ADPC6
ADC Pin Control 6 -- ADPC6 is used to control the pin associated with channel AD6.
0 AD6 pin I/O control enabled
1 AD6 pin I/O control disabled
5
ADPC5
ADC Pin Control 5 -- ADPC5 is used to control the pin associated with channel AD5.
0 AD5 pin I/O control enabled
1 AD5 pin I/O control disabled
4
ADPC4
ADC Pin Control 4 -- ADPC4 is used to control the pin associated with channel AD4.
0 AD4 pin I/O control enabled
1 AD4 pin I/O control disabled
3
ADPC3
ADC Pin Control 3 -- ADPC3 is used to control the pin associated with channel AD3.
0 AD3 pin I/O control enabled
1 AD3 pin I/O control disabled
2
ADPC2
ADC Pin Control 2 -- ADPC2 is used to control the pin associated with channel AD2.
0 AD2 pin I/O control enabled
1 AD2 pin I/O control disabled
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
126
Freescale Semiconductor
9.3.9
Pin Control 2 Register (APCTL2)
APCTL2 is used to control channels 815 of the ADC module.
1
ADPC1
ADC Pin Control 1 -- ADPC1 is used to control the pin associated with channel AD1.
0 AD1 pin I/O control enabled
1 AD1 pin I/O control disabled
0
ADPC0
ADC Pin Control 0 -- ADPC0 is used to control the pin associated with channel AD0.
0 AD0 pin I/O control enabled
1 AD0 pin I/O control disabled
7
6
5
4
3
2
1
0
R
ADPC15
ADPC14
ADPC13
ADPC12
ADPC11
ADPC10
ADPC9
ADPC8
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-12. Pin Control 2 Register (APCTL2)
Table 9-10. APCTL2 Register Field Descriptions
Field
Description
7
ADPC15
ADC Pin Control 15 -- ADPC15 is used to control the pin associated with channel AD15.
0 AD15 pin I/O control enabled
1 AD15 pin I/O control disabled
6
ADPC14
ADC Pin Control 14 -- ADPC14 is used to control the pin associated with channel AD14.
0 AD14 pin I/O control enabled
1 AD14 pin I/O control disabled
5
ADPC13
ADC Pin Control 13 -- ADPC13 is used to control the pin associated with channel AD13.
0 AD13 pin I/O control enabled
1 AD13 pin I/O control disabled
4
ADPC12
ADC Pin Control 12 -- ADPC12 is used to control the pin associated with channel AD12.
0 AD12 pin I/O control enabled
1 AD12 pin I/O control disabled
3
ADPC11
ADC Pin Control 11 -- ADPC11 is used to control the pin associated with channel AD11.
0 AD11 pin I/O control enabled
1 AD11 pin I/O control disabled
2
ADPC10
ADC Pin Control 10 -- ADPC10 is used to control the pin associated with channel AD10.
0 AD10 pin I/O control enabled
1 AD10 pin I/O control disabled
Table 9-9. APCTL1 Register Field Descriptions (continued)
Field
Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
127
9.3.10
Pin Control 3 Register (APCTL3)
APCTL3 is used to control channels 1623 of the ADC module.
1
ADPC9
ADC Pin Control 9 -- ADPC9 is used to control the pin associated with channel AD9.
0 AD9 pin I/O control enabled
1 AD9 pin I/O control disabled
0
ADPC8
ADC Pin Control 8 -- ADPC8 is used to control the pin associated with channel AD8.
0 AD8 pin I/O control enabled
1 AD8 pin I/O control disabled
7
6
5
4
3
2
1
0
R
ADPC23
ADPC22
ADPC21
ADPC20
ADPC19
ADPC18
ADPC17
ADPC16
W
Reset:
0
0
0
0
0
0
0
0
Figure 9-13. Pin Control 3 Register (APCTL3)
Table 9-11. APCTL3 Register Field Descriptions
Field
Description
7
ADPC23
ADC Pin Control 23 -- ADPC23 is used to control the pin associated with channel AD23.
0 AD23 pin I/O control enabled
1 AD23 pin I/O control disabled
6
ADPC22
ADC Pin Control 22 -- ADPC22 is used to control the pin associated with channel AD22.
0 AD22 pin I/O control enabled
1 AD22 pin I/O control disabled
5
ADPC21
ADC Pin Control 21 -- ADPC21 is used to control the pin associated with channel AD21.
0 AD21 pin I/O control enabled
1 AD21 pin I/O control disabled
4
ADPC20
ADC Pin Control 20 -- ADPC20 is used to control the pin associated with channel AD20.
0 AD20 pin I/O control enabled
1 AD20 pin I/O control disabled
3
ADPC19
ADC Pin Control 19 -- ADPC19 is used to control the pin associated with channel AD19.
0 AD19 pin I/O control enabled
1 AD19 pin I/O control disabled
2
ADPC18
ADC Pin Control 18 -- ADPC18 is used to control the pin associated with channel AD18.
0 AD18 pin I/O control enabled
1 AD18 pin I/O control disabled
Table 9-10. APCTL2 Register Field Descriptions (continued)
Field
Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
128
Freescale Semiconductor
9.4
Functional Description
The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a
conversion has completed and another conversion has not been initiated. When idle, the module is in its
lowest power state.
The ADC can perform an analog-to-digital conversion on any of the software selectable channels. The
selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result.
In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a
9-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL).In
10-bit mode, the result is rounded to 10 bits and placed in ADCRH and ADCRL. In 8-bit mode, the result
is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) is then set and an
interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates
in conjunction with any of the conversion modes and configurations.
9.4.1
Clock Select and Divide Control
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
The bus clock divided by 2. For higher bus clock rates, this allows a maximum divide by 16 of the
bus clock.
ALTCLK, as defined for this MCU (See module section introduction).
The asynchronous clock (ADACK) This clock is generated from a clock source within the ADC
module. When selected as the clock source this clock remains active while the MCU is in wait or
stop3 mode and allows conversions in these modes for lower noise operation.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC will not perform according to specifications. If the available clocks
1
ADPC17
ADC Pin Control 17 -- ADPC17 is used to control the pin associated with channel AD17.
0 AD17 pin I/O control enabled
1 AD17 pin I/O control disabled
0
ADPC16
ADC Pin Control 16 -- ADPC16 is used to control the pin associated with channel AD16.
0 AD16 pin I/O control enabled
1 AD16 pin I/O control disabled
Table 9-11. APCTL3 Register Field Descriptions (continued)
Field
Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
129
are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the
ADIV bits and can be divide-by 1, 2, 4, or 8.
9.4.2
Input Select and Pin Control
The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the
pins used as analog inputs.When a pin control register bit is set, the following conditions are forced for the
associated MCU pin:
The output buffer is forced to its high impedance state.
The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
The pullup is disabled.
9.4.3
Hardware Trigger
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled
when the ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for
information on the ADHWT source specific to this MCU.
When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is initiated
on the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is
ignored. In continuous convert configuration, only the initial rising edge to launch continuous conversions
is observed. The hardware trigger function operates in conjunction with any of the conversion modes and
configurations.
9.4.4
Conversion Control
Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits.
Conversions can be initiated by either a software or hardware trigger. In addition, the ADC module can be
configured for low power operation, long sample time, continuous conversion, and automatic compare of
the conversion result to a software determined compare value.
9.4.4.1
Initiating Conversions
A conversion is initiated:
Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is
selected.
Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
Following the transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
130
Freescale Semiconductor
9.4.4.2
Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high
at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if
the previous data is in the process of being read while in 12-bit or 10-bit MODE (the ADCRH register has
been read but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO
is not set, and the new result is lost. In the case of single conversions with the compare function enabled
and the compare condition false, blocking has no effect and ADC operation is terminated. In all other cases
of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of
ADCO (single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.
9.4.4.3
Aborting Conversions
Any conversion in progress will be aborted when:
A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
The MCU is reset.
The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case that
the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
9.4.4.4
Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum value
for f
ADCK
(see the electrical specifications).
9.4.4.5
Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock (
f
ADCK
). After
the module becomes active, sampling of the input begins. ADLSMP is used to select between short and
long sample times.When sampling is complete, the converter is isolated from the input channel and a
successive approximation algorithm is performed to determine the digital value of the analog signal. The
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
131
result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion
algorithm.
If the bus frequency is less than the f
ADCK
frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
ADCK
frequency, precise sample time for continuous conversions cannot be guaranteed when long
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in
Table 9-12
.
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
NOTE
The ADCK frequency must be between f
ADCK
minimum and f
ADCK
maximum to meet ADC specifications.
Table 9-12. Total Conversion Time vs. Control Conditions
Conversion Type
ADICLK
ADLSMP
Max Total Conversion Time
Single or first continuous 8-bit
0x, 10
0
20 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit
0x, 10
0
23 ADCK cycles + 5 bus clock cycles
Single or first continuous 8-bit
0x, 10
1
40 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit
0x, 10
1
43 ADCK cycles + 5 bus clock cycles
Single or first continuous 8-bit
11
0
5
s + 20 ADCK + 5 bus clock cycles
Single or first continuous 10-bit
11
0
5
s + 23 ADCK + 5 bus clock cycles
Single or first continuous 8-bit
11
1
5
s + 40 ADCK + 5 bus clock cycles
Single or first continuous 10-bit
11
1
5
s + 43 ADCK + 5 bus clock cycles
Subsequent continuous 8-bit;
f
BUS
> f
ADCK
xx
0
17 ADCK cycles
Subsequent continuous 10-bit;
f
BUS
> f
ADCK
xx
0
20 ADCK cycles
Subsequent continuous 8-bit;
f
BUS
> f
ADCK
/11
xx
1
37 ADCK cycles
Subsequent continuous 10-bit;
f
BUS
> f
ADCK
/11
xx
1
40 ADCK cycles
23 ADCK cyc
Conversion time =
8 MHz/1
Number of bus cycles = 3.5
s x 8 MHz = 28 cycles
5 bus cyc
8 MHz
+
= 3.5
s
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
132
Freescale Semiconductor
9.4.5
Automatic Compare Function
The compare function can be configured to check for either an upper limit or lower limit. After the input
is sampled and converted, the result is added to the two's complement of the compare value (ADCCVH
and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to
the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than
the compare value, COCO is set. The value generated by the addition of the conversion result and the two's
complement of the compare value is transferred to ADCRH and ADCRL.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon
the setting of COCO if the ADC interrupt is enabled (AIEN = 1).
NOTE
The compare function can be used to monitor the voltage on a channel while
the MCU is in either wait or stop3 mode. The ADC interrupt will wake the
MCU when the compare condition is met.
9.4.6
MCU Wait Mode Operation
The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery
is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters
wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by
means of the hardware trigger or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in
wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of
ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this
MCU.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait
mode if the ADC interrupt is enabled (AIEN = 1).
9.4.7
MCU Stop3 Mode Operation
The STOP instruction is used to put the MCU in a low power-consumption standby mode during which
most or all clock sources on the MCU are disabled.
9.4.7.1
Stop3 Mode With ADACK Disabled
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction
aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL
are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to
resume conversions.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
133
9.4.7.2
Stop3 Mode With ADACK Enabled
If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For
guaranteed ADC operation, the MCU's voltage regulator must remain active during stop3 mode. Consult
the module introduction for configuration information for this MCU.
If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions
can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous
conversions are enabled.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3
mode if the ADC interrupt is enabled (AIEN = 1).
NOTE
It is possible for the ADC module to wake the system from low power stop
and cause the MCU to begin consuming run-level currents without
generating a system level interrupt. To prevent this scenario, software
should ensure that the data transfer blocking mechanism (discussed in
Section 9.4.4.2, "Completing Conversions
) is cleared when entering stop3
and continuing ADC conversions.
9.4.8
MCU Stop1 and Stop2 Mode Operation
The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module
registers contain their reset values following exit from stop1 or stop2. Therefore the module must be
re-enabled and re-configured following exit from stop1 or stop2.
9.5
Initialization Information
This section is intended to give some basic direction on how a user would initialize and configure the ADC
module. The user has the flexibility of choosing between configuring the module for 8-, 10-, or 12-bit
resolution, single or continuous conversion, and a polled or interrupt approach, among many other options.
The following sections contain an initialization example to aid in the configuration of the ADC module.
NOTE
Hexadecimal values designated by a preceding 0x, binary values designated
by a preceding %, and decimal values have no preceding character.
Refer to
Table 9-6
,
Table 9-7
, and
Table 9-8
for information used in this example.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
134
Freescale Semiconductor
9.5.1
ADC Module Initialization Example
9.5.1.1
Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be carried
out, as follows:
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
9.5.1.2
Pseudo -- Code Example
In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit
conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will
be derived from the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7
ADLPC
1
Configures for low power (lowers maximum clock speed)
Bit 6:5 ADIV
00
Sets the ADCK to the input clock
1
Bit 4
ADLSMP
1
Configures for long sample time
Bit 3:2 MODE
10
Sets mode at 10-bit conversions
Bit 1:0 ADICLK
00
Selects bus clock as input clock source
ADCSC2 = 0x00 (%00000000)
Bit 7
ADACT
0
Flag indicates if a conversion is in progress
Bit 6
ADTRG
0
Software trigger selected
Bit 5
ACFE
0
Compare function disabled
Bit 4
ACFGT
0
Not used in this example
Bit 3:2
00
Unimplemented or reserved, always reads zero
Bit 1:0
00
Reserved for Freescale's internal use; always write zero
ADCSC1 = 0x42 (%01000001)
Bit 7
COCO
0
Read-only flag which is set when a conversion completes
Bit 6
AIEN
1
Conversion complete interrupt enabled
Bit 5
ADCO
0
One conversion only (continuous conversions disabled)
Bit 4:0 ADCH
00001 Input channel 1 selected as ADC input channel
ADCRH/L = 0xxx
Holds results of conversion. Read high byte first (ADCRH) before low byte (ADCRL) so that read data
cannot be overwritten with data from the net conversion.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
135
ADCCVH/L = 0xxx
Holds compare value when compare function enabled
APCTL1=0x02
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins
APCTL2=0x00
All other AD pins remain general purpose I/O pins
Figure 9-14. Initialization Flowchart for Example
9.6
Application Information
This section contains information for using the ADC module in applications. The ADC has been designed
to be integrated into a microcontroller for use in embedded control applications requiring an A/D
converter.
9.6.1
External Pins and Routing
The following sections discuss the external pins associated with the ADC module and how they should be
used for best results.
YES
NO
RESET
INITIALIZE ADC
ADCCFG = $98
ADCSC1 = $42
ADCSC2 = $00
CHECK
COCO=1?
READ ADCRH
THEN ADCRL TO
CLEAR COCO BIT
CONTINUE
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
136
Freescale Semiconductor
9.6.1.1
Analog Supply Pins
The ADC module has analog power and ground supplies (V
DDAD
and V
SSAD
) which are available as
separate pins on some devices. On other devices, V
SSAD
is shared on the same pin as the MCU digital V
SS
,
and on others, both V
SSAD
and V
DDAD
are shared with the MCU digital supply pins. In these cases, there
are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital
supply so that some degree of isolation between the supplies is maintained.
When available on a separate pin, both V
DDAD
and V
SSAD
must be connected to the same voltage potential
as their corresponding MCU digital supply (V
DD
and V
SS
) and must be routed carefully for maximum
noise immunity and bypass capacitors placed as near as possible to the package.
In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies must be at the V
SSAD
pin. This should be the only ground connection between these
supplies if possible. The V
SSAD
pin makes a good single point ground location.
9.6.1.2
Analog Reference Pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The
high reference is V
REFH
, which may be shared on the same pin as V
DDAD
on some devices. The low
reference is V
REFL
, which may be shared on the same pin as V
SSAD
on some devices.
When available on a separate pin, V
REFH
may be connected to the same potential as V
DDAD
, or may be
driven by an external source that is between the minimum V
DDAD
spec and the V
DDAD
potential (V
REFH
must never exceed V
DDAD
). When available on a separate pin, V
REFL
must be connected to the same
voltage potential as V
SSAD
. Both V
REFH
and V
REFL
must be routed carefully for maximum noise
immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive
approximation step is drawn through the V
REFH
and V
REFL
loop. The best external component to meet this
current demand is a 0.1
F capacitor with good high frequency characteristics. This capacitor is connected
between V
REFH
and V
REFL
and must be placed as near as possible to the package pins. Resistance in the
path is not recommended because the current will cause a voltage drop which could result in conversion
errors. Inductance in this path must be minimum (parasitic only).
9.6.1.3
Analog Input Pins
The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control
is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be
performed on inputs without the associated pin control register bit set. It is recommended that the pin
control register bit always be set when using a pin as an analog input. This avoids problems with contention
because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input
buffer draws DC current when its input is not at either V
DD
or V
SS
. Setting the pin control register bits for
all pins used as analog inputs should be done to achieve lowest operating current.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise
or when the source impedance is high. Use of 0.01
F capacitors with good high-frequency characteristics
is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as
possible to the package pins and be referenced to V
SSA
.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
137
For proper conversion, the input voltage must fall between V
REFH
and V
REFL
. If the input is equal to or
exceeds V
REFH
, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF
(full scale 8-bit representation). If the input is equal to or less than V
REFL
, the converter circuit converts it
to $000. Input voltages between V
REFH
and V
REFL
are straight-line linear conversions. There will be a
brief current associated with V
REFL
when the sampling capacitor is charging. The input is sampled for
3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.
9.6.2
Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
9.6.2.1
Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7k
and input capacitance of approximately 5.5 pF, sampling
to within 1/4
LSB
(at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R
AS
) is kept
below 5 k
.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
9.6.2.2
Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (R
AS
) is high.
If this error cannot be tolerated by the application, keep R
AS
lower than V
DDAD
/ (2
N
*I
LEAK
) for less than
1/4
LSB
leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode).
9.6.2.3
Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
There is a 0.1
F low-ESR capacitor from V
REFH
to V
REFL
.
There is a 0.1
F low-ESR capacitor from V
DDAD
to V
SSAD
.
If inductive isolation is used from the primary supply, an additional 1
F capacitor is placed from
V
DDAD
to V
SSAD
.
V
SSAD
(and V
REFL
, if connected) is connected to V
SS
at a quiet point in the ground plane.
Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
-- For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT
instruction or STOP instruction.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
138
Freescale Semiconductor
-- For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V
DD
noise but increases effective conversion time due to stop recovery.
There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V
DD
noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
Place a 0.01
F capacitor (C
AS
) on the selected input channel to V
REFL
or V
SSAD
(this will
improve noise issues but will affect sample rate based on the external analog source resistance).
Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1
LSB
, one-time error.
Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
9.6.2.4
Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10),
defined as 1
LSB
, is:
1
LSB
= (V
REFH
- V
REFL
) / 2
N
Eqn. 9-2
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code will transition when the voltage is at the midpoint between the points where the straight line
transfer function is exactly represented by the actual transfer function. Therefore, the quantization error
will be
1/2
LSB
in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000)
conversion is only 1/2
LSB
and the code width of the last ($FF or $3FF) is 1.5
LSB
.
9.6.2.5
Linearity Errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system should be aware of them because they affect overall accuracy. These errors are:
Zero-scale error (E
ZS
) (sometimes called offset) -- This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2
LSB
). Note, if the first
conversion is $001, then the difference between the actual $001 code width and its ideal (1
LSB
) is
used.
Full-scale error (E
FS
) -- This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5
LSB
). Note, if the last conversion is $3FE, then the
difference between the actual $3FE code width and its ideal (1
LSB
) is used.
Differential non-linearity (DNL) -- This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
139
Integral non-linearity (INL) -- This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual
transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
Total unadjusted error (TUE) -- This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.
9.6.2.6
Code Jitter, Non-Monotonicity and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled
repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the
converter yields the lower code (and vice-versa). However, even very small amounts of system noise can
cause the converter to be indeterminate (between two codes) for a range of input voltages around the
transition voltage. This range is normally around 1/2
LSB
and will increase with noise. This error may be
reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed
in
Section 9.6.2.3
will reduce this error.
Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a
higher input voltage. Missing codes are those values which are never converted for any input value.
In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
140
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
141
Chapter 10
Internal Clock Source (S08ICSV1)
10.1
Introduction
The internal clock source (ICS) module provides clock source choices for the MCU. The module contains
a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external
reference clock. The module can provide this FLL clock or either of the internal or external reference
clocks as a source for the MCU system clock. There are also signals provided to control a low power
oscillator (XOSC) module to allow the use of an external crystal/resonator as the external reference clock.
Whichever clock source is chosen, it is passed through a reduced bus divider (BDIV) which allows a lower
final output clock frequency to be derived.
The bus frequency will be one-half of the ICSOUT frequency.
NOTE
The external reference clock is not available on all packages. See
Table 1-1
for external clock availability for each package option.
10.1.1
Module Configuration
When the internal reference is enabled in stop mode (IREFSTEN = 1), the voltage regulator must also be
enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register.
On this MCU, the internal reference is not connected to any module that is operational in stop mode.
Therefore, the IREFSTEN bit in the ICSC1 register should always be cleared.
Figure 10-1
shows the MC9S08QG8/4 block diagram with the ICS highlighted.
Chapter 10 Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
142
Freescale Semiconductor
Figure 10-1. MC9S08QG8/4 Block Diagram Highlighting ICS Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
PTB7/SCL/EXTAL
POR
T B
PTB6/SDA/XTAL
16-MHz INTERNAL CLOCK
SOURCE (ICS)
EXTAL
XTAL
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
143
10.1.2
Features
Key features of the ICS module are:
Frequency-locked loop (FLL) is trimmable for accuracy
-- 0.2% resolution using internal 32-kHz reference
-- 2% deviation over voltage and temperature using internal 32-kHz reference
Internal or external reference clocks up to 5-MHz can be used to control the FLL
-- 3 bit select for reference divider is provided
Internal reference clock has 9 trim bits available
Internal or external reference clocks can be selected as the clock source for the MCU
Whichever clock is selected as the source can be divided down
-- 2 bit select for clock divider is provided
Allowable dividers are: 1, 2, 4, 8
BDC clock is provided as a constant divide by 2 of the DCO output
Control signals for a low power oscillator as the external reference clock are provided
-- HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
FLL engaged internal mode is automatically selected out of reset
10.1.3
Modes of Operation
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
10.1.3.1
FLL Engaged Interna
l (FEI)
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
10.1.3.2
FLL Engaged External
(FEE)
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock. The BDC clock is supplied from the FLL.
10.1.3.3
FLL Bypassed Interna
l (FBI)
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
10.1.3.4
FLL Bypassed Interna
l Low Power (FBILP)
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
144
Freescale Semiconductor
10.1.3.5
FLL Bypassed Externa
l (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.3.6
FLL Bypassed Externa
l Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.3.7
Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
10.1.4
Block Diagram
Figure 10-2
is the ICS block diagram.
Figure 10-2. Internal Clock Source (ICS) Block Diagram
DCO
Filter
RDIV
TRIM
/ 2
9
External Reference
IREFS
Clock Source
Block
CLKS
n=0-7
/ 2
n
n=0-3
/ 2
n
Internal
Reference
Clock
BDIV
9
ICSLCLK
ICSOUT
ICSIRCLK
EREFS
RANGE
EREFSTEN
HGO
Optional
IREFSTEN
ICSERCLK
Internal Clock Source Block
LP
ICSFFCLK
ERCLKEN
IRCLKEN
DCOOUT
FLL
RDIV_CLK
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
145
10.2
External Signal Description
There are no ICS signals that connect off chip.
10.3
Register Definition
10.3.1
ICS Control Register 1 (ICSC1)
7
6
5
4
3
2
1
0
R
CLKS
RDIV
IREFS
IRCLKEN
IREFSTEN
W
Reset:
0
0
0
0
0
1
0
0
Figure 10-3. ICS Control Register 1 (ICSC1)
Table 10-1. ICS Control Register 1 Field Descriptions
Field
Description
7:6
CLKS
Clock Source Select -- Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
00
Output of FLL is selected.
01
Internal reference clock is selected.
10
External reference clock is selected.
11
Reserved, defaults to 00.
5:3
RDIV
Reference Divider -- Selects the amount to divide down the FLL reference clock selected by the IREFS bits.
Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.
000 Encoding 0 -- Divides reference clock by 1 (reset default)
001 Encoding 1 -- Divides reference clock by 2
010 Encoding 2 -- Divides reference clock by 4
011 Encoding 3 -- Divides reference clock by 8
100 Encoding 4 -- Divides reference clock by 16
101 Encoding 5 -- Divides reference clock by 32
110 Encoding 6 -- Divides reference clock by 64
111 Encoding 7 -- Divides reference clock by 128
2
IREFS
Internal Reference Select -- The IREFS bit selects the reference clock source for the FLL.
1 Internal reference clock selected
0 External reference clock selected
1
IRCLKEN
Internal Reference Clock Enable -- The IRCLKEN bit enables the internal reference clock for use as
ICSIRCLK.
1 ICSIRCLK active
0 ICSIRCLK inactive
0
IREFSTEN
Internal Reference Stop Enable -- The IREFSTEN bit controls whether or not the internal reference clock
remains enabled when the ICS enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before
entering stop
0 Internal reference clock is disabled in stop
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
146
Freescale Semiconductor
10.3.2
ICS Control Register 2 (ICSC2)
7
6
5
4
3
2
1
0
R
BDIV
RANGE
HGO
LP
EREFS
ERCLKEN
EREFSTEN
W
Reset:
0
1
0
0
0
0
0
0
Figure 10-4. ICS Control Register 2 (ICSC2)
Table 10-2. ICS Control Register 2 Field Descriptions
Field
Description
7:6
BDIV
Bus Frequency Divider -- Selects the amount to divide down the clock source selected by the CLKS bits. This
controls the bus frequency.
00
Encoding 0 -- Divides selected clock by 1
01
Encoding 1 -- Divides selected clock by 2 (reset default)
10
Encoding 2 -- Divides selected clock by 4
11
Encoding 3 -- Divides selected clock by 8
5
RANGE
Frequency Range Select -- Selects the frequency range for the external oscillator.
1 High frequency range selected for the external oscillator
0 Low frequency range selected for the external oscillator
4
HGO
High Gain Oscillator Select -- The HGO bit controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
3
LP
Low Power Select -- The LP bit controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes unless BDM is active
0 FLL is not disabled in bypass mode
2
EREFS
External Reference Select -- The EREFS bit selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
1
ERCLKEN
External Reference Enable -- The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
1 ICSERCLK active
0 ICSERCLK inactive
0
EREFSTEN
External Reference Stop Enable -- The EREFSTEN bit controls whether or not the external reference clock
remains enabled when the ICS enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode
before entering stop
0 External reference clock is disabled in stop
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
147
10.3.3
ICS Trim Register (ICSTRM)
10.3.4
ICS Status and Control (ICSSC)
7
6
5
4
3
2
1
0
R
TRIM
W
POR:
1
0
0
0
0
0
0
0
Reset:
U
U
U
U
U
U
U
U
Figure 10-5. ICS Trim Register (ICSTRM)
Table 10-3. ICS Trim Register Field Descriptions
Field
Description
7:0
TRIM
ICS Trim Setting -- The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits' effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
7
6
5
4
3
2
1
0
R
0
0
0
0
CLKST
OSCINIT
FTRIM
W
POR:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-4. ICS Status and Control Register Field Descriptions
Field
Description
7:2
Reserved, should be cleared.
1
OSC Initialization -- If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is cleared only when either ERCLKEN or EREFS are cleared.
0
ICS Fine Trim -- The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
3:2
CLKST
Clock Mode Status -- The CLKST bits indicate the current clock mode. The CLKST bits don't update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
Output of FLL is selected.
01
FLL Bypassed, Internal reference clock is selected.
10
FLL Bypassed, External reference clock is selected.
11
Reserved.
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
148
Freescale Semiconductor
10.4
Functional Description
10.4.1
Operational Modes
Figure 10-7. Clock Switching Modes
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
10.4.1.1
FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
CLKS bits are written to 00
IREFS bit is written to 1
RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=00
Entered from any state
when MCU enters stop
FLL Engaged
Internal (FEI)
FLL Bypassed
Internal (FBI)
FLL Bypassed
External (FBE)
FLL Engaged
External (FEE)
FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=00
IREFS=0
CLKS=10
BDM Enabled
or LP =0
Returns to state that was active
before MCU entered stop, unless
reset occurs while in stop.
IREFS=0
CLKS=10
BDM Disabled
and LP=1
IREFS=1
CLKS=01
BDM Enabled
or LP=0
IREFS=1
CLKS=01
BDM Disabled
and LP=1
Stop
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
149
10.4.1.2
FLL Engaged External (FEE)
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
CLKS bits are written to 00
IREFS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock.The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external
reference clock is enabled.
10.4.1.3
FLL Bypassed Internal (FBI)
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is active or LP bit is written to 0
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the Filter frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC
communications, and the internal reference clock is enabled.
10.4.1.4
FLL Bypassed Internal Low Power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
CLKS bits are written to 01
IREFS bit is written to 1.
BDM mode is not active and LP bit is written to 1
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
10.4.1.5
FLL Bypassed External (FBE)
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is active or LP bit is written to 0.
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL
clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
150
Freescale Semiconductor
times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC
communications, and the external reference clock is enabled.
10.4.1.6
FLL Bypassed External Low Power (FBELP)
The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:
CLKS bits are written to 10.
IREFS bit is written to 0.
BDM mode is not active and LP bit is written to 1.
In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external
reference clock is enabled.
10.4.1.7
Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static
except in the following cases:
ICSIRCLK will be active in stop mode when all the following conditions occur:
IRCLKEN bit is written to 1
IREFSTEN bit is written to 1
ICSERCLK will be active in stop mode when all the following conditions occur:
ERCLKEN bit is written to 1
EREFSTEN bit is written to 1
10.4.2
Mode Switching
When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS
bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting
frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will
begin locking again after a few full cycles of the resulting divided reference frequency.
The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that
the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly
selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is
not available, the previous clock will remain selected.
10.4.3
Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
151
10.4.4
Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not
being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for
maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0.
10.4.5
Internal Reference Clock
When IRCLKEN is set the internal reference clock signal will be presented as ICSIRCLK, which can be
used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM
register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to
the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT
frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed
internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset.
Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT
frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing
specifications (see the
Device Overview
chapter).
If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value can
be copied to the ICSTRM register during reset initialization. The factory trim value does not include the
FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the
FTRIM bit accordingly.
10.4.6
Optional External Reference Clock
The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz
in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as
ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can
be equal to the maximum frequency the chip-level timing specifications will support (see the
Device
Overview
chapter).
If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
152
Freescale Semiconductor
10.4.7
Fixed Frequency Clock
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for
peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is
providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK).
In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS bypass modes,
ICSFFE will get asserted for the following combinations of BDIV and RDIV values:
BDIV=00 (divide by 1), RDIV
010
BDIV=01 (divide by 2), RDIV
011
BDIV=10 (divide by 4), RDIV
100
BDIV=11 (divide by 8), RDIV
101
10.5
Module Initialization
This section describes how to initialize and configure the ICS module. The following sections contain two
initialization examples.
10.5.1
ICS Module Initialization Sequence
The ICS comes out of POR configured for FEI mode with the BDIV set for divide-by 2. The internal
reference will stabilize in t
IRST
microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL will acquire lock in t
Acquire
milliseconds.
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the ICSSC register,
and 0xFFAF for storing the 8-bit trim value for the ICSTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
NOTE
The BDIV value should not be changed to divide-by 1 without first
trimming the internal reference. Failure to do so could result in the MCU
running out of specification.
10.5.1.1
Initialization Sequence, Internal Clock Mode to External Clock Mode
To change from FEI or FBI clock modes to FEE or FBE clock modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in ICSC2.
-- If FBE will be the selected mode, also set the LP bit at this time to minimize power
consumption.
2. If necessary, wait for the external clock source to stabilize. Typical crystal startup times are given
in
Appendix A, "Electrical Characteristics
." If EREFS is set in step 1, then the OSCINIT bit will
set as soon as the oscillator has completed the initialization cycles.
3. Write to ICSC1 to select the clock mode.
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
153
-- If entering FEE, set the reference divider and clear the IREFS bit to switch to the external
reference.
-- The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
useful if the application will switch back and forth between internal clock and external clock
modes. For minimum power consumption, leave the internal reference disabled while in an
external clock mode.
4. The CLKST bits can be monitored to determine when the mode switch has completed. If FEE was
selected, the bus clock will be stable in t
Acquire
milliseconds. The CLKST bits will not change when
switching from FEI to FEE.
10.5.1.2
Initialization Sequence, External Clock Mode to Internal Clock Mode
To change from FEE or FBE clock modes to FEI or FBI clock modes, follow this procedure:
1. If saved, copy the TRIM and FTRIM values from FLASH to the ICSTRM and ICSSC registers.
This needs to be done only once after POR.
2. Enable the internal clock reference by selecting FBI (CLKS = 0:1) or selecting FEI (CLKS = 0:0,
RDIV = 0:0:0, and IREFS = 1) in ICSC1.
3. Wait for the internal clock reference to stabilize. The typical startup time is given in
Appendix A,
"Electrical Characteristics
."
4. Write to ICSC2 to disable the external clock.
-- The external reference can optionally be kept running by setting the ERCLKEN bit. This is
useful if the application will switch back and forth between internal clock and external clock
modes. For minimum power consumption, leave the external reference disabled while in an
internal clock mode.
-- If FBI will be the selected mode, also set the LP bit at this time to minimize power
consumption.
NOTE
The internal reference must be enabled and running before disabling the
external clock. Therefore it is imperative to execute steps 2 and 3 before
step 4.
5. The CLKST bits in the ICSSC register can be monitored to determine when the mode switch has
completed. The CLKST bits will not change when switching from FEE to FEI. If FEI was selected,
the bus clock will be stable in t
Acquire
milliseconds.
Internal Clock Source (S08ICSV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
154
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
155
Chapter 11
Inter-Integrated Circuit (S08IICV1)
11.1
Introduction
The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The
interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
11.1.1
Module Configuration
The IIC module pins, SDA and SCL can be repositioned under software control using IICPS in SOPT2 as
as shown in
Table 11-1
. IICPS in SOPT2 selects which general-purpose I/O ports are associated with IIC
operation.
Figure 11-1
is the MC9S08QG8/4 block diagram with the IIC block highlighted.
Table 11-1. IIC Position Options
IICPS in SOPT2
Port Pin for SDA
Port Pin for SCL
0 (default)
PTA2
PTA3
1
PTB6
PTB7
Chapter 11 Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
156
Freescale Semiconductor
Figure 11-1. MC9S08QG8/4 Block Diagram Highlighting IIC Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Chapter 11 Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
157
Figure 11-2. IIC Module Quick Start
Module Initialization (Slave)
1.
Write: IICA
--
to set the slave address
2.
Write: IICC
--
to enable IIC and interrupts
3.
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4.
Initialize RAM variables used to achieve the routine shown in
Figure 11-3
Module Initialization (Master)
1.
Write: IICF
--
to set the IIC baud rate (example provided in this chapter)
2.
Write: IICC
--
to enable IIC and interrupts
3.
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
4.
Initialize RAM variables used to achieve the routine shown in
Figure 11-3
5.
Write: IICC
--
to enable TX
6.
Write: IICC
--
to enable MST (master mode)
7.
Write: IICD
--
with the address of the target slave. (The LSB of this byte will determine whether the communication is
master receive or transmit.)
Module Use
The routine shown in
Figure 11-3
can handle both master and slave IIC operations. For slave operation, an
incoming IIC message that contains the proper address will begin IIC communication. For master operation,
communication must be initiated by writing to the IICD register.
0
IICF
IICA
Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER))
TX
TXAK
RSTA
0
0
IICC
IICEN
IICIE
MST
Module configuration
ARBL
0
SRW
IICIF
RXAK
IICS
TCF
IAAS
BUSY
Module status flags
Register Model
ADDR
Address to which the module will respond when addressed as a slave (in slave mode)
MULT
ICR
IICD
DATA
Data register; Write to transmit IIC data read to read IIC data
Chapter 11 Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
158
Freescale Semiconductor
Figure 11-3. Typical IIC Interrupt Routine
Clear
Master
Mode
?
Tx/Rx
?
Last Byte
Transmitted
?
RXAK=0
?
End of
Addr Cycle
(Master Rx)
?
Write Next
Byte to IICD
Switch to
Rx Mode
Dummy Read
from IICD
Generate
Stop Signal
Read Data
from IICD
and Store
Set NACK =1
Generate
Stop Signal
2nd Last
Byte to Be Read
?
Last
Byte to Be Read
?
Arbitration
Lost
?
Clear ARBL
IAAS=1
?
IAAS=1
?
SRW=1
?
TX/RX
?
Set TX
Mode
Write Data
to IBDR
Set RX
Mode
Dummy Read
from IICD
ACK from
Receiver
?
Tx Next
Byte
Read Data
from IICD
and Store
Switch to
Rx Mode
Dummy Read
from IICD
RTI
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
Y
TX
RX
RX
TX
(Write)
(Read)
N
IICIF
Address Transfer
Data Transfer
(MST = 0)
(MST = 0)
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
159
11.1.2
Features
The IIC includes these distinctive features:
Compatible with IIC bus standard
Multi-master operation
Software programmable for one of 64 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus busy detection
11.1.3
Modes of Operation
The IIC functions the same in normal and monitor modes. A brief description of the IIC in the various
MCU modes is given here.
Run mode -- This is the basic mode of operation. To conserve power in this mode, disable the
module.
Wait mode -- The module will continue to operate while the MCU is in wait mode and can provide
a wake-up interrupt.
Stop mode -- The IIC is inactive in stop3 mode for reduced power consumption. The STOP
instruction does not affect IIC register states. Stop1 and stop2 will reset the register contents.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
160
Freescale Semiconductor
11.1.4
Block Diagram
Figure 11-4
is a block diagram of the IIC.
Figure 11-4. IIC Functional Block Diagram
11.2
External Signal Description
This section describes each user-accessible pin signal.
11.2.1
SCL -- Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
11.2.2
SDA -- Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
11.3
Register Definition
This section consists of the IIC register descriptions in address order.
INPUT
SYNC
IN/OUT
DATA
SHIFT
REGISTER
ADDRESS
COMPARE
INTERRUPT
CLOCK
CONTROL
START
STOP
ARBITRATION
CONTROL
CTRL_REG
FREQ_REG
ADDR_REG
STATUS_REG
DATA_REG
ADDR_DECODE
DATA_MUX
DATA BUS
SCL
SDA
ADDRESS
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
161
Refer to the direct-page register summary in the
Memory
chapter of this data sheet for the absolute address
assignments for all IIC registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
11.3.1
IIC Address Register (IICA)
11.3.2
IIC Frequency Divider Register (IICF)
7
6
5
4
3
2
1
0
R
ADDR
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-5. IIC Address Register (IICA)
Table 11-2. IICA Register Field Descriptions
Field
Description
7:1
ADDR[7:1]
IIC Address Register -- The ADDR contains the specific slave address to be used by the IIC module. This is
the address the module will respond to when addressed as a slave.
7
6
5
4
3
2
1
0
R
MULT
ICR
W
Reset
0
0
0
0
0
0
0
0
Figure 11-6. IIC Frequency Divider Register (IICF)
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
162
Freescale Semiconductor
Table 11-3. IICA Register Field Descriptions
Field
Description
7:6
MULT
IIC Multiplier Factor -- The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0
ICR
IIC Clock Rate -- The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to
define the SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT
register (multiplier factor mul) is used to generate IIC baud rate.
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC data). The
ICR is used to determine the SDA hold value.
SDA hold time = bus period (s) * SDA hold value
Table 11-4
provides the SCL divider and SDA hold values for corresponding values of the ICR. These values can
be used to set IIC baud rate and SDA hold time. For example:
Bus speed = 8 MHz
MULT is set to 01 (mul = 2)
Desired IIC baud rate = 100 kbps
IIC baud rate = bus speed (Hz)/(mul * SCL divider)
100000 = 8000000/(2*SCL divider)
SCL divider = 40
Table 11-4
shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result in an SDA
hold value of 9.
SDA hold time = bus period (s) * SDA hold value
SDA hold time = 1/8000000 * 9 = 1.125
s
If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This will result
in a different SDA hold value.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
163
Table 11-4. IIC Divider and Hold Values
ICR
(hex)
SCL Divider
SDA Hold
Value
ICR
(hex)
SCL Divider
SDA Hold
Value
00
20
7
20
160
17
01
22
7
21
192
17
02
24
8
22
224
33
03
26
8
23
256
33
04
28
9
24
288
49
05
30
9
25
320
49
06
34
10
26
384
65
07
40
10
27
480
65
08
28
7
28
320
33
09
32
7
29
384
33
0A
36
9
2A
448
65
0B
40
9
2B
512
65
0C
44
11
2C
576
97
0D
48
11
2D
640
97
0E
56
13
2E
768
129
0F
68
13
2F
960
129
10
48
9
30
640
65
11
56
9
31
768
65
12
64
13
32
896
129
13
72
13
33
1024
129
14
80
17
34
1152
193
15
88
17
35
1280
193
16
104
21
36
1536
257
17
128
21
37
1920
257
18
80
9
38
1280
129
19
96
9
39
1536
129
1A
112
17
3A
1792
257
1B
128
17
3B
2048
257
1C
144
25
3C
2304
385
1D
160
25
3D
2560
385
1E
192
33
3E
3072
513
1F
240
33
3F
3840
513
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
164
Freescale Semiconductor
11.3.3
IIC Control Register (IICC)
7
6
5
4
3
2
1
0
R
IICEN
IICIE
MST
TX
TXAK
0
0
0
W
RSTA
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-7. IIC Control Register (IICC)
Table 11-5. IICC Register Field Descriptions
Field
Description
7
IICEN
IIC Enable -- The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
6
IICIE
IIC Interrupt Enable -- The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
5
MST
Master Mode Select -- The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave Mode.
1 Master Mode.
4
TX
Transmit Mode Select -- The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
3
TXAK
Transmit Acknowledge Enable -- This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
0 An acknowledge signal will be sent out to the bus after receiving one data byte.
1 No acknowledge signal response is sent.
2
RSTA
Repeat START -- Writing a one to this bit will generate a repeated START condition provided it is the current
master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
165
11.3.4
IIC Status Register (IICS)
7
6
5
4
3
2
1
0
R
TCF
IAAS
BUSY
ARBL
0
SRW
IICIF
RXAK
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-8. IIC Status Register (IICS)
Table 11-6. IICS Register Field Descriptions
Field
Description
7
TCF
Transfer Complete Flag -- This bit is set on the completion of a byte transfer. Note that this bit is only valid
during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by
reading the IICD register in receive mode or writing to the IICD in transmit mode.
0 Transfer in progress.
1 Transfer complete.
6
IAAS
Addressed as a Slave -- The IAAS bit is set when its own specific address is matched with the calling address.
Writing the IICC register clears this bit.
0 Not addressed.
1 Addressed as a slave.
5
BUSY
Bus Busy -- The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is
set when a START signal is detected and cleared when a STOP signal is detected.
0 Bus is idle.
1 Bus is busy.
4
ARBL
Arbitration Lost -- This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be
cleared by software, by writing a one to it.
0 Standard bus operation.
1 Loss of arbitration.
2
SRW
Slave Read/Write -- When addressed as a slave the SRW bit indicates the value of the R/W command bit of
the calling address sent to the master.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
1
IICIF
IIC Interrupt Flag -- The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a one to it in the interrupt routine. One of the following events can set the IICIF bit:
One byte transfer completes
Match of slave address to calling address
Arbitration lost
0 No interrupt pending.
1 Interrupt pending.
0
RXAK
Receive Acknowledge -- When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received.
1 No acknowledge received.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
166
Freescale Semiconductor
11.3.5
IIC Data I/O Register (IICD)
NOTE
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IICD will not initiate the receive.
Reading the IICD will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IICD does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7bit 1) concatenated with the required
R/W bit (in position bit 0).
7
6
5
4
3
2
1
0
R
DATA
W
Reset
0
0
0
0
0
0
0
0
Figure 11-9. IIC Data I/O Register (IICD)
Table 11-7. IICD Register Field Descriptions
Field
Description
7:0
DATA
Data -- In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
167
11.4
Functional Description
This section provides a complete functional description of the IIC module.
11.4.1
IIC Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
START signal
Slave address transmission
Data transfer
STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and illustrated in
Figure 11-10
.
Figure 11-10. IIC Bus Transmission Signals
SCL
SDA
START
SIGNAL
ACK
BIT
1
2
3
4
5
6
7
8
MSB
LSB
1
2
3
4
5
6
7
8
MSB
LSB
STOP
SIGNAL
NO
SCL
SDA
1
2
3
4
5
6
7
8
MSB
LSB
1
2
5
6
7
8
MSB
LSB
REPEATED
3
4
9
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
CALLING ADDRESS
READ/
DATA BYTE
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
NEW CALLING ADDRESS
9
9
XX
ACK
BIT
WRITE
START
SIGNAL
START
SIGNAL
ACK
BIT
CALLING ADDRESS
READ/
WRITE
STOP
SIGNAL
NO
ACK
BIT
READ/
WRITE
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
168
Freescale Semiconductor
11.4.1.1
START Signal
When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in
Figure 11-10
, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
11.4.1.2
Slave Address Transmission
The first byte of data transferred immediately after the START signal is the slave address transmitted by
the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master will respond by
sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see
Figure 11-10
).
No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit
an address that is equal to its own slave address. The IIC cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle, the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
11.4.1.3
Data Transfer
Before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction
specified by the R/W bit sent by the calling master.
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in
Figure 11-10
. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte is followed by a 9th (acknowledge) bit, which is signalled from the
receiving device. An acknowledge is signalled by pulling the SDA low at the ninth clock. In summary, one
complete data transfer needs nine clock pulses.
If the slave receiver does not acknowledge the master in the 9th bit time, the SDA line must be left high
by the slave. The master interprets the failed acknowledge as an unsuccessful data transfer.
If the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave
interprets this as an end of data transfer and releases the SDA line.
In either case, the data transfer is aborted and the master does one of two things:
Relinquishes the bus by generating a STOP signal.
Commences a new calling by generating a repeated START signal.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
169
11.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logical 1 (see
Figure 11-10
).
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
11.4.1.5
Repeated START Signal
As shown in
Figure 11-10
, a repeated START signal is a START signal generated without first generating
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
11.4.1.6
Arbitration Procedure
The IIC bus is a true multi-master bus that allows more than one master to be connected on it. If two or
more masters try to control the bus at the same time, a clock synchronization procedure determines the bus
clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest
one among the masters. The relative priority of the contending masters is determined by a data arbitration
procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The
losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is
set by hardware to indicate loss of arbitration.
11.4.1.7
Clock Synchronization
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device's clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is still within its
low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see
Figure 11-11
). When all
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
170
Freescale Semiconductor
Figure 11-11. IIC Clock Synchronization
11.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
11.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
11.5
Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
11.6
Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
Table 11-8
occur provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.
The user can determine the interrupt type by reading the status register.
Table 11-8. Interrupt Summary
Interrupt Source
Status
Flag
Local Enable
Complete 1-byte transfer
TCF
IICIF
IICIE
Match of received calling address
IAAS
IICIF
IICIE
Arbitration Lost
ARBL
IICIF
IICIE
SCL1
SCL2
SCL
INTERNAL COUNTER RESET
DELAY
START COUNTING HIGH PERIOD
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
171
11.6.1
Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of
byte transfer.
11.6.2
Address Detect Interrupt
When its own specific address (IIC address register) is matched with the calling address, the IAAS bit in
status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit
and set its Tx mode accordingly.
11.6.3
Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
SDA sampled as a low when the master drives a high during an address or data transmit cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
A START cycle is attempted when the bus is busy.
A repeated START cycle is requested in slave mode.
A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a one to it.
Inter-Integrated Circuit (S08IICV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
172
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
173
Chapter 12
Keyboard Interrupt (S08KBIV2)
12.1
Introduction
The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources.
Figure 12-1
Shows the MC9S08QG8/4 block guide with the KBI highlighted.
Chapter 12 Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
174
Freescale Semiconductor
Figure 12-1. MC9S08QG8/4 Block Diagram Highlighting KBI Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
175
12.1.1
Features
The KBI features include:
Up to eight keyboard interrupt pins with individual pin enable bits.
Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling
edge and low level (or both rising edge and high level) interrupt sensitivity.
One software enabled keyboard interrupt.
Exit from low-power modes.
12.1.2
Modes of Operation
This section defines the KBI operation in wait, stop, and background debug modes.
12.1.2.1
KBI in Wait Mode
The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore,
an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is
enabled (KBIE = 1).
12.1.2.2
KBI in Stop Modes
The KBI operates asynchronously in stop3 mode if enabled before executing the STOP instruction.
Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of stop3 mode if the KBI
interrupt is enabled (KBIE = 1).
During either stop1 or stop2 mode, the KBI is disabled. In some systems, the pins associated with the KBI
may be sources of wakeup from stop1 or stop2, see the stop modes section in the
Modes of Operation
chapter. Upon wake-up from stop1 or stop2 mode, the KBI module will be in the reset state.
12.1.2.3
KBI in Active Background Mode
When the microcontroller is in active background mode, the KBI will continue to operate normally.
12.1.3
Block Diagram
The block diagram for the keyboard interrupt module is shown
Figure
12-2
.
Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
176
Freescale Semiconductor
Figure
12-2. Keyboard Interrupt (KBI) Block Diagram
12.2
External Signal Description
The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt
requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high
level interrupt requests.
The signal properties of KBI are shown in
Table
12-1
.
Table
12-1. Signal Properties
Signal
Function
I/O
KBIPn
Keyboard interrupt pins
I
D
Q
CK
CLR
V
DD
KBMOD
KBIE
KEYBOARD
INTERRUPT FF
KBACK
RESET
SYNCHRONIZER
KBF
STOP BYPASS
STOP
BUSCLK
KBIPEn
0
1
S
KBEDGn
KBIPE0
0
1
S
KBEDG0
KBIP0
KBIPn
KBI
INTERRUPT
REQUES
T
Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
177
12.3
Register Definition
The KBI includes three registers:
An 8-bit pin status and control register.
An 8-bit pin enable register.
An 8-bit edge select register.
Refer to the direct-page register summary in the
Memory
chapter for the absolute address assignments for
all KBI registers. This section refers to registers and control bits only by their names and relative address
offsets.
Some MCUs may have more than one KBI, so register names include placeholder characters to identify
which KBI is being referenced.
12.3.1
KBI Status and Control Register (
KBI
SC)
KBISC contains the status flag and control bits, which are used to configure the KBI.
12.3.2
KBI Pin Enable Register (KBIPE)
KBIPE contains the pin enable control bits.
7
6
5
4
3
2
1
0
R
0
0
0
0
KBF
0
KBIE
KBMOD
W
KBACK
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure
12-3. KBI
Status and Control Register
Table
12-2. KBISC Register Field Descriptions
Field
Description
7:4
Unused register bits, always read 0.
3
KBF
Keyboard Interrupt Flag -- KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF.
0 No keyboard interrupt detected.
1 Keyboard interrupt detected.
2
KBACK
Keyboard Acknowledge -- Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads
as 0.
1
KBIE
Keyboard Interrupt Enable -- KBIE determines whether a keyboard interrupt is requested.
0 Keyboard interrupt request not enabled.
1 Keyboard interrupt request enabled.
0
KBMOD
Keyboard Detection Mode -- KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard
interrupt pins.0Keyboard detects edges only.
1 Keyboard detects both edges and levels.
Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
178
Freescale Semiconductor
12.3.3
KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.
12.4
Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was
designed to simplify the connection and use of row-column matrices of keyboard switches. However, these
inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from
stop or wait low-power modes.
The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPEn bits
in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin.
Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in
the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to
be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level
sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES).
7
6
5
4
3
2
1
0
R
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
W
Reset:
0
0
0
0
0
0
0
0
Figure
12-4. KBI Pin Enable Register
Table
12-3. KBIPE Register Field Descriptions
Field
Description
7:0
KBIPEn
Keyboard Pin Enables -- Each of the KBIPEn bits enable the corresponding keyboard interrupt pin.
0 Pin not enabled as keyboard interrupt.
1 Pin enabled as keyboard interrupt.
7
6
5
4
3
2
1
0
R
KBEDG7
KBEDG6
KBEDG5
KBEDG4
KBEDG3
KBEDG2
KBEDG1
KBEDG0
W
Reset:
0
0
0
0
0
0
0
0
Figure
12-5. KBI Edge Select Register
Table
12-4. KBIES Register Field Descriptions
Field
Description
7:0
KBEDGn
Keyboard Edge Selects -- Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level
function of the corresponding pin).
0 Falling edge/low level.
1 Rising edge/high level.
Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
179
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs must be at
the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a
logic 1 (the deasserted level) during one bus cycle and then a logic
0 (the asserted level) during the next
cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a
logic 1 during the next cycle.
12.4.1
Edge Only Sensitivity
A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request
will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC.
12.4.2
Edge and Level Sensitivity
A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt
request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in
KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any
enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK.
12.4.3
KBI Pullup/Pulldown Resistors
The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port
pullup enable register. If an internal resistor is enabled, the KBIES register is used to select whether the
resistor is a pullup (KBEDGn = 0) or a pulldown (KBEDGn = 1).
12.4.4
KBI Initialization
When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To prevent
a false interrupt request during keyboard initialization, the user should do the following:
1. Mask keyboard interrupts by clearing KBIE in KBISC.
2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES.
3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE.
4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE.
5. Write to KBACK in KBISC to clear any false interrupts.
6. Set KBIE in KBISC to enable interrupts.
Keyboard Interrupt (S08KBIV2)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
180
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
181
Chapter 13
Modulo Timer (S08MTIMV1)
13.1
Introduction
The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable
interrupt.
The central component of the MTIM is the 8-bit counter, which can operate as a free-running counter or a
modulo counter. A timer overflow interrupt can be enabled to generate periodic interrupts for time-based
software loops.
Figure 13-1
shows the MC9S08QG8/4 block diagram with the MTIM highlighted.
13.1.1
MTIM/TPM Configuration Information
The external clock for the MTIM module, TCLK, is selected by setting CLKS = 1:1 or 1:0 in MTIMCLK,
which selects the TCLK pin input. The TCLK input on PTA5 can be enabled as external clock inputs to
both the MTIM and TPM modules simultaneously.
Chapter 13 Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
182
Freescale Semiconductor
Figure 13-1. MC9S08QG8/4 Block Diagram Highlighting MTIM Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
183
13.1.2
Features
Timer system features include:
8-bit up-counter
-- Free-running or 8-bit modulo limit
-- Software controllable interrupt on overflow
-- Counter reset bit (TRST)
-- Counter stop bit (TSTP)
Four software selectable clock sources for input to prescaler:
-- System bus clock -- rising edge
-- Fixed frequency clock (XCLK) -- rising edge
-- External clock source on the TCLK pin -- rising edge
-- External clock source on the TCLK pin -- falling edge
Nine selectable clock prescale values:
-- Clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256
13.1.3
Modes of Operation
This section defines the MTIM's operation in stop, wait and background debug modes.
13.1.3.1
MTIM in Wait Mode
The MTIM continues to run in wait mode if enabled before executing the WAIT instruction. Therefore, the
MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled. For lowest
possible current consumption, the MTIM should be stopped by software if not needed as an interrupt
source during wait mode.
13.1.3.2
MTIM in Stop Modes
The MTIM is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
Therefore, the MTIM cannot be used as a wake up source from stop modes.
Waking from stop1 and stop2 modes, the MTIM will be put into its reset state. If stop3 is exited with a
reset, the MTIM will be put into its reset state. If stop3 is exited with an interrupt, the MTIM continues
from the state it was in when stop3 was entered. If the counter was active upon entering stop3, the count
will resume from the current value.
13.1.3.3
MTIM in Active Background Mode
The MTIM suspends all counting until the microcontroller returns to normal user operating mode.
Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written to a 1
or
MTIM
MOD written).
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
184
Freescale Semiconductor
13.1.4
Block Diagram
The block diagram for the modulo timer module is shown
Figure 13-2
.
Figure 13-2. Modulo Timer (MTIM) Block Diagram
13.2
External Signal Description
The MTIM includes one external signal, TCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TCLK are shown in
Table 13-1
.
The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter must
be accommodated. Therefore, the TCLK signal must be limited to one-fourth of the bus frequency.
The TCLK pin can be muxed with a general-purpose port pin. See the
Pins and Connections
chapter for
the pin location and priority of this function.
13.3
Register Definition
Each MTIM includes four registers:
An 8-bit status and control register
An 8-bit clock configuration register
An 8-bit counter register
An 8-bit modulo register
Refer to the direct-page register summary in the
Memory
chapter of this data sheet for the absolute address
assignments for all MTIM registers. This section refers to registers and control bits only by their names
and relative address offsets.
Some MCUs may have more than one MTIM, so register names include placeholder characters to identify
which MTIM is being referenced.
Table 13-1. Signal Properties
Signal
Function
I/O
TCLK
External clock source input into MTIM
I
BUSCLK
TCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALE AND
SELECT DIVIDE
BY
8-BIT COUNTER
(MTIMCNT)
8-BIT MODULO
(MTIMMOD)
8-BIT COMPARATOR
TRST
TSTP
CLKS
PS
XCLK
TOIE
MTIM
INTERRUPT
REQUEST
TOF
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
185
13.3.1
MTIM Status and Control Register (MTIMSC)
MTIM
SC contains the overflow status flag and control bits, which are used to configure the interrupt enable,
reset the counter, and stop the counter.
7
6
5
4
3
2
1
0
R
TOF
TOIE
0
TSTP
0
0
0
0
W
TRST
Reset:
0
0
0
1
0
0
0
0
Figure 13-3. MTIM Status and Control Register
Table 13-2. MTIM Status and Control Register Field Descriptions
Field
Description
7
TOF
MTIM Overflow Flag -- This read-only bit is set when the MTIM counter register overflows to 0x00 after reaching
the value in the MTIM modulo register. Clear TOF by reading the MTIMSC register while TOF is set, then writing
a 0 to TOF. TOF is also cleared when TRST is written to a 1 or when any value is written to the MTIMMOD register.
0 MTIM counter has not reached the overflow value in the MTIM modulo register.
1 MTIM counter has reached the overflow value in the MTIM modulo register.
6
TOIE
MTIM Overflow Interrupt Enable -- This read/write bit enables MTIM overflow interrupts. If TOIE is set, then an
interrupt is generated when TOF = 1. Reset clears TOIE. Do not set TOIE if TOF = 1. Clear TOF first, then set TOIE.
0 TOF interrupts are disabled. Use software polling.
1 TOF interrupts are enabled.
5
TRST
MTIM Counter Reset -- When a 1 is written to this write-only bit, the MTIM counter register resets to 0x00 and
TOF is cleared. Reading this bit always returns 0.
0 No effect. MTIM counter remains at current state.
1 MTIM counter is reset to 0x00.
4
TSTP
MTIM Counter Stop -- When set, this read/write bit stops the MTIM counter at its current value. Counting resumes
from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting.
0 MTIM counter is active.
1 MTIM counter is stopped.
3:0
Unused register bits, always read 0.
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
186
Freescale Semiconductor
13.3.2
MTIM Clock Configuration Register (MTIMCLK)
MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS).
7
6
5
4
3
2
1
0
R
0
0
CLKS
PS
W
Reset:
0
0
0
0
0
0
0
0
Figure 13-4. MTIM Clock Configuration Register
Table 13-3. MTIM Clock Configuration Register Field Description
Field
Description
7:6
Unused register bits, always read 0.
5:4
CLKS
Clock Source Select -- These two read/write bits select one of four different clock sources as the input to the
MTIM prescaler. Changing the clock source while the counter is active does not clear the counter. The count
continues with the new clock source. Reset clears CLKS to 00.
00
Encoding 0. Bus clock (BUSCLK)
01
Encoding 1. Fixed-frequency clock (XCLK)
10
Encoding 2. External source (TCLK pin), falling edge
11
Encoding 3. External source (TCLK pin), rising edge
3:0
PS
Clock Source Prescaler -- These four read/write bits select one of nine outputs from the 8-bit prescaler.
Changing the prescaler value while the counter is active does not clear the counter. The count continues with the
new prescaler value. Reset clears PS to 0000.
0000 Encoding 0. MTIM clock source
1
0001 Encoding 1. MTIM clock source
2
0010 Encoding 2. MTIM clock source
4
0011 Encoding 3. MTIM clock source
8
0100 Encoding 4. MTIM clock source
16
0101 Encoding 5. MTIM clock source
32
0110 Encoding 6. MTIM clock source
64
0111 Encoding 7. MTIM clock source
128
1000 Encoding 8. MTIM clock source
256
All other encodings default to MTIM clock source
256.
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
187
13.3.3
MTIM Counter Register (MTIMCNT)
MTIM
CNT is the read-only value of the current MTIM count.
13.3.4
MTIM Modulo Register (MTIMMOD)
7
6
5
4
3
2
1
0
R
COUNT
W
Reset:
0
0
0
0
0
0
0
0
Figure 13-5. MTIM Counter Register
Table 13-4. MTIM Counter Register Field Description
Field
Description
7:0
COUNT
MTIM Count -- These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to
this register. Reset clears the count to 0x00.
7
6
5
4
3
2
1
0
R
MOD
W
Reset:
0
0
0
0
0
0
0
0
Figure 13-6. MTIM Modulo Register
Table 13-5.
MTIM
Modulo Register Field Descriptions
Field
Description
7:0
MOD
MTIM Modulo -- These eight read/write bits contain the modulo value used to reset the count and set TOF. A value
of 0x00 puts the MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to 0x00 and clears TOF.
Reset sets the modulo to 0x00.
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
188
Freescale Semiconductor
13.4
Functional Description
The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector,
and a prescaler block with nine selectable values. The module also contains software selectable interrupt
logic.
The MTIM counter (
MTIM
CNT) has three modes of operation: stopped, free-running, and modulo. Out of
reset, the counter is stopped. If the counter is started without writing a new value to the modulo register,
then the counter will be in free-running mode. The counter is in modulo mode when a value other than
0x00 is in the modulo register while the counter is running.
After any MCU reset, the counter is stopped and reset to 0x00, and the modulus is set to 0x00. The bus
clock is selected as the default clock source and the prescale value is divide by 1. To start the MTIM in
free-running mode, simply write to the MTIM status and control register (
MTIM
SC) and clear the MTIM
stop bit (TSTP).
Four clock sources are software selectable: the internal bus clock, the fixed frequency clock (XCLK), and
an external clock on the TCLK pin, selectable as incrementing on either rising or falling edges. The MTIM
clock select bits (CLKS1:CLKS0) in
MTIM
SC are used to select the desired clock source. If the counter is
active (TSTP = 0) when a new clock source is selected, the counter will continue counting from the
previous value using the new clock source.
Nine prescale values are software selectable: clock source divided by 1, 2, 4, 8, 16, 32, 64, 128, or 256.
The prescaler select bits (PS[3:0]) in
MTIM
SC select the desired prescale value. If the counter is active
(TSTP = 0) when a new prescaler value is selected, the counter will continue counting from the previous
value using the new prescaler value.
The MTIM modulo register (
MTIM
MOD) allows the overflow compare value to be set to any value from
0x01 to 0xFF. Reset clears the modulo value to 0x00, which results in a free running counter.
When the counter is active (TSTP = 0), the counter increments at the selected rate until the count matches
the modulo value. When these values match, the counter overflows to 0x00 and continues counting. The
MTIM overflow flag (TOF) is set whenever the counter overflows. The flag sets on the transition from the
modulo value to 0x00. Writing to
MTIM
MOD while the counter is active resets the counter to 0x00 and
clears TOF.
Clearing TOF is a two-step process. The first step is to read the
MTIM
SC register while TOF is set. The
second step is to write a 0 to TOF. If another overflow occurs between the first and second steps, the
clearing process is reset and TOF will remain set after the second step is performed. This will prevent the
second occurrence from being missed. TOF is also cleared when a 1 is written to TRST or when any value
is written to the
MTIM
MOD register.
The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM
overflow interrupt, set the MTIM overflow interrupt enable bit (TOIE) in
MTIM
SC. TOIE should never be
written to a 1 while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1.
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
189
13.4.1
MTIM Operation Example
This section shows an example of the MTIM operation as the counter reaches a matching value from the
modulo register.
Figure 13-7. MTIM counter overflow example
In the example of
Figure 13-7
, the selected clock source could be any of the five possible choices. The
prescaler is set to PS = %0010 or divide-by-4. The modulo value in the
MTIM
MOD register is set to 0xAA.
When the counter,
MTIM
CNT, reaches the modulo value of 0xAA, the counter overflows to 0x00 and
continues counting. The timer overflow flag, TOF, sets when the counter value changes from 0xAA to
0x00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1.
selected
clock source
MTIMCNT
MTIM clock
(PS=%0010)
MTIMMOD:
0xA
0xA7
0xA8
0xA9
0xAA
0x00
0x01
TOF
Modulo Timer (S08MTIMV1)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
190
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
191
Chapter 14
Serial Communications Interface (S08SCIV3)
14.1
Introduction
Figure 14-1
shows the MC9S08QG8/4 block diagram with the SCI highlighted.
Chapter 14 Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
192
Freescale Semiconductor
Figure 14-1. MC9S08QG8/4 Block Diagram Highlighting SCI Block and Pins
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
Chapter 14 Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
193
Figure 14-2. SCI Module Quick Start
SBR12
SBR11
SBR10
SBR9
SBR8
SBR4
SBR3
SBR2
SBR1
SBR0
SBR7
SBR6
SBR5
SCIBDL
SCIBDH
Baud rate = BUSCLK / (16 x SBR12:SBR0)
M
WAKE
ILT
PE
PT
SCIC1
LOOPS
SCISWAI
RSRC
Module configuration
ILIE
TE
RE
RWU
SBK
SCIC2
TIE
TCIE
RIE
Local interrupt enables Tx and Rx enable
Rx wakeup and send break
IDLE
OR
NF
FE
PF
SCIS1
TDRE
TC
RDRF
Interrupt flags
Rx error flags
BRK13
RAF
SCIS2
Configure LIN support options and monitor receiver activity
FEIE
PEIE
SCIS3
9th data bits
TXDIR
R8
T8
ORIE
NEIE
SCIID
Read: Rx data; write: Tx data
R5/T5
R7/T7
R6/T6
Rx/Tx pin
direction in
Local interrupt enables
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
TXINV
Tx data path
polarity
single-wire
mode
Module Initialization:
Write:
SCIBDH:SCIBDL
to set
baud rate
Write:
SCFC1
to configure
1-wire/2-wire, 9/8-bit data, wakeup, and parity, if used.
Write;
SCIC2
to configure
interrupts, enable Rx and Tx, RWU
Enable Rx wakeup, SBK sends break character
Write:
SCIC3
to enable
Rx error interrupt sources. Also controls pin direction in
1-wire modes. R8 and T8 only used in 9-bit data modes.
Module Use:
Wait for TDRE, then write data to SCID
Wait for RDRF, then read data from SCID
A small number of applications will use RWU to manage automatic receiver wakeup, SBK to send break characters, and
R8 and T8 for 9-bit data.
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
194
Freescale Semiconductor
14.1.1
Features
Features of SCI module include:
Full-duplex, standard non-return-to-zero (NRZ) format
Double-buffered transmitter and receiver with separate enables
Programmable baud rates (13-bit modulo divider)
Interrupt-driven or polled operation:
-- Transmit data register empty and transmission complete
-- Receive data register full
-- Receive overrun, parity error, framing error, and noise error
-- Idle receiver detect
Hardware parity generation and checking
Programmable 8-bit or 9-bit character length
Receiver wakeup by idle-line or address-mark
Optional 13-bit break character
Selectable transmitter output polarity
14.1.2
Modes of Operation
See
Section 14.3, "Functional Description
," for a detailed description of SCI operation in the different
modes.
8- and 9- bit data modes
Stop modes -- SCI is halted during all stop modes
Loop mode
Single-wire mode
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
195
14.1.3
Block Diagram
Figure 14-3
shows the transmitter portion of the SCI. (
Figure 14-4
shows the receiver portion of the SCI.)
Figure 14-3. SCI Transmitter Block Diagram
H
8
7
6
5
4
3
2
1
0
L
SCID Tx BUFFER
(WRITE-ONLY)
INTERNAL BUS
STOP
11-BIT TRANSMIT SHIFT REGISTER
START
SHIFT DIRECTION
LSB
1
BAUD
RATE CLOCK
PARITY
GENERATION
TRANSMIT CONTROL
SHIFT ENABLE
PREAMBLE (ALL 1s)
BREAK (ALL 0s)
SCI CONTROLS TxD
TxD DIRECTION
TO TxD
PIN LOGIC
LOOP
CONTROL
TO RECEIVE
DATA IN
TO TxD PIN
Tx INTERRUPT
REQUEST
LOOPS
RSRC
TIE
TC
TDRE
M
PT
PE
TCIE
TE
SBK
T8
TXDIR
LO
AD FR
OM SCID
TXINV
BRK13
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
196
Freescale Semiconductor
Figure 14-4
shows the receiver portion of the SCI.
Figure 14-4. SCI Receiver Block Diagram
H
8
7
6
5
4
3
2
1
0
L
SCID Rx BUFFER
(READ-ONLY)
INTERNAL BUS
STOP 11-BIT RECEIVE SHIFT REGISTER
START
SHIFT DIRECTION
LSB
FROM RxD PIN
RATE CLOCK
Rx INTERRUPT
REQUEST
DATA RECOVERY
DIVIDE
16
BAUD
SINGLE-WIRE
LOOP CONTROL
WAKEUP
LOGIC
ALL 1s
MSB
FROM
TRANSMITTER
ERROR INTERRUPT
REQUEST
PARITY
CHECKING
BY 16
RDRF
RIE
IDLE
ILIE
OR
ORIE
FE
FEIE
NF
NEIE
PF
LOOPS
PEIE
PT
PE
RSRC
WAKE
ILT
RWU
M
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
197
14.2
Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
Memory
chapter of this data sheet for the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
14.2.1
SCI Baud Rate Registers (SCIBDH, SCIBHL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIBDH to buffer the high half of the new value and then write
to SCIBDL. The working value in SCIBDH does not change until SCIBDL is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
7
6
5
4
3
2
1
0
R
0
0
0
SBR12
SBR11
SBR10
SBR9
SBR8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-5. SCI Baud Rate Register (SCIBDH)
Table 14-1. SCIBDH Register Field Descriptions
Field
Description
4:0
SBR[12:8]
Baud Rate Modulo Divisor -- These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16
BR). See also BR bits in
Table 14-2
.
7
6
5
4
3
2
1
0
R
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
W
Reset
0
0
0
0
0
1
0
0
Figure 14-6. SCI Baud Rate Register (SCIBDL)
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
198
Freescale Semiconductor
14.2.2
SCI Control Register 1 (SCIC1)
This read/write register is used to control various optional features of the SCI system.
Table 14-2. SCIBDL Register Field Descriptions
Field
Description
7:0
SBR[7:0]
Baud Rate Modulo Divisor -- These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16
BR). See also BR bits in
Table 14-1
.
7
6
5
4
3
2
1
0
R
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
W
Reset
0
0
0
0
0
0
0
0
Figure 14-7. SCI Control Register 1 (SCIC1)
Table 14-3. SCIC1 Register Field Descriptions
Field
Description
7
LOOPS
Loop Mode Select -- Selects between loop back modes and normal 2-pin full-duplex modes. When
LOOPS = 1, the transmitter output is internally connected to the receiver input.
0 Normal operation -- RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
RSRC
bit.) RxD pin is not used by SCI.
6
SCISWAI
SCI Stops in Wait Mode
0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
5
RSRC
Receiver Source Select -- This bit has no meaning or effect unless the LOOPS bit is set to 1. When
LOOPS = 1, the receiver input is internally connected to the TxD pin and RSRC determines whether this
connection is also connected to the transmitter output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
4
M
9-Bit or 8-Bit Mode Select
0 Normal -- start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
start + 8 data bits (LSB first) + 9th data bit + stop.
3
WAKE
Receiver Wakeup Method Select -- Refer to
Section 14.3.3.2, "Receiver Wakeup Operation
" for more
information.
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select -- Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character
do not count toward the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to
Section 14.3.3.2.1, "Idle-Line Wakeup
" for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
199
14.2.3
SCI Control Register 2 (SCIC2)
This register can be read or written at any time.
1
PE
Parity Enable -- Enables hardware parity generation and checking. When parity is enabled, the most significant
bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
0
PT
Parity Type -- Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in
the data character, including the parity bit, is even.
0 Even parity.
1 Odd parity.
7
6
5
4
3
2
1
0
R
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
W
Reset
0
0
0
0
0
0
0
0
Figure 14-8. SCI Control Register 2 (SCIC2)
Table 14-4. SCIC2 Register Field Descriptions
Field
Description
7
TIE
Transmit Interrupt Enable (for TDRE)
0 Hardware interrupts from TDRE disabled (use polling).
1 Hardware interrupt requested when TDRE flag is 1.
6
TCIE
Transmission Complete Interrupt Enable (for TC)
0 Hardware interrupt requested when TC flag is 1.
1 Hardware interrupts from TC disabled (use polling).
5
RIE
Receiver Interrupt Enable (for RDRF)
0 Hardware interrupts from RDRF disabled (use polling).
1 Hardware interrupt requested when RDRF flag is 1.
4
ILIE
Idle Line Interrupt Enable (for IDLE)
0 Hardware interrupts from IDLE disabled (use polling).
1 Hardware interrupt requested when IDLE flag is 1.
3
TE
Transmitter Enable
0 Transmitter off.
1 Transmitter on.
TE must be 1 in order to use the SCI transmitter. Normally, when TE = 1, the SCI forces the TxD pin to act as an
output for the SCI system. If LOOPS = 1 and RSRC = 0, the TxD pin reverts to being a port B general-purpose
I/O pin even if TE = 1.
When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of
traffic on the single SCI communication line (TxD pin).
TE also can be used to queue an idle character by writing TE = 0 then TE = 1 while a transmission is in progress.
Refer to
Section 14.3.2.1, "Send Break and Queued Idle
," for more details.
When TE is written to 0, the transmitter keeps control of the port TxD pin until any data, queued idle, or queued
break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin.
Table 14-3. SCIC1 Register Field Descriptions (continued)
Field
Description
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
200
Freescale Semiconductor
14.2.4
SCI Status Register 1 (SCIS1)
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.
2
RE
Receiver Enable -- When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin.
0 Receiver off.
1 Receiver on.
1
RWU
Receiver Wakeup Control -- This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to
Section 14.3.3.2, "Receiver Wakeup Operation
," for more details.
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
0
SBK
Send Break -- Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the
set and clear of SBK relative to the information currently being transmitted, a second break character may be
queued before software clears SBK. Refer to
Section 14.3.2.1, "Send Break and Queued Idle
," for more details.
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
7
6
5
4
3
2
1
0
R
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
W
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-9. SCI Status Register 1 (SCIS1)
Table 14-5. SCIS1 Register Field Descriptions
Field
Description
7
TDRE
Transmit Data Register Empty Flag -- TDRE is set out of reset and when a transmit data value transfers from
the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read
SCIS1 with TDRE = 1 and then write to the SCI data register (SCID).
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
6
TC
Transmission Complete Flag -- TC is set out of reset and when TDRE = 1 and no data, preamble, or break
character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things:
Write to the SCI data register (SCID) to transmit new data
Queue a preamble by changing TE from 0 to 1
Queue a break character by writing 1 to SBK in SCIC2
Table 14-4. SCIC2 Register Field Descriptions (continued)
Field
Description
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
201
5
RDRF
Receive Data Register Full Flag -- RDRF becomes set when a character transfers from the receive shifter into
the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register
(SCID).
0 Receive data register empty.
1 Receive data register full.
4
IDLE
Idle Line Flag -- IDLE is set when the SCI receive line becomes idle for a full character time after a period of
activity. When ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is
all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times
depending on the M control bit) needed for the receiver to detect an idle line. When ILT = 1, the receiver doesn't
start counting idle bit times until after the stop bit. So the stop bit and any logic high bit times at the end of the
previous character do not count toward the full character time of logic high needed for the receiver to detect an
idle line.
To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been
cleared, it cannot become set again until after a new character has been received and RDRF has been set. IDLE
will get set only once even if the receive line remains idle for an extended period.
0 No idle line detected.
1 Idle line was detected.
3
OR
Receiver Overrun Flag -- OR is set when a new serial character is ready to be transferred to the receive data
register (buffer), but the previously received character has not been read from SCID yet. In this case, the new
character (and all associated error information) is lost because there is no room to move it into SCID. To clear
OR, read SCIS1 with OR = 1 and then read the SCI data register (SCID).
0 No overrun.
1 Receive overrun (new SCI data lost).
2
NF
Noise Flag -- The advanced sampling technique used in the receiver takes seven samples during the start bit
and three samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples
within any bit time in the frame, the flag NF will be set at the same time as the flag RDRF gets set for the
character. To clear NF, read SCIS1 and then read the SCI data register (SCID).
0 No noise detected.
1 Noise detected in the received character in SCID.
1
FE
Framing Error Flag -- FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop
bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read
SCIS1 with FE = 1 and then read the SCI data register (SCID).
0 No framing error detected. This does not guarantee the framing is correct.
1 Framing error.
0
PF
Parity Error Flag -- PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in
the received character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the
SCI data register (SCID).
0 No parity error.
1 Parity error.
Table 14-5. SCIS1 Register Field Descriptions (continued)
Field
Description
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
202
Freescale Semiconductor
14.2.5
SCI Status Register 2 (SCIS2)
This register has one read-only status flag. Writes have no effect.
14.2.6
SCI Control Register 3 (SCIC3)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
BRK13
0
RAF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-10. SCI Status Register 2 (SCIS2)
Table 14-6. SCIS2 Register Field Descriptions
Field
Description
2
BRK13
Break Character Length -- BRK13 is used to select a longer break character length. Detection of a framing
error is not affected by the state of this bit.
0 Break character is 10 bit times (11 if M = 1)
1 Break character is 13 bit times (14 if M = 1)
0
RAF
Receiver Active Flag -- RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is
cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an
SCI character is being received before instructing the MCU to go to stop mode.
0 SCI receiver idle waiting for a start bit.
1 SCI receiver active (RxD input not idle).
7
6
5
4
3
2
1
0
R
R8
T8
TXDIR
TXINV
ORIE
NEIE
FEIE
PEIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-11. SCI Control Register 3 (SCIC3)
Table 14-7. SCIC3 Register Field Descriptions
Field
Description
7
R8
Ninth Data Bit for Receiver -- When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a
ninth receive data bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data,
read R8 before reading SCID because reading SCID completes automatic flag clearing sequences which could
allow R8 and SCID to be overwritten with new data.
6
T8
Ninth Data Bit for Transmitter -- When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a
ninth transmit data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire
9-bit value is transferred to the SCI shift register after SCID is written so T8 should be written (if it needs to
change from its previous value) before SCID is written. If T8 does not need to change in the new value (such as
when it is used to generate mark or space parity), it need not be written each time SCID is written.
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
203
14.2.7
SCI Data Register (SCID)
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
5
TXDIR
TxD Pin Direction in Single-Wire Mode -- When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
0 TxD pin is an input in single-wire mode.
1 TxD pin is an output in single-wire mode.
4
TXINV
1
Transmit Data Inversion -- Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
1 Transmit data inverted
3
ORIE
Overrun Interrupt Enable -- This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
2
NEIE
Noise Error Interrupt Enable -- This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
1
FEIE
Framing Error Interrupt Enable -- This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
0
PEIE
Parity Error Interrupt Enable -- This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
1
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
Reset
0
0
0
0
0
0
0
0
Figure 14-12. SCI Data Register (SCID)
Table 14-7. SCIC3 Register Field Descriptions (continued)
Field
Description
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
204
Freescale Semiconductor
14.3
Functional Description
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.
14.3.1
Baud Rate Generation
As shown in
Figure 14-13
, the clock source for the SCI baud rate generator is the bus-rate clock.
Figure 14-13. SCI Baud Rate Generation
SCI communications require the transmitter and receiver (which typically derive baud rates from
independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends
on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is
performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are
no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is
accumulated for the whole character time. For a Freescale Semiconductor SCI system whose bus
frequency is driven by a crystal, the allowed baud rate mismatch is about
4.5 percent for 8-bit data format
and about
4 percent for 9-bit data format. Although baud rate modulo divider settings do not always
produce baud rates that exactly match standard rates, it is normally possible to get within a few percent,
which is acceptable for reliable communications.
14.3.2
Transmitter Functional Description
This section describes the overall block diagram for the SCI transmitter, as well as specialized functions
for sending break and idle characters. The transmitter block diagram is shown in
Figure 14-3
.
The transmitter output (TxD) idle state defaults to logic high (TXINV = 0 following reset). The transmitter
output is inverted by setting TXINV = 1. The transmitter is enabled by setting the TE bit in SCIC2. This
queues a preamble character that is one full character frame of the idle state. The transmitter then remains
idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the SCI data register (SCID).
The central element of the SCI transmitter is the transmit shift register that is either 10 or 11 bits long
depending on the setting in the M control bit. For the remainder of this section, we will assume M = 0,
SBR12:SBR0
DIVIDE BY
Tx BAUD RATE
Rx SAMPLING CLOCK
(16
BAUD RATE)
BAUD RATE GENERATOR
OFF IF [SBR12:SBR0] = 0
BUSCLK
BAUD RATE =
BUSCLK
[SBR12:SBR0]
16
16
MODULO DIVIDE BY
(1 THROUGH 8191)
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
205
selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits,
and a stop bit. When the transmit shift register is available for a new SCI character, the value waiting in
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status flag is set to indicate another character may be written to the
transmit data buffer at SCID.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the
transmitter sets the transmit complete flag and enters an idle mode, with TxD1 high, waiting for more
characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must first be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
14.3.2.1
Send Break and Queued Idle
The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.
Normally, a program would wait for TDRE to become set to indicate the last character of a message has
moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break
character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into
the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving
device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data
bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD1 pin. If
there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a
normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
Table 14-8. Break Character Length
BRK13
M
Break Character Length
0
0
10 bit times
0
1
11 bit times
1
0
13 bit times
1
1
14 bit times
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
206
Freescale Semiconductor
14.3.3
Receiver Functional Description
In this section, the receiver block diagram (
Figure 14-4
) is used as a guide for the overall receiver
functional description. Next, the data sampling technique used to reconstruct receiver data is described in
more detail. Finally, two variations of the receiver wakeup function are explained.
The receiver is enabled by setting the RE bit in SCIC2. Character frames consist of a start bit of logic 0,
eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer
to
Section 14.4.1, "8- and 9-Bit Data Modes
." For the remainder of this discussion, we assume the SCI is
configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status
flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun
(OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program
has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid
a receiver overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCID. The RDRF flag is cleared automatically by a 2-step sequence which is
normally satisfied in the course of the user's program that handles receive data. Refer to
Section 14.3.4,
"Interrupts and Status Flags
," for more details about flag clearing.
14.3.3.1
Data Sampling Technique
The SCI receiver uses a 16
baud rate clock for sampling. The receiver starts by taking logic level samples
at 16 times the baud rate to search for a falling edge on the RxD1 serial data input pin. A falling edge is
defined as a logic 0 sample after three consecutive logic 1 samples. The 16
baud rate clock is used to
divide the bit time into 16 segments labeled RT1 through RT16. When a falling edge is located, three more
samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not merely noise. If at
least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to
determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples
taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples
at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any
sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic
level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive
data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample
clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise
or mismatched baud rates. It does not improve worst case analysis because some characters do not have
any extra falling edges anywhere in the character frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic
that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected
almost immediately.
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
207
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing
error flag is cleared. The receive shift register continues to function, but a complete character cannot
transfer to the receive data buffer if FE is still set.
14.3.3.2
Receiver Wakeup Operation
Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a
message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first
character(s) of each message, and as soon as they determine the message is intended for a different
receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2. When RWU = 1, it inhibits
setting of the status flags associated with the receiver, thus eliminating the software overhead for handling
the unimportant message characters. At the end of a message, or at the beginning of the next message, all
receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of
the next message.
14.3.3.2.1
Idle-Line Wakeup
When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When the RWU bit is set, the idle character that wakes a receiver does not set the receiver idle bit, IDLE,
or the receive data register full flag, RDRF. It therefore will not generate an interrupt when this idle
character occurs. The receiver will wake up and wait for the next data transmission which will set RDRF
and generate an interrupt if enabled.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle
bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
14.3.3.2.2
Address-Mark Wakeup
When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved
for use in address frames. The logic 1 MSB of an address frame clears the receivers RWU bit before the
stop bit is received and sets the RDRF flag.
14.3.4
Interrupts and Status Flags
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is
used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
208
Freescale Semiconductor
masked by local interrupt enable masks. The flags can still be polled by software when the local masks are
cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCID. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be
requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished
transmitting all data, preamble, and break characters and is idle with TxD1 high. This flag is often used in
systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt
enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware
interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE
or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then
reading SCID.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains
idle for an extended period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading
SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one
new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags --
noise flag (NF), framing error (FE), and parity error flag (PF) -- get set at the same time as RDRF. These
flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag gets set instead and the data and any associated NF, FE, or PF
condition is lost.
14.4
Additional SCI Functions
The following sections describe additional SCI functions.
14.4.1
8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCIC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCIC3. For the receiver, the ninth bit is held
in R8 in SCIC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID.
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
209
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the
ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.
14.4.2
Stop Mode Operation
During all stop modes, clocks to the SCI module are halted.
In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these
two stop modes.
No SCI module registers are affected in stop3 mode.
Note, because the clocks are halted, the SCI module will resume operation upon exit from stop (only in
stop3 mode). Software should ensure stop mode is not entered while there is a character being transmitted
out of or received into the SCI module.
14.4.3
Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a
general-purpose port I/O pin.
14.4.4
Single-Wire Operation
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Single-wire mode is used to implement a half-duplex serial connection.
The receiver is internally connected to the transmitter output and to the TxD1 pin. The RxD1 pin is not
used and reverts to a general-purpose port I/O pin.
In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD1 pin. When
TXDIR = 0, the TxD1 pin is an input to the SCI receiver and the transmitter is temporarily disconnected
from the TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1
pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the
transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
Serial Communications Interface (S08SCIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
210
Freescale Semiconductor
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
211
Chapter 15
Serial Peripheral Interface (S08SPIV3)
15.1
Introduction
Figure 15-1
shows the MC9S08QG8/4 block diagram with the SPI highlighted.
Chapter 15 Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
212
Freescale Semiconductor
Figure 15-1. MC9S08QG8/4 Block Diagram Highlighting SPI Block and Pins
V
SS
V
DD
V
SSA
V
DDA
V
REFL
V
REFH
IIC MODULE (IIC)
SERIAL PERIPHERAL
INTERFACE MODULE (SPI)
USER FLASH
USER RAM
(MC9S08QG8 = 8192 BYTES)
HCS08 CORE
CPU
BDC
NOTES:
1
Not all pins or pin functions are available on all devices, see
Table 1-1
for available functions on each device.
2
Port pins are software configurable with pullup device if input port.
3
Port pins are software configurable for output drive strength.
4
Port pins are software configurable for output slew rate control.
5
IRQ contains a software configurable (IRQPDD) pullup device if PTA5 enabled as IRQ pin function (IRQPE = 1).
6
RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
7
PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8
SDA and SCL pin locations can be repositioned under software control (IICPS), defaults on PTA2 and PTA3.
9
When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure
the pullup as a pulldown device.
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/SCL/EXTAL
POR
T B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI
COP
IRQ
LVD
INTERFACE MODULE (SCI)
SERIAL COMMUNICATIONS
8-BIT MODULO TIMER
MODULE (MTIM)
(MC9S08QG4 = 4096 BYTES)
PTB6/SDA/XTAL
PTB5/TPMCH1/SS
PTB4/MISO
PTB3/KBIP7/MOSI/ADP7
PTB2/KBIP6/SPSCK/ADP6
VOLTAGE REGULATOR
POR
T A
PTA5//IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/ADP1/ACMP
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
8-BIT KEYBOARD
INTERRUPT MODULE (KBI)
(MC9S08QG8 = 512 BYTES)
(MC9S08QG4 = 256 BYTES)
DEBUG MODULE (DBG)
ANALOG COMPARATOR
(ACMP)
MISO
SCL
SDA
MOSI
SPSCK
RxD
TxD
LOW-POWER OSCILLATOR
16-MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
EXTAL
XTAL
4
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
4
SS
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
TPMCH0
TPMCH1
ACMPO
ACMP
TCLK
BKGD/MS
IRQ
ACMP+
4
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
213
15.1.1
Features
Features of the SPI module include:
Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate
Double-buffered transmit and receive
Serial clock phase and polarity options
Slave select output
Selectable MSB-first or LSB-first shifting
15.1.2
Block Diagrams
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
15.1.2.1
SPI System Block Diagram
Figure 15-2
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
Figure 15-2. SPI System Connections
7
6
5
4
3
2
1
0
SPI SHIFTER
CLOCK
GENERATOR
7
6
5
4
3
2
1
0
SPI SHIFTER
SS
SPSCK
MISO
MOSI
SS
SPSCK
MISO
MOSI
MASTER
SLAVE
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
214
Freescale Semiconductor
The most common uses of the SPI system include connecting simple shift registers for adding input or
output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although
Figure 15-2
shows a system where data is exchanged between two MCUs, many practical systems involve
simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a
slave to the master MCU.
15.1.2.2
SPI Module Block Diagram
Figure 15-3
is a block diagram of the SPI module. The central element of the SPI is the SPI shift register.
Data is written to the double-buffered transmitter (write to SPID) and gets transferred to the SPI shift
register at the start of a data transfer. After shifting in a byte of data, the data is transferred into the
double-buffered receiver where it can be read (read from SPID). Pin multiplexing logic controls
connections between MCU pins and the SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
215
Figure 15-3. SPI Module Block Diagram
15.1.3
SPI Baud Rate Generation
As shown in
Figure 15-4
, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
SPI SHIFT REGISTER
SHIFT
CLOCK
SHIFT
DIRECTION
Rx BUFFER
FULL
Tx BUFFER
EMPTY
SHIFT
OUT
SHIFT
IN
ENABLE
SPI SYSTEM
CLOCK
LOGIC
CLOCK GENERATOR
BUS RATE
CLOCK
MASTER/SLAVE
MODE SELECT
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
SPI
INTERRUPT
REQUEST
PIN CONTROL
M
S
MASTER/
SLAVE
MOSI
(MOMI)
MISO
(SISO)
SPSCK
SS
M
S
S
M
MODF
SPE
LSBFE
MSTR
SPRF
SPTEF
SPTIE
SPIE
MODFEN
SSOE
SPC0
BIDIROE
SPIBR
Tx BUFFER (WRITE SPID)
Rx BUFFER (READ SPID)
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
216
Freescale Semiconductor
Figure 15-4. SPI Baud Rate Generation
15.2
External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPE = 0), these four pins revert to being general-purpose port I/O pins that
are not controlled by the SPI.
15.2.1
SPSCK -- SPI Serial Clock
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
15.2.2
MOSI -- Master Data Out, Slave Data In
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data output. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
input. If SPC0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes
the bidirectional data I/O pin (MOMI). Also, the bidirectional mode output enable bit determines whether
the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and slave mode is
selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
15.2.3
MISO -- Master Data In, Slave Data Out
When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this
pin is the serial data input. When the SPI is enabled as a slave and SPC0 = 0, this pin is the serial data
output. If SPC0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes
the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit determines whether the
pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 = 1 and master mode is selected,
this pin is not used by the SPI and reverts to being a general-purpose port I/O pin.
15.2.4
SS -- Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (MODFEN = 0), this pin is not used by the SPI and reverts to being
a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select
output enable bit determines whether this pin acts as the mode fault input (SSOE = 0) or as the slave select
output (SSOE = 1).
DIVIDE BY
2, 4, 8, 16, 32, 64, 128, or 256
DIVIDE BY
1, 2, 3, 4, 5, 6, 7, or 8
PRESCALER
CLOCK RATE DIVIDER
SPPR2:SPPR1:SPPR0
SPR2:SPR1:SPR0
BUS CLOCK
MASTER
SPI
BIT RATE
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
Freescale Semiconductor
217
15.3
Register Definition
The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the
Memory
chapter of this data sheet for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
15.3.1
SPI Control Register 1 (SPIC1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
7
6
5
4
3
2
1
0
R
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
W
Reset
0
0
0
0
0
1
0
0
Figure 15-5. SPI Control Register 1 (SPIC1)
Table 15-1. SPIC1 Field Descriptions
Field
Description
7
SPIE
SPI Interrupt Enable (for SPRF and MODF) -- This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
6
SPE
SPI System Enable -- Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes
internal state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled
5
SPTIE
SPI Transmit Interrupt Enable -- This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
4
MSTR
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
CPOL
Clock Polarity -- This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to
Section 15.4.1, "SPI Clock Formats
"
for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
2
CPHA
Clock Phase -- This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to
Section 15.4.1, "SPI Clock Formats
"
for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
Serial Peripheral Interface (S08SPIV3)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 1.01
218
Freescale Semiconductor
15.3.2
SPI Control Register 2 (SPIC2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
1
SSOE
Slave Select Output Enable -- This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in
Table 15-2
.
0
LSBFE
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
Table 15-2. SS Pin Function
MODFEN
SSOE
Master Mode
Slave Mode
0
0
General-purpose I/O (not SPI)
Slave select input
0
1
General-purpose I/O (not SPI)
Slave select input
1
0
SS input for mode fault
Slave select input
1
1
Automatic SS output
Slave select input
7
6
5
4
3
2
1
0
R
0
0
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. SPI Control Register 2 (SPIC2)
Table 15-3. SPIC2 Register Field Descriptions
Field
Description
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