Embedded EraseTM, Embedded ProgramTM and ExpressFlashTM are trademarks of Advanced Micro Devices, Inc.
DS05-20868-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
2M (256K
8) BIT
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
FEATURES
Single 5.0 V read, write, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
32-pin PLCC (Package Suffix: PD)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
Any combination of sectors can be erased. Also supports full chip erase
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM Algorithms
Automatically programs and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Low V
CC
write inhibit
3.2 V
Hardware RESET pin
Resets internal state machine to the read mode
Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
Sector protection
Hardware method that disables any combination of sector from write or erase operation
Temporary sector unprotection
Temporary sector unprotection via the RESET pin
2
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
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PACKAGE
32-pin plastic QFJ (PLCC)
(LCC-32P-M02)
Marking Side
32-pin plastic TSOP(I)
(FPT-32P-M24)
32-pin plastic TSOP(I)
(FPT-32P-M25)
Marking Side
Marking Side
3
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/MBM29F002BC
-55/-70/-90
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GENERAL DESCRIPTION
The MBM29F002TC/BC is a 2 M-bit, 5.0 V-Only Flash memory organized as 256K bytes of 8 bits each. The
MBM29F002TC/BC is offered in a 32-pin TSOP(I) and 32-pin PLCC packages. This device is designed to be
programmed in-system with the standard system 5.0 V V
CC
supply. A 12.0 V V
PP
is not required for program or
erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F002TC/BC offers access times between 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F002TC/BC is command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 12.0 V Flash or EPROM devices.
The MBM29F002TC/BC is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase
is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margin.
This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to
be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1
second (if already completely preprogrammed). The MBM29F002TC/BC is erased when shipped from the
factory.
The MBM29F002TC/BC device also features hardware sector protection. This feature will disable both program
and erase operations in any number of secotrs (0 through 6)
.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.
The device features single 5.0 V power supply operation for both read and program functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of
DQ
7
, or by the Toggle Bit I feature on DQ
6
. Once the end of a program or erase cycle has been completed, the
device automatically resets to the read mode.
The MBM29F002TC/BC also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into
the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs
during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read
mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu's Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F002TC/BC memory electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the
EPROM programming mechanism of hot electron injection.
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MBM29F002TC
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/MBM29F002BC
-55/-70/-90
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
Individual-sector, multiple-sector, or bulk-erase capability
Individual or multiple-sector protection is user definable
00000H
MBM29F002TC Sector Architecture
MBM29F002BC Sector Architecture
03FFFH
00000H
16K byte
8K byte
8K byte
32K byte
64K byte
64K byte
64K byte
64K byte
64K byte
64K byte
32K byte
8K byte
8K byte
16K byte
3FFFFH
3BFFFH
39FFFH
37FFFH
2FFFFH
1FFFFH
0FFFFH
3FFFFH
2FFFFH
1FFFFH
0FFFFH
07FFFH
05FFFH
5
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
PRODUCT LINE UP
s
BLOCK DIAGRAM
Part No.
MBM29F002TC/BC
Ordering Part No.
V
CC
= 5.0 V 5%
-55
--
--
V
CC
= 5.0 V 10%
--
-70
-90
Max. Address Access Time (ns)
55
70
90
Max. CE Access Time (ns)
55
70
90
Max. OE Access Time (ns)
30
30
35
V
SS
V
CC
WE
CE
A
0
to A
17
OE
Erase Voltage
Generator
DQ
0
to DQ
7
State
Control
Command
Register
Program Voltage
Generator
Low V
CC
Detector
Address
Latch
X-Decoder
Y-Decoder
Cell Matrix
Y-Gating
Chip Enable
Output Enable
Logic
Data Latch
Input/Output
Buffers
STB
STB
Timer for
RESET
Program/Erase
6
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/MBM29F002BC
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s
CONNECTION DIAGRAMS
A
11
A
9
A
8
A
13
A
14
A
17
WE
V
CC
RESET
A
16
A
15
A
12
A
7
A
6
A
5
A
4
OE
A
10
CE
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
V
SS
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
12
A
15
A
16
RESET
V
CC
WE
A
17
A
14
A
13
A
8
A
9
A
11
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
CE
A
10
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Standard Pinout
Reverse Pinout
TSOP (I)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
7
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
4
3
2
1
32
31
30
14
15
16
17
18
19
20
DQ
1
DQ
2
V
SS
DQ
3
DQ
4
DQ
5
DQ
6
PLCC
A
12
A
15
A
16
RES
E
T
V
CC
WE
A
17
LCC-32P-M02
FPT-32P-M24
FPT-32P-M25
Marking Side
Marking Side
7
MBM29F002TC
-55/-70/-90
/MBM29F002BC
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s
LOGIC SYMBOL
Legend: L = V
IL
, H = V
IH
, X = V
IL
or V
IH
,
= Pulse Input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to
Table 6.
2. Refer to the section on Sector Protection.
3. WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
Table 1 MBM29F002TC/BC Pin Configuration
Pin
Function
A
0
to A
17
Address Inputs
DQ
0
to DQ
7
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Hardware Reset Pin/Sector Protection
Unlock
N.C.
No Internal Connection
V
SS
Device Ground
V
CC
Device Power Supply
Table 2 MBM29F002TC/BC User Bus Operations
Operation
CE
OE
WE
A
0
A
1
A
6
A
9
A
10
DQ
0
to DQ
7
RESET
Auto-Select Manufacturer Code (1)
L
L
H
L
L
L
V
ID
L
Code
H
Auto-Select Device Code (1)
L
L
H
H
L
L
V
ID
L
Code
H
Read (3)
L
L
H
A
0
A
1
A
6
A
9
A
10
D
OUT
H
Standby
H
X
X
X
X
X
X
X
HIGH-Z
H
Output Disable
L
H
H
X
X
X
X
X
HIGH-Z
H
Write (Program/Erase)
L
H
L
A
0
A
1
A
6
A
9
A
10
D
IN
H
Enable Sector Protection (2)
L
V
ID
X
X
X
V
ID
X
X
H
Verify Sector Protection (2)
L
L
H
L
H
L
V
ID
L
Code
H
Temporary Sector Unprotection
X
X
X
X
X
X
X
X
X
V
ID
Reset (Hardware)
X
X
X
X
X
X
X
X
HIGH-Z
L
18
A
0
to A
17
WE
OE
CE
DQ
0
to DQ
7
8
RESET
8
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29F002 T
C
-70
PFTN
DEVICE NUMBER/DESCRIPTION
MBM29F002
2 Mega-bit (256K
8-Bit) CMOS Flash Memory
5.0 V-only Read, Write, and Erase
PACKAGE TYPE
PFTN = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 32-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
PD
= 32-Pin Rectangular Plastic Leaded
Chip Carrier (PLCC)
SPEED OPTION
See Product Selector Guide
C = Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
9
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/MBM29F002BC
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FUNCTIONAL DESCRIPTION
Read Mode
The MBM29F002TC/BC has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the
addresses have been stable for at least t
ACC
-t
OE
time).
Standby Mode
There are two ways to implement the standby mode on the MBM29F002TC/BC devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
0.3 V.
Under this condition the current consumed is less than 5
A. A TTL standby mode is achieved with CE and
RESET pins held at V
IH
. Under this condition the current is reduced to approximately 1 mA. During Embedded
Algorithm operation, V
CC
Active current (I
CC2
) is required even CE = V
IH
. The device can be read with standard
access time (t
CE
) from either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
0.3 V (CE
= "H" or "L"). Under this condition the current consumed is less than 5
A. A TTL standby mode is achieved with
RESET pin held at V
IL
(CE = "H" or "L"). Under this condition the current required is reduced to approximately
1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before outputs are valid
for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (V
IH
), output from the device is disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the device outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are don't cares except A
0
, A
1
, A
6
and A
10
. (See Table 3.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29F002TC/BC is erased or programmed in a system without access to high voltage on the A
9
pin. The
command sequence is illustrated in Table 6. (Refer to Autoselect Command section.)
Byte 0 (A
0
= V
IL
) represents the manufacturer's code (Fujitsu = 04H) and byte 1 (A
0
= V
IH
) represents the device
identifier code for MBM29F002TC = B0H, MBM29F002BC = 34H. These two bytes are given in the table 3. All
identifiers for manufactures and device will exhibit odd parity with DQ
7
defined as the parity bit. In order to read
the proper device codes when executing the Autoselect, A
1
must be V
IL
. (See Table 3.)
The Autoselect mode also facilitates the determination of sector protection in the system. By performing a read
operation at the address location XX02H with the higher order address bits A
13
, A
14
, A
15
, A
16
and A
17
set to the
desired sector address, the device will return 01H for a protected sector and 00H for a non-protected sector.
10
MBM29F002TC
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/MBM29F002BC
-55/-70/-90
* : Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Table 3 .1 MBM29F002TC/BC Sector Protection Verify Autoselect Codes
Type
A
13
to A
17
A
10
A
6
A
1
A
0
Code (HEX)
Manufacture's Code
X
V
IL
V
IL
V
IL
V
IL
04H
Device Code
MBM29F002TC
X
V
IL
V
IL
V
IL
V
IH
B0H
MBM29F002BC
X
V
IL
V
IL
V
IL
V
IH
34H
Sector Protection
Sector
Addresses
V
IL
V
IL
V
IH
V
IL
01H*
Table 3 .2 Expanded Autoselect Code Table
Type
Code
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
Manufacture's Code
04H
0
0
0
0
0
1
0
0
Device Code
MBM29F002TC
B0H
1
0
1
1
0
0
0
0
MBM29F002BC
34H
0
0
1
1
0
1
0
0
Sector Protection
01H
0
0
0
0
0
0
0
1
Table 4 Sector Address Tables (MBM29F002TC)
A
17
A
16
A
15
A
14
A
13
Address Range
SA0
0
0
X
X
X
00000H to 0FFFFH
SA1
0
1
X
X
X
10000H to 1FFFFH
SA2
1
0
X
X
X
20000H to 2FFFFH
SA3
1
1
0
X
X
30000H to 37FFFH
SA4
1
1
1
0
0
38000H to 39FFFH
SA5
1
1
1
0
1
3A000H to 3BFFFH
SA6
1
1
1
1
X
3C000H to 3FFFFH
Table 5 Sector Address Tables (MBM29F002BC)
A
17
A
16
A
15
A
14
A
13
Address Range
SA0
0
0
0
0
X
00000H to 03FFFH
SA1
0
0
0
1
0
04000H to 05FFFH
SA2
0
0
0
1
1
06000H to 07FFFH
SA3
0
0
1
X
X
08000H to 0FFFFH
SA4
0
1
X
X
X
10000H to 1FFFFH
SA5
1
0
X
X
X
20000H to 2FFFFH
SA6
1
1
X
X
X
30000H to 3FFFFH
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/MBM29F002BC
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Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F002TC/BC features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 6)
.
The sector protection feature is enabled using programming
equipment at the user's site. The device is shipped with all sectors unprotected.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
and control pin OE, (suggest
V
ID
= 11.5 V), CE = V
IL
. The sector addresses (A
13
, A
14
, A
15
, A
16
, and A
17
) should be set to the sector to be
protected. Tables 4 and 5 define the sector address for each of the seven (7) individual sectors. Programming
of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of
the same. Sector addresses must be held constant during the WE pulse. See figures 14 and 21 for sector
protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector addresses (A
13
, A
14
, A
15
, A
16
, and A
17
) while (A
10
, A
6
,
A
1
, A
0
) = (0, 0, 1, 0) will produce a logical "1" code at device output DQ
0
for a protected sector. Otherwise the
device will produce 00H for unprotected sector. In this mode, the lower order addresses, except for A
0
, A
1
, A
6
,
and A
10
are DON'T CARES. Address locations with A
1
= V
IL
are reserved for Autoselect manufacturer and device
codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A
13
, A
14
, A
15
, A
16
, and A
17
)
are the desired sector address will produce a logical "1" at DQ
0
for a protected sector. See Table 3 for Autoselect
codes.
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MBM29F002TC
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/MBM29F002BC
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Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29F002TC/BC device in
order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12
V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.
Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.
Refer to Figures 14 and 21.
Notes: 1. Address bits A
11
to A
17
= X = "H" or "L" for all address commands except or Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A
17
, A
16
, A
15
, A
14
, and A
13
will uniquely select
any sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
ID = Device Code (Refer to the section on Sector Protection Verify Autoselect Codes.)
*: Either of the two reset commands will reset the device.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to the
read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both
Read/Reset commands are functionally equivalent, resetting the device to the read mode.
Table 6 MBM29F002TC/BC Command Definitions
Command
Sequence
Bus
Write
Cycles
Req'd
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset*
1
XXXH F0H
--
--
--
--
--
--
--
--
--
--
Reset/Read*
3
555H AAH
2AAH
55H
555H
F0H
RA
RD
--
--
--
--
Manufacture Code
3
555H AAH
2AAH
55H
555H
90H
00H
04H
--
--
--
--
Device Code
3
555H AAH
2AAH
55H
555H
90H
01H
ID
--
--
--
--
Byte Program
4
555H AAH
2AAH
55H
555H
A0H
PA
PD
--
--
--
--
Chip Erase
6
555H AAH
2AAH
55H
555H
80H
555H
AAH 2AAH
55H
555H
10H
Sector Erase
6
555H AAH
2AAH
55H
555H
80H
555H
AAH 2AAH
55H
SA
30H
Sector Erase Suspend
Erase can be suspended during sector erase with Addr ("H" or "L"), Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Addr ("H" or "L"), Data (30H)
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Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
9
to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desirable system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H returns the device code D5H. (See Table 3).
All manufacturer and device codes will exhibit odd parity with the DQ
7
defined as the parity bit.
Sector state (protection or unprotection) will be informed by address XX02H.
Scanning the sector addresses (A
17
, A
16
, A
15
, A
14
, and A
13
) while (A
10
, A
6
, A
1
, A
0
) = (0, 0, 1, 0) will produce a
logical "1" at device output DQ
0
for a protected sector.
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is
not
required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
This automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 7, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from reset/read mode will show that the data is still "0". Only
erase operations can convert "0"s to "1"s.
Figure 16 illustrates the Embedded Programming
TM
Algorithm using typical command strings and bus operations.
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Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase does
not
require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is "1" (see Write Operation Status section) at which time the device returns to read the
mode.
Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data = 30H) is latched on the rising edge of WE. After time-out of 50
s from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50
s otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50
s
from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling
edge of the WE occurs within the 50
s time-out window the timer is reset. (Monitor DQ
3
to determine if the
sector erase timer window is still open, see section DQ
3
, Sector Erase Timer.) Any command other than Sector
Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once execution has begun will corrupt the data in that sector. In that case,
restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for
DQ
3
, Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with
any number of sectors (0 to 6).
Sector erase does
not
require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system is
not
required to provide any controls or timings
during these operations.
The automatic sector erase begins after the 50
s time out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on DQ
7
is "1" (see Write Operation Status section)
at which time the device returns to the read mode. Data polling must be performed at an address within any of
the sectors being erased.
Figure 17 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
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Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during a Sector Erase operation
which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written
during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase
operation.
Any other command written during the Erase Suspend mode will be ignored except the Erase Resume command.
Writing the Erase Resume command resumes the erase operation. The addresses are DON'T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 15
s to suspend the erase operation. When the device has entered the erase-suspended mode, the DQ
7
bit
will be at logic "1", and DQ
6
will stop toggling. The user must use the address of the erasing sector for reading
DQ
6
and DQ
7
to determine if the erase operation has been suspended. Further writes of the Erase Suspend
command are ignored.
When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ
2
to toggle. (See the section on DQ
2
.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.
Again, programming in this mode is the same as programming in the regular Byte Program mode except that
the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-
suspended sector while the device is in the erase-suspend-program mode will cause DQ
2
to toggle. The end of
the erase-suspended program operation is detected by Data polling of DQ
7
, or by the Toggle Bit I (DQ
6
) which
is the same as the regular Byte Program operation. Note that DQ
7
must be read from the Byte Program address
while DQ
6
can be read from any address.
To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
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Write Operation Status
Notes: 1. Performing successive read operations from the erase-suspended sector will cause DQ
2
to toggle.
2. Performing successive read operations from any address will cause DQ
6
to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
"1" at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to toggle.
DQ
7
Data Polling
The MBM29F002TC/BC device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device
will produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded
EraseTM Algorithm, an attempt to read the device will produce a "0" at the DQ
7
output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ
7
output. The flowchart
for Data Polling (DQ
7
) is shown in Figure 18.
Data polling will also flag the entry into Erase Suspend. DQ
7
will switch "0" to "1" at the start of the Erase Suspend
mode. Please note that the address of an erasing sector must be applied in order to observe DQ
7
in the Erase
Suspend Mode.
During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling
must be performed at sector address within any of the sectors being erased and not a sector that is within a
protected sector. Otherwise, the status may not be valid.
Table 7 Hardware Sequence Flags
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
(Note 1)
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
(Note 2)
0
0
1
(Note 3)
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
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Just prior to the completion of Embedded Algorithm operation DQ
7
may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ
7
at one instant of
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ
7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ
6
Toggle Bit I
The MBM29F002TC/BC also features the "Toggle Bit I" as a method to indicate to the host system that the
embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device
at any address
will result in DQ
6
toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ
6
will stop toggling and valid data will be read on
the next
successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth
WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of
the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.
In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2
s and then
stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for
the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about
100
s and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ
6
to toggle. In addition, an Erase Suspend/Resume command will
cause DQ
6
to toggle.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ
5
Exceeded Timing Limits
DQ
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ
5
will produce a "1". This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ
7
, DQ
6
is the only operating function of the device under
this condition. The CE circuit will partially power down the device under these conditions (to approximately 2
mA). The OE and WE pins will control the output disable functions as described in Table 2.
The DQ
5
failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the
system never reads a valid data on DQ
7
bit and DQ
6
never stops toggling. Once the device has exceeded timing
limits, the DQ
5
bit will indicate a "1." Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
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DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
3
may
be used to determine if the sector erase timer window is still open. If DQ
3
is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
3
is low ("0"),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
Refer to Table 7: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This toggle bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded EraseTM
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded EraseTM Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic "1" at the DQ
2
bit.
Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended.
2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ
7
, is summarized
as follows:
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode (DQ
2
toggles while
DQ
6
does not). See also Table 7 and Figure 15.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from the erasing sector.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
toggles
1
Erase
0
toggles
toggles
Erase Suspend Read (1)
(Erase-Suspended Sector)
1
1
toggles
Erase Suspend Program
DQ
7
(2)
toggles
1 (2)
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RESET
Hardware Reset
The MBM29F002TC/BC device may be reset by driving the RESET pin to V
IL
. The RESET pin must be kept low
(V
IL
) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset
to the read mode 20
s after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires t
RH
of wake up time until outputs are valid for read access.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system's
microprocessor to read the boot-up firmware from the Flash memory.
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Data Protection
The MBM29F002TC/BC is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 3.2 V (typically 3.7 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 3.2 V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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s
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ........................................................................................55C to +125C
Ambient Temperature with Power Applied ........................................................40C to +85C
Voltage with Respect to Ground All pins except A
9
, OE, and RESET (Note 1).2.0 V to +7.0 V
V
CC
(Note 1) ......................................................................................................2.0 V to +7.0 V
A
9
, OE, and RESET (Note 2) ............................................................................2.0 V to +13.5 V
Notes: 1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, inputs may negative
overshoot V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is V
CC
+0.5 V. During voltage transitions, outputs may positive overshoot to V
CC
+2.0 V for periods up to 20 ns.
2. Minimum DC input voltage on A
9
, OE, and RESET pins are 0.5 V. During voltage transitions, A
9
, OE,
and RESET pins may negative overshoot V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A
9
, OE, and RESET are +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. Voltage
difference between input voltage and power supply. (V
IN
V
CC
) do not exceed 9 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s
RECOMMENDED OPERATING RANGES
Ambient Temperature (T
A
) ................................................................................ 40C to +85C
V
CC
Supply Voltages
MBM29F002TC/BC-55 ................................................................................. +4.75 V to +5.25 V
MBM29F002TC/BC-70/-90 ........................................................................... +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
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s
MAXIMUM OVERSHOOT
Figure 1 Maximum Negative Overshoot Waveform
+0.8 V
0.5 V
20 ns
2.0 V
20 ns
20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
+2.0 V
V
CC
+0.5 V
20 ns
V
CC
+2.0 V
20 ns
20 ns
V
CC
+0.5 V
+13.0 V
20 ns
+14.0 V
20 ns
20 ns
Figure 3 Maximum Positive Overshoot Waveform 2
Note: This waveform is applied for A
9
, OE, and RESET.
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s
DC CHARACTERISTICS
Notes: 1. The I
CC
current listed includes both the DC operating current and the frequency dependent component
(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. Applicable to sector protection function.
4. (V
ID
V
CC
) do not exceed 9 V.
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
Max.
--
1.0
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
,
V
CC
= V
CC
Max.
--
1.0
A
I
LIT
A
9
, OE, RESET Inputs Leakage
Current
V
CC
= V
CC
Max.
A
9
, OE, RESET = 12.5 V
--
50
A
I
CC1
V
CC
Active Current (Note 1)
CE = V
IL
, OE = V
IH
--
35
mA
I
CC2
V
CC
Active Current (Note 2)
CE = V
IL
, OE = V
IH
--
50
mA
I
CC3
V
CC
Current (Standby)
V
CC
= V
CC
Max., CE = V
IH
RESET = V
IH
--
1
mA
V
CC
= V
CC
Max., CE = V
CC
0.3 V,
RESET = V
CC
0.3 V
--
5
A
I
CC4
V
CC
Current (Standby, Reset)
V
CC
= V
CC
Max.
RESET = V
IL
--
1
mA
V
CC
= V
CC
Max.
RESET = V
SS
0.3 V
--
5
A
V
IL
Input Low Level
--
0.5
0.8
V
V
IH
Input High Level
--
2.0
V
CC
+0.5
V
V
ID
Voltage for Autoselect and Sector
Protection (A
9
, OE, RESET)
(Note 3, 4)
--
11.5
12.5
V
V
OL
Output Low Voltage Level
I
OL
= 12.0 mA, V
CC
= V
CC
Min.
--
0.45
V
V
OH1
Output High Voltage Level
I
OH
= 2.5 mA, V
CC
= V
CC
Min.
2.4
--
V
V
OH2
I
OH
= 100
A
V
CC
0.4
--
V
V
LKO
Low V
CC
Lock-Out Voltage
--
3.2
4.2
V
24
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
AC CHARACTERISTICS
Read Only Operations Characteristics
Note: 1.Test Conditions:
Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
Parameter
Symbols
Description
Test Setup
-55
(Note1)
-70
(Note2)
-90
(Note2) Unit
JEDEC Standard
t
AVAV
t
RC
Read Cycle Time
--
Min.
55
70
90
ns
t
AVQV
t
ACC
Address to Output Delay
CE = V
IL
OE = V
IL
Max.
55
70
90
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE = V
IL
Max.
55
70
90
ns
t
GLQV
t
OE
Output Enable to Output Delay
--
Max.
30
30
35
ns
t
EHQZ
t
DF
Chip Enable to Output HIGH-Z
--
Max.
20
20
20
ns
t
GHQZ
t
DF
Output Enable to Output HIGH-Z
--
Max.
20
20
20
ns
t
AXQX
t
OH
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
--
Min.
0
0
0
ns
--
t
READY
RESET Pin Low to Read Mode
--
Max.
20
20
20
s
Figure 4 Test Conditions
Note: 1. C
L
= 30 pF including jig capacitance
2. C
L
= 100 pF including jig capacitance
C
L
5.0 V
Diodes = IN3064
or Equivalent
2.7 k
Device
Under
Test
IN3064
or Equivalent
6.2 k
Note: 2. Test Conditions:
Output Load: 1 TTL gate and 100 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level
Input: 0.8 V and 2.0 V
Output: 0.8 V and 2.0 V
25
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Write/Erase/Program Operations
(Continued)
Parameter Symbols
Description
MBM29F002TC/BC
Unit
JEDEC
Standard
-55
-70
-90
t
AVAV
t
WC
Write Cycle Time
Min.
55
70
90
ns
t
AVWL
t
AS
Address Setup Time
Min.
0
0
0
ns
t
WLAX
t
AH
Address Hold Time
Min.
40
45
45
ns
t
DVWH
t
DS
Data Setup Time
Min.
25
30
45
ns
t
WHDX
t
DH
Data Hold Time
Min.
0
0
0
ns
--
t
OES
Output Enable Setup Time
Min.
0
0
0
ns
--
t
OEH
Output Enable
Hold Time
Read
Min.
0
0
0
ns
Toggle Bit I and Data Polling
Min.
10
10
10
ns
t
GHWL
t
GHWL
Read Recover Time Before Write
Min.
0
0
0
ns
t
GHEL
t
GHEL
Read Recover Time Before Write
Min.
0
0
0
ns
t
ELWL
t
CS
CE Setup Time
Min.
0
0
0
ns
t
WLEL
t
WS
WE Setup Time
Min.
0
0
0
ns
t
WHEH
t
CH
CE Hold Time
Min.
0
0
0
ns
t
EHWH
t
WH
WE Hold Time
Min.
0
0
0
ns
t
WLWH
t
WP
Write Pulse Width
Min.
30
35
45
ns
t
ELEH
t
CP
Write Pulse Width
Min.
30
35
45
ns
t
WHWL
t
WPH
Write Pulse Width High
Min.
20
20
20
ns
t
EHEL
t
CPH
Write Pulse Width High
Min.
20
20
20
ns
t
WHWH1
t
WHWH1
Byte Programming Operation
Typ.
8
8
8
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 1)
Typ.
1
1
1
sec
Max.
8
8
8
sec
--
t
VCS
V
CC
Setup Time
Min.
50
50
50
s
--
t
VIDR
Rise Time to V
ID
Min.
500
500
500
ns
--
t
VLHT
Voltage Transition Time (Note 2)
Min.
4
4
4
s
--
t
WPP
Write Pulse Width (Note 2)
Min.
100
100
100
s
--
t
OESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
4
s
--
t
CSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
4
s
26
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
(Continued)
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
Parameter Symbols
Description
MBM29F002TC/BC
Unit
JEDEC
Standard
-55
-70
-90
--
t
RP
RESET Pulse Width
Min.
500
500
500
ns
--
t
RH
RESET Hold Time Before Read
Min.
50
50
50
ns
--
t
EOE
Delay Time from Embedded Output Enable
Max.
30
30
35
ns
27
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
SWITCHING WAVEFORMS
Key to Switching Waveforms
Figure 5.1 AC Waveforms for Read Operations
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
"H" or "L"
Any Change
Permitted
Does Not
Apply
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center Line is
High-
Impedance
"Off" State
WE
OE
CE
t
ACC
t
DF
t
CE
t
OE
DQ
0
to DQ
7
t
RC
Addresses
Addresses Stable
High-Z
Output Valid
High-Z
t
OEH
28
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
RESET
t
ACC
t
OH
DQ
0
to DQ
7
t
RC
Addresses
Addresses Stable
High-Z
Output Valid
t
RH
Figure 5.2 AC Waveforms for Read Operations
29
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 6 AC Waveforms for Alternate WE Controlled Program Operations
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ
7
is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
t
WP
t
DS
t
WHWH1
t
WC
t
AH
CE
OE
t
RC
Addresses
Data
t
AS
t
OE
t
WPH
t
CS
t
DH
DQ
7
PD
A0H
D
OUT
t
CE
WE
555H
PA
PA
t
OH
Data Polling
3rd Bus Cycle
t
GHWL
t
CH
D
OUT
30
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 7 AC Waveforms for Alternate CE Controlled Program Operations
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ
7
is the output of the complement of the data written to the device.
4. D
OUT
is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
t
CP
t
DS
t
WHWH1
t
WC
t
AH
WE
OE
Addresses
Data
t
AS
t
CPH
t
WS
t
DH
DQ
7
PD
A0H
D
OUT
CE
555H
PA
PA
Data Polling
3rd Bus Cycle
t
GHEL
t
WH
31
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 8 AC Waveforms Chip/Sector Erase Operations
*
: SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.
V
CC
CE
OE
Addresses
Data
t
WP
WE
555H
2AAH
555H
555H
2AAH
SA*
t
DS
t
CH
t
AS
t
AH
t
CS
t
WPH
t
DH
t
VCS
t
WC
55H
55H
80H
AAH
AAH
10H/
30H
t
GHWL
32
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 9 AC Waveforms for Data Polling During Embedded Algorithm Operations
* : DQ
7
= Valid Data (The device has completed the Embedded operation.)
t
OEH
t
OE
t
WHWH1 or 2
CE
OE
WE
t
DF
t
CH
t
CE
High-Z
DQ
7
=
Valid Data
DQ
0
to DQ
6
= Output Flug
DQ
0
to DQ
7
DQ
7
*
Valid Data
High-Z
t
EOE
DQ
7
Data
Data
DQ
0
to DQ
6
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
* : DQ
6
stops toggling (The device has completed the Embedded operation.)
t
OEH
CE
WE
OE
DQ
6
= Toggle
*
t
OES
t
OE
DQ
6
=
Stop Toggling
DQ
0
to DQ
7
Valid
DQ
6
= Toggle
DQ
6
Data
33
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 11 RESET Timing Diagram
RESET
t
READY
t
RP
34
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 12 AC Waveforms for Sector Protection Timing Diagram
SGAx = Sector Address for initial sector
SGAy = Sector Address for next sector
t
VLHT
SAx
SAy
A
0
A
6
A
9
V
ID
5 V
t
VLHT
OE
V
ID
5 V
t
VLHT
t
VLHT
WE
CE
t
OE
01H
Data
V
CC
A
1
A
17
, A
16
, A
15
,
A
14
, A
13
t
WPP
t
OESP
t
CSP
t
VCS
35
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 13 Temporary Sector Unprotection Timing Diagram
5 V
RESET
V
CC
CE
WE
t
VLHT
Program or Erase Command Sequence
5 V
t
VLHT
t
VCS
t
VIDR
V
ID
t
VLHT
Unprotection period
DQ
2
DQ
6
WE
Erase
Erase
Suspend
Enter
Embedded
Erasing
Erase Suspend
Read
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase
Erase
Complete
Toggle
DQ
2
and DQ
6
with OE
Figure 14 DQ
2
vs. DQ
6
Note: DQ
2
is read from the erase-suspended sector.
36
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 15 Embedded Program
TM
Algorithm
No
Yes
Start
Program Command Sequence (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Write Program Command
Sequence
(See Below)
Data Polling Device
Increment Address
Last Address
?
Programming Completed
Program Address/Program Data
EMBEDDED ALGORITHMS
37
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 16 Embedded EraseTM Algorithm
Note: To insure the command has been accepted, the system software should check the status
of DQ
3
prior to and following each subsequent sector erase command. If DQ
3
were high on
the second status check, the command may not have been accepted.
Start
555H/AAH
2AAH/55H
555H/AAH
555H/80H
555H/10H
2AAH/55H
555H/AAH
2AAH/55H
555H/AAH
555H/80H
2AAH/55H
Additional sector
erase commands
are optional.
Write Erase Command
Sequence
(See Below)
Data Polling or Toggle Bit I
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
Sector Address/30H
Sector Address/30H
Sector Address/30H
38
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 17 Data Polling Algorithm
Note: DQ
7
is rechecked even if DQ
5
= "1" because DQ
7
may change simultaneously with DQ
5
.
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
erases operation.
= Any of the sector
addresses within the sector not
being protected during sector
erase or multiple sector erases
operation.
Fail
DQ
7
= Data?
No
No
DQ
7
= Data?
DQ
5
= 1?
Pass
Yes
Yes
No
Start
Read Byte
(DQ
0
to DQ
7
)
Addr. = VA
Read Byte
(DQ
0
to DQ
7
)
Addr. = VA
Yes
39
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 18 Toggle Bit I Algorithm
Note: DQ
6
is rechecked even if DQ
5
= "1" because DQ
6
may stop toggling at the same time as DQ
5
changing to "1".
Fail
DQ
6
= Toggle
?
Yes
No
DQ
6
= Toggle
DQ
5
= 1
Pass
Yes
No
Yes
Start
Read Byte
?
(DQ
0
to DQ
7
)
Addr. = "H" or "L"
No
Read Byte
(DQ
0
to DQ
7
)
Addr. = "H" or "L"
?
40
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 19 Sector Protection Algorithm
Setup Sector Addr.
Activate WE Pulse
WE = V
IH,
CE = OE = V
IL,
(A
9
should remain V
ID
)
Yes
Yes
No
No
PLSCNT = 1
Time out 100
s
Read from Sector
Increment PLSCNT
No
Yes
Protect Another Sector?
Start
Sector Protection
Data = 01H?
PLSCNT = 25?
Device Failed
Remove V
ID
from A
9
Completed
Remove
V
ID
from A
9
Write Reset Command
Addr. (A
19
, A
18
, A
17
)
A
1
= 1, A
0
= A
6
= 0
OE = V
ID
, A
9
= V
ID
,
CE = V
IL
, RESET = V
IH
(
A
17
, A
16
, A
15
, A
14
, A
13
)
Write Reset Command
41
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Figure 20 Temporary Sector Unprotection Algorithm
Notes: 1. All Protected sectors unprotected.
2. All previously protected sectors are protected once again.
RESET = V
ID
(Note 1)
Perform Erase or
Program Operations
RESET = V
IH
Start
Temporary Sector
Unprotection Completed
(Note 2)
42
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
ERASE AND PROGRAMMING PERFORMANCE
s
TSOP(I) PIN CAPACITANCE
Note: Test conditions T
A
= 25C, f = 1.0 MHz
s
PLCC PIN CAPACITANCE
Notes: 1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz
Parameter
Limits
Unit
Comments
Min.
Typ.
Max.
Sector Erase Time
--
1
8
sec
Excludes 00H programming
prior to erasure
Byte Programming Time
--
8
150
s
Excludes system-level
overhead
Chip Programming Time
--
2.1
5
sec
Excludes system-level
overhead
Erase/Program Cycle
100,000
--
--
cycles
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0
7
8
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
10
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
8
10
pF
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0
7
8
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
10
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
8
10
pF
43
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
s
PACKAGE DIMENSIONS
C
1994 FUJITSU LIMITED F32035S-2C-1
1
32
16
17
INDEX
"A"
LEAD No.
20.000.20
(.787.008)
18.400.20
(.724.008)
19.000.20
(.748.008)
0.10(.004)
0.500.10
(.020.004)
0.150.05
(.006.002)
0.200.10
(.008.004)
7.50(.295)
REF.
M
0.10(.004)
0.50(.0197)
TYP
8.000.20
(.315.008)
0.05(.002)MIN
(STAND OFF)
.043
.002
+.004
0.05
+0.10
1.10
Details of "A" part
MAX
0.35(.014)
MAX
0.15(.006)
0.15(.006)
0.25(.010)
(Mounting height)
Dimensions in mm(inches)
32-pin plastic TSOP(I)
(FPT-32P-M24)
44
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
C
1997 FUJITSU LIMITED F32036S-2C-2
1
32
16
17
"A"
LEAD No.
19.000.20
(.748.008)
0.10(.004)
20.000.20
(.787.008)
18.400.20
(.724.008)
0.150.05
(.006.002)
0.500.10
(.020.004)
8.000.20
(.315.008)
7.50(.295)
REF.
0.200.10
(.008.004)
0.50(.0197)
TYP
M
0.10(.004)
0.05(.002)MIN
(STAND OFF)
.043
.002
+.004
0.05
+0.10
1.10
0.25(.010)
0.15(.006)
0.15(.006)
MAX
0.35(.014)
MAX
Details of "A" part
INDEX
(Mounting height)
Dimensions in mm(inches)
32-pin plastic TSOP(I)
(FPT-32P-M25)
45
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
C
1994 FUJITSU LIMITED C32021S-2C-4
1
4
32
30
5
13
21
29
20
14
11.430.08
(.450.003)
12.370.13
(.487.005)
13.970.08
(.550.003)
14.940.13
(.588.005)
0.64(.025)
MIN
2.250.38
(.089.015)
3.400.16
(.134.006)
12.950.51
(.510.020)
R0.95(.037)
TYP
1.270.13
(.050.005)
7.62(.300)REF
10.16(.400)
REF
0.43(.017)
TYP
0.66(.026)
TYP
10.410.51
(.410.020)
.008
.001
+.002
0.02
+0.05
0.20
0.10(.004)
INDEX
No
: LEAD No.
Dimensions in mm(inches)
32-pin plastic QFJ(PLCC)
(LCC-32P-M02)
46
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9903
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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