Fujitsu's CS66, a 0.35m (0.28m L
eff
) standard cell
product is based on the state-of-the-art Fujitsu CMOS
process technologya process designed for high integration
and cost effective solutions. The cell-based design enables
the realization of "system-on-silicon"applications that
include the following:
User-defined logic
Sophisticated analog functions
High-density memory
Intelligent peripherals
Cores
The CS66 technology is based on an enhanced 3.3V
process that provides fast performance along with 3.3V
power savings. The CS66 standard cell library is the most
aggressive and optimal library for implementing today's
high-performance deep submicron systems-on-silicon. The
CS66 supports dense, high-clock frequency system-level
designs that meet the performance, integration, and power
management requirements of networking, telecommunica-
tion, electronic data processing and digital video applications.
The library also supports the most popular third-party
tools and data exchange file standards.
The core operates at 2V, 2.5V and 3.3V, with I/Os operating
at 3.3V, 5V and 5V tolerant, or any combination of these.
The core also supports voltages as low as 1.1V for sensitive,
ultra low-power applications. Interface options include
low-swing, and bus interface I/Os.
CS66 Series Standard Cell
0.28m L
eff
Features
w
Description
w
In addition to the traditional QFP packages, the CS66 family
is available in Ball Grid Array and Flip Chip packages. The
CS66 also offers a rich set of ADCs and DACs, analog PLLs
and high-speed RAMs, ROMs and DRAMs, along with a
variety of other embedded functions.
Design Methodology
Fujitsu's design methodology ensures first-silicon success by
integrating proprietary point tools with the most popular,
sign-off quality, industry-standard CAD tools. The following
are among these tools:
Logic design rule checker
Delay calculator
Quasi three-dimensional parasitic extraction tool
Fujitsu's clock-driven design methodology offers low power
and low skew. It identifies the best-suited clock distribution
strategy for a given design and predicts performance in
advance. Fujitsu supports co-simulation, emulation, and
high-level floorplanning to ease the power, timing and size
estimation of the design. This enables the designer to make
effective architectural-level decisions toward achieving opti-
mal design solutions.
Fujitsu's design methodology supports cycle-based simulators
and formal verification, as well as static timing analysis
and the more conventional VHDL and Verilog simulators.
Fujitsu's design-for-test strategy includes boundary scan
(JTAG), full and partial scan, as well as a built-in self-test
for memory.
CS66
Dual Power Supply
(5.0V/3.3V)
High-Speed
Devices
T-LVTTL
P-CML
LVDS
SDRAM I/F
SSTL
GTL
ADC/DAC
3.3V
CMOS
AGP
USB
PCI
AGP Bus
USB Devices
PCI Bus
5.0V
Tolerant
High-Speed
Interface
Analog
Interface
3.3V CMOS
3.3V Device
5.0V TTL
5.0V Device
CS66 I/O Interface Capabilities
0.28m L
eff
(0.35m drawn)
Propagation delay of 98 ps
Mixed-signal macros: A/D and D/A converters
High-density diffused RAMs and ROMs
Separate core and I/O supply voltages
I/Os: 5V, 3.3V and 5V tolerant
100m staggered pad pitch for core-limited designs
Special I/Os: PCI, LVTTL, I
2
C, USB
Analog and digital PLLs
Packaging options: QFP, HQFP, LQFP, TQFP, PBGA, FBGA
Support for major third party EDA tools
0.3W/gate/MHz power dissipation @ 3.3V
High-performance SRAM and DRAM
1998 Fujitsu Microelectronics, Inc.
All company and product names are trademarks or
registered trademarks of their respective owners.
Printed in the U.S.A. ASIC-FS-20639-7/98
CS66 Series
(0.28m L
eff
)
Standard Cell
Applications
The CS66 series offers high integration and very low power
consumption, in addition to cost-effective, high-performance,
area-optimized memories. High-performance transmission
and switching applications and power-sensitive applications,
such as mobile computing and mobile communications, can
benefit from this technology.
Memory Macros
SRAM Compiler: single and dual port (1 R/W, 1R),
up to 72K bits per block
ROM Compiler: up to 512K bits per block
Phase Locked Loops
Analog: 50 to 200 MHz
Digital: 180 to 360 MHz (Preliminary)
I/Os
5V, 3.3V and 5V tolerant
Slew-rate controlled
CMOS, TTL, PCI, I2C, USB
IPs and Mega Macros
To achieve the highest level of integration for our customers,
Fujitsu offers a rich set of IPs that are either developed
internally or acquired through strategic relationships with
IP providers.
Interface Functions
PCI core
10/100 Ethernet MAC (under development)
P1394 (under development)
USB
High-Performance Functions
MPEG2 (Q1'99)
16/64/256 QAM(Q1'99)
QPSK (Q1'99)
ASIC Design Kit and EDA Support
Verifire VCS,
Verilog-XL,
(VCS, Cadence Tools,
Sign-off Simulation, Veritime,
Synopsys Synthesis)
Verifault, Design Compiler (Synopsys)
Vhdlfire
All vital compliance tools,
Sign-off Simulation, Design Time,
Design Compiler
Other EDA Tools
Motive, Sunrise, HLD, DesignPower
PACKAGE AVAILABILITY
No. of Pins
Frame Size
TQFP
100
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
LQFP
100
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
144
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
176
P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
208
P6, P7, P8, P9, PA, PB, PC, PD
QFP
120
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
144
P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
160
P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
176
P3, P4, P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
208
P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
240
P8, P9, PA, PB, PC, PD, PE, PF
256
P9, PA, PB, PC, PD, PE, PF
HQFP
208
P5, P6, P7, P8, P9, PA, PB, PC, PD, PE, PF
240
P8, P9, PA, PB, PC, PD, PE, PF
256
P9, PA, PB, PC, PD, PE, PF
304
PC, PD, PE, PF
PBGA
256
P9, PA, PB, PC, PD, PE, PF
352
PF
FBGA
112
Planned
144
Planned
168
Planned
176
Planned
192
Planned
224
Planned
288
---
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters
3545 North First Street, San Jose, California 95134-1804
Tel: (800) 866-8608 Fax: (408) 922-9179
E-mail: fmicrc@fmi.fujitsu.com Internet: http://www.fujitsumicro.com
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