GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: June 2004
Document No. 52248 - 5
DATA SHEET
GS15
11
KEY FEATURES
SMPTE 292M compliant
NRZ(I) encoding
SMPTE 292M scrambler with BYPASS option
selectable TRS insertion
selectable line number insertion
selectable line based CRC insertion
selectable active picture illegal code re-mapping
20 bit 3.3V CMOS compatible input data bus
optimized output interface to GS1522
Pb-free and Green
single +3.3V power supply
5V tolerant I/O
APPLICATIONS
SMPTE 292M Serial Digital Interfaces
DESCRIPTION
The GS1511 HDTV Serial Digital Formatter formats the
HDTV Luma and Chroma data according to SMPTE 292M
prior to serialization by the GS1522 HDTV Serializer. The
GS1511 optionally inserts TRS and line number signals
based on externally supplied H, V and F signals. The
device also allows the insertion of CRCs based on TRS
signals embedded in the input data streams, should the
user choose not to supply external HVF signals.
Following the insertion of TRS, Line Number, and CRC,
protected words of 000-003 and 3FC to 3FF occurring
during the active video period are optionally re-mapped to
004 and 3FB respectively. Prior to exiting the device SMPTE
292M compliant NRZ(I) encoding and scrambling may be
performed on the data stream.
GS1511 FUNCTIONAL BLOCK DIAGRAM
INPUT
BUFFER
and
BLANKER
TRS
and
LINE NUMBER
DETECTION
PCLK_IN
DATA_OUT
[19:0]
[H:V:F]
BP_SC
ILLEGAL CODE
REMAPPING
CODE
PROTECT
TRS_INS
LN_INS
CRC_INS
NRZI
ENCODER
SMPTE
SCAMBLER
OEN
3
TRS
INSERTION
LINE NUMBER
INSERTION
CRC INSERTION
DATA_IN
[19:10]
(LUMA)
DATA_IN
[9:0]
(CHROMA)
BLANK
TRS_Y/C
DET_TRS
2
3
SRST
RSTLN
HD-LINX
TM
GS1511
HDTV Serial Digital Formatter
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TABLE OF CONTENTS
1. PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PIN ASSIGNMENT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PIN DESCRIPTIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
2. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 ABSOLUTE MAXIMUM RATINGS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 DC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 AC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. DETAILED DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. PACKAGE & ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 PACKAGE DIMENSIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 ORDERING INFORMATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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1. PIN OUT
1.1 PIN ASSIGNMENT
V
DD
GND
OEN
TN
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
GND
F
V
H
V
DD
GND
V
DD
GND
CRC_INS
LN_INS
GND
TRS_INS
TRS Y/C
SRST
BP_SC
RSTLN
CODE_PROTECT
GND
BLANK
DET_TRS
GND
V
DD
GND
PCLK_IN
NC
NC
NC
V
DD
GND
TEST
NC
NC
NC
NC
NC
V
DD
V
DD
V
DD
GND
V
DD
V
DD
GND
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
GND
V
DD
V
DD
GND
GND
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
DA
T
A_OUT[19]
DA
T
A_OUT[18]
DA
T
A_OUT[17]
DA
T
A_OUT[16]
DA
T
A_OUT[15]
V
DD
GND
DA
T
A_OUT[14]
DA
T
A_OUT[13]
DA
T
A_OUT[12]
DA
T
A_OUT[11]
DA
T
A_OUT[10]
DA
T
A_OUT[9]
V
DD
GND
DA
T
A_OUT[8]
DA
T
A_OUT[7]
V
DD
GND
DA
T
A_OUT[6]
DA
T
A_OUT[5]
DA
T
A_OUT[4]
DA
T
A_OUT[3]
DA
T
A_OUT[2]
DA
T
A_OUT[1]
DA
T
A_OUT[0]
DA
T
A_IN[19]
DA
T
A_IN[18]
DA
T
A_IN[17]
DA
T
A_IN[16]
DA
T
A_IN[15]
DA
T
A_IN[14]
V
DD
GND
DA
T
A_IN[13]
DA
T
A_IN[12]
DA
T
A_IN[11]
DA
T
A_IN[10]
V
DD
GND
DA
T
A_IN[9]
DA
T
A_IN[8]
DA
T
A_IN[7]
DA
T
A_IN[6]
DA
T
A_IN[5]
DA
T
A_IN[4]
DA
T
A_IN[3]
DA
T
A_IN[2]
DA
T
A_IN[1]
DA
T
A_IN[0]
V
DD
GND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GS1511
TOP
VIEW
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1.2 PIN DESCRIPTIONS
PIN NUMBER
NAME
TIMING
TYPE
DESCRIPTION
1
PCLK_IN
Synchronous
Input
Parallel Data Clock input.
74.25MHz or 74.25/1.001MHz.
2, 4, 14, 19, 24,
37, 46, 50, 58,
69, 79, 82, 91,
94, 110, 116,
128
GND
N/A
Ground
Ground.
Ground power supply connections.
3, 20, 25, 38, 47,
51, 59, 68, 78,
81, 90, 93, 99,
102, 109, 115,
127
V
DD
N/A
Power
Power.
Positive power supply connections.
5
DET_TRS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable the detection of
the TRS signals embedded in the video stream. When DET
_TRS is high, the device detects the TRS signals embedded in
the input video stream and uses the detected HVF signals
instead of the external HVF signals. When DET _TRS is low,
TRS detection is disabled. The device uses the external
supplied HVF signals.
6
BLANK
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
When BLANK is low, the device sets the
accompanying LUMA and CHROMA data to their appropriate
blanking levels. When BLANK is high, the LUMA and CHROMA
data streams pass through this stage of the device unaltered.
See timing diagram Figure 3.
7, 17, 95
GND
N/A
Ground.
This pin must be connected to GND for normal
operation.
8
CODE_PROTECT
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable re-mapping of
out-of-range words contained in the active portion of the video
signal. When this signal is high, the device re-maps out-of-
range words contained within the active portion of the video
signal into CCIR-601 compliant words. Values between 000-003
are re-mapped to 004. Values between 3FC and 3FF are re-
mapped to 3FB. When this signal is low, out-of-range words in
the active video region pass through the device unaltered.
9
RSTLN
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
Line number reset signal which must be
asserted once per frame at the beginning of the frame (for
example, on the falling edge of the F signal). A high to low
transition will reset the line number counter of the device to one
(1). See Figure 2 for timing.
10
BP_SC
Non-
synchronous
Input
Control Signal Input.
Used to enable or bypass the SMPTE292M
scrambler and NRZ(I) encoder. When BP_SC is low, the video
stream is scrambled according to SMPTE 292M and NRZ(I)
encoded. When BP_SC is high, the scrambler and NRZ(I)
encoder are by-passed.
11
SRST
Non-
synchronous
Input
Control Signal Input.
Used to reset the SMPTE292M scrambler
and NRZI encoder. When SRST is low, the scrambler and
encoder operate normally. A low to high transition on SRST
causes the scrambler and encoder to reset.
12
TRS_Y/C
Non-
synchronous
Input
Control Signal Input.
Only used when DET_TRS is high. When
TRS_Y/C is high, the device detects and uses TRS signals
embedded in the LUMA (DATA_IN[19:10]) channel. When
TRS_Y/C is low, the device detects and uses TRS signals
embedded in the CHROMA (DATA_IN[9:0]) channel.
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13
TRS_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable insertion of TRS
into the video streams. When TRS_INS is high, the device
inserts SMPTE 292M compliant TRS signals into the input LUMA
and CHROMA data streams based on the supplied HVF
signals. When TRS_INS is low, the device does not insert TRS
signals.
15
LN_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable insertion of line
numbers into the video stream. When LN_INS is high, the
device inserts SMPTE 292M compliant line number information
into the LUMA and CHROMA channels. When LN_INS is low,
the device does not insert the line number information into the
LUMA and CHROMA channels. Line number insertion is only
available when user supplied external FVH data is used
(DET_TRS set LOW).
16
CRC_INS
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable insertion of
CRCs into the video stream. When CRC_INS is high, the device
calculates and inserts line based CRCs. When CRC_INS is low,
this feature is disabled.
18, 99, 102, 76,
77, 80, 83-89,
92, 96-98, 100,
101
V
DD
N/A
This pin must be connected to V
DD
for normal operation.
21
H
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
This signal indicates the Horizontal
blanking period of the input video data stream. The device
inserts HDTV TRS based on the supplied HVF signals. Refer to
Figure 4 for required timing of H relative to LUMA
(DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]).
22
V
Synchronous
wrt PCLK_IN
Input
Control Signal Input.
This signal indicates the Vertical blanking
period of the input video data streams. Refer to Figure 4 for
required timing of V relative to LUMA (DATA_IN[19:10]) and
CHROMA (DATA_IN[9:0]).
1.2 PIN DESCRIPTIONS
(Continued)
PIN NUMBER
NAME
TIMING
TYPE
DESCRIPTION
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