www.gennum.com
GS1559 HD-LINXTM II
Multi-Rate Deserializer with
Loop-Through Cable Driver
GS1559 Data Sheet
30572 - 4
July 2005
1 of 74
Key Features
SMPTE 292M and SMPTE 259M-C compliant
descrambling and NRZI
NRZ decoding (with
bypass)
DVB-ASI sync word detection and 8b/10b decoding
auto-configuration for HD-SDI, SD-SDI and
DVB-ASI
serial loop-through cable driver output selectable as
reclocked or non-reclocked
dual serial digital input buffers with 2 x 1 mux
integrated serial digital signal termination
integrated reclocker
automatic or manual rate selection / indication
(HD/SD)
descrambler bypass option
user selectable additional processing features
including:
CRC, TRS, ANC data checksum, line number
and EDH CRC error detection and correction
programmable ANC data detection
illegal code remapping
internal flywheel for noise immune H, V, F
extraction
FIFO load Pulse
20-bit / 10-bit CMOS parallel output data bus
148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital output
automatic standards detection and indication
1.8V core power supply and 3.3V charge pump
power supply
3.3V digital I/O supply
JTAG test interface
Available in a Pb-free package
small footprint (11mm x 11mm)
Applications
SMPTE 292M Serial Digital Interfaces
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
Description
The GS1559 is a reclocking deserializer with a serial
loop-through cable driver. When used in conjunction
with the GS1574 Automatic Cable Equalizer and the
GO1525 Voltage Controlled Oscillator, a receive
solution can be realized for HD-SDI, SD-SDI and
DVB-ASI applications.
In addition to reclocking and deserializing the input data
stream, the GS1559 performs NRZI-to-NRZ decoding,
descrambling as per SMPTE 292M/259M-C, and word
alignment when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will word align
the data to K28.5 sync characters and 8b/10b decode
the received stream.
Two serial digital input buffers are provided with a 2x1
multiplexer to allow the device to select from one of two
serial digital input signals.
The integrated reclocker features a very wide Input
Jitter Tolerance of 0.3 UI (total 0.6 UI), a rapid
asynchronous lock time, and full compliance with
DVB-ASI data streams.
An integrated cable driver is provided for serial input
loop-through applications and can be selected to output
either buffered or reclocked data. This cable driver also
features an output mute on loss of signal, high
impedance mode, adjustable signal swing, and
automatic dual slew-rate selection depending on
HD/SD operational requirements.
The GS1559 also includes a range of data processing
functions such as error detection and correction,
automatic standards detection, and EDH support. The
device can also detect and extract SMPTE 352M
payload identifier packets and independently identify
the received video standard. This information is read
from internal registers via the host interface port.
Line-based CRC errors, line number errors, TRS errors,
EDH CRC errors and ancillary data checksum errors
can all be detected. A single `DATA_ERROR' pin is
provided which is a logical 'OR'ing of all detectable
errors. Individual error status is stored in internal
`ERROR_STATUS' registers.
Finally, the device can correct detected errors and
insert new TRS ID words, line-based CRC words,
ancillary data checksum words, EDH CRC words, and
line numbers. Illegal code re-mapping is also available.
All processing functions may be individually enabled or
disabled via host interface control.
GS1559 Data Sheet
30572 - 4
July 2005
3 of 74
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics........................................................................................16
2.1 Absolute Maximum Ratings ..........................................................................16
2.2 DC Electrical Characteristics ........................................................................16
2.3 AC Electrical Characteristics.........................................................................18
2.4 Solder Reflow Profiles...................................................................................20
3. Input/Output Circuits ..............................................................................................21
3.1 Host Interface Map........................................................................................23
3.1.1 Host Interface Map (R/W Configurable Registers) .............................24
3.1.2 Host Interface Map (Read Only Registers).........................................25
4. Detailed Description ...............................................................................................26
4.1 Functional Overview .....................................................................................26
4.2 Serial Digital Input.........................................................................................26
4.2.1 Input Signal Selection .........................................................................27
4.2.2 Carrier Detect Input ............................................................................27
4.2.3 Single Input Configuration ..................................................................27
4.3 Serial Digital Reclocker.................................................................................27
4.3.1 External VCO......................................................................................28
4.3.2 Loop Bandwidth ..................................................................................28
4.4 Serial Digital Loop-Through Output ..............................................................28
4.4.1 Output Swing ......................................................................................29
4.4.2 Reclocker Bypass Control ..................................................................29
4.4.3 Serial Digital Output Mute...................................................................30
4.5 Serial-To-Parallel Conversion .......................................................................30
4.6 Modes Of Operation......................................................................................31
4.6.1 Lock Detect.........................................................................................31
4.6.2 Master Mode.......................................................................................32
4.6.3 Slave Mode.........................................................................................32
4.7 SMPTE Functionality ....................................................................................34
4.7.1 SMPTE Descrambling and Word Alignment.......................................34
4.7.2 Internal Flywheel.................................................................................34
4.7.3 Switch Line Lock Handling..................................................................35
4.7.4 HVF Timing Signal Generation ...........................................................39
4.8 DVB-ASI Functionality ..................................................................................41
4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment................................41
GS1559 Data Sheet
30572 - 4
July 2005
4 of 74
4.8.2 Status Signal Outputs .........................................................................41
4.9 Data Through Mode ......................................................................................42
4.10 Additional Processing Functions.................................................................42
4.10.1 FIFO Load Pulse...............................................................................42
4.10.2 Ancillary Data Detection and Indication ............................................43
4.10.3 SMPTE 352M Payload Identifier.......................................................46
4.10.4 Automatic Video Standard and Data Format Detection....................47
4.10.5 Error Detection and Indication ..........................................................51
4.10.6 Error Correction and Insertion ..........................................................57
4.10.7 EDH Flag Detection ..........................................................................59
4.11 Parallel Data Outputs..................................................................................61
4.11.1 Parallel Data Bus Buffers..................................................................61
4.11.2 Parallel Output in SMPTE Mode.......................................................62
4.11.3 Parallel Output in DVB-ASI Mode.....................................................62
4.11.4 Parallel Output in Data-Through Mode .............................................62
4.11.5 Parallel Output Clock (PCLK) ...........................................................63
4.12 GSPI Host Interface ....................................................................................64
4.12.1 Command Word Description.............................................................64
4.12.2 Data Read and Write Timing ............................................................65
4.12.3 Configuration and Status Registers ..................................................66
4.13 JTAG...........................................................................................................67
4.14 Device Power Up ........................................................................................68
4.15 Device Reset...............................................................................................68
5. Application Reference Design................................................................................69
5.1 Typical Application Circuit (Part A) ...............................................................69
5.2 Typical Application Circuit (Part B) ...............................................................70
6. References & Relevant Standards.........................................................................71
7. Package & Ordering Information............................................................................72
7.1 Package Dimensions ....................................................................................72
7.2 Packaging Data.............................................................................................73
7.3 Ordering Information .....................................................................................73
8. Revision History .....................................................................................................74
PDF 
ZIP
