Document No. 520 - 23 - 03

DATA SHEET

GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-2055

Japan Branch: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3247-8838 fax (03) 3247-8839

FEATURES

GS1881, GS4881, GS4981

Monolithic Video Sync Separators

DESCRIPTION

The GS1881, GS4881 and GS4981 are general purpose sync
separators for use in a wide variety of video applications. The
devices extract the timing information from composite video
signals with scan rates from 15 to 130 kHz.

The GS1881 is a drop-in replacement for the industry standard
LM1881 with much improved performance. The device
generates composite sync, vertical sync, back porch and
odd/even field signals. The GS4881 is identical to the GS1881
but features a noise immune back porch pulse which maintains
a constant H rate during the vertical interval. The GS4981 is
identical to the GS4881, except that it provides horizontal sync
in place of the odd/even output.

All three devices feature a self-adjusting windowing circuit for
noise immunity, which synchronizes to H rate. This
windowing c i r c u i t d e t e r m i n e s t h e o d d o r e v e n f i e l d
in the GS1881 and GS4881, gates the back porch pulse in
the GS4881 and GS4981, and generates the horizontal sync
output in the GS4981.

The devices feature an improved input stage which ensures
that the input signal is sliced at a predictable point due to
well-controlled input clamp discharge current and sync
slicing level. A missing pulse detector enables the devices to
recover quickly from impulse noise disturbances by temporarily
increasing the clamp discharge current by roughly ten times.
The input stage will operate with signals from 0.5 to 4 volts
peak to peak with a 5 volt supply.

The GS1881, GS4881 and GS4981 also feature a predictable
vertical output pulse width with a default trigger for non-standard
video signals. All three are available in commercial and
industrial temperature ranges and are packaged in both DIP
and SOIC.

· noise tolerant odd/even flag, back porch and

horizontal sync pulse

· fast recovery from impulse noise

· excellent temperature stability

· 0.5 V to 4 Vpp input signal amplitude with 5 V

supply

· well-controlled clamp discharge current and

slicing level

· programmable horizontal scan rate (up to 130 kHz)

· composite, vertical, back porch, odd/even

(GS1881, GS4881), horizontal (GS4981) outputs

· predictable vertical output pulse width with

default trigger for non-standard video signals

· 5 V to 12 V supply voltage range

· pin compatible with LM1881 sync separator

APPLICATION CHOOSE DEVICE:

Direct LM1881 Replacement

GS1881

with Improved Performance

New Applications

GS4881

Substitution for LM1881

New Applications Requiring

GS4981

Horizontal Sync Output

SELECTION CHART

SET

BACK PORCH

ODD/EVEN

GROUND

8 PIN DIP

8 PIN SOIC

COMPOSITE

SYNC OUT

COMPOSITE

VIDEO IN

VERTICAL

SYNC OUT

SET

BACK PORCH

GROUND

8 PIN DIP

8 PIN SOIC

GS4981

COMPOSITE

SYNC OUT

COMPOSITE

VIDEO IN

VERTICAL

SYNC OUT

HORIZONTAL

GS1881, GS4881

PIN CONNECTIONS

Revision Date: October 1995

Patent No. 5,432,559

520 - 23 - 03

Supply Voltage

4.5

13.2

Supply Current

Outputs at Logic 1 V

= 5 V

4.6

6.5

= 12 V

5.0

7.0

Video Input (Pin 2)

(a) Signal Level

= 5 V

0.5

Vp-p

(b) Clamp Current

Charge

500

650

850

Discharge - normal

- Nosync flag raised

115

130

(d) Sync Tip Clamp Voltage

1.55

Sync Slice Level

Relative to sync tip clamp voltage

SET

Pin Reference Voltage (Pin 6)

See Note 1

1.14

1.24

1.34

Composite Sync Out (Pin 1)

See Note 2

Delay from Video

= 15p

Back Porch Pulse Out (Pin 5)

= 15p

(a) Delay from Rising

Edge of Sync

400

500

650

(b) Pulse Width

2.0

2.5

3.2

Vertical Sync Out (Pin 3)

(a) Pulse Width

Serrations during vertical interval

197.7

(b) Default Starting Time

No serrations during the vertical interval

Horizontal Scan Rate

Modified R

SET

130

kHz

Logic Outputs

(a) V

= 40

A V

= 5 V

4.2

4.6

= 12 V

11.2

11.6

= 1.6 mA V

= 5 V

2.4

3.4

= 12 V

9.4

10.4

(b) V

= -1.6 mA

0.3

0.6

PARAMETER

CONDITIONS MIN TYP MAX UNITS

GS1881 ELECTRICAL CHARACTERISTICS

= 5 V, R

SET

= 680 k

, T

= 25

C, unless otherwise specified)

Note 1: When placing the R

SET

resistor and the 0.1

F decoupling capacitor careful attention should be made to ensure that they are as close

as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.

Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.

CAUTION

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE

EXCEPT AT A STATIC-FREE WORKSTATION

ORDERING INFORMATION

Part Number Package Type Temperature Range

GS1881 - CDA

8 PDIP

to 70

GS1881 - CKA

8 SOIC

to 70

GS1881 - CTA

8 TAPE

to 70

GS1881 - IDA

8 PDIP

-25

to 85

GS1881 - IKA

8 SOIC

-25

to 85

GS1881 - ITA

8 TAPE

-25

to 85

520 - 23 - 03

Supply Voltage

4.5

13.2

Supply Current

Outputs at Logic 1 V

= 5 V

4.6

6.5

= 12 V

5.0

7.0

Video Input (Pin 2)

(a) Signal Level

= 5 V

0.5

Vp-p

(b) Clamp Current

Charge

500

650

850

Discharge - normal

- Nosync flag raised

115

Video input held high

130

(d) Sync Tip Clamp Voltage

1.55

Sync Slice Level

Relative to sync tip clamp voltage

SET

Pin Reference Voltage (Pin 6)

See Note 1

1.14

1.24

1.34

Composite Sync Out (Pin 1)

See Note 2

Delay from Video

= 15p

Back Porch Pulse Out (Pin 5)

= 15p

(a) Delay from Rising

Edge of Sync

400

500

650

(b) Pulse Width

2.0

2.5

3.2

Vertical Sync Out (Pin 3)

(a) Pulse Width

Serrations during vertical interval

197.7

(b) Default Starting Time

No serrations during the vertical interval

Horizontal Scan Rate

Modified R

SET

130

kHz

Logic Outputs

(a) V

= 40

A V

= 5 V

4.2

4.6

= 12 V

11.2

11.6

= 1.6 mA V

= 5 V

2.4

3.4

= 12 V

9.4

10.4

(b) V

= -1.6 mA

0.3

0.6

PARAMETER

CONDITIONS MIN TYP MAX UNITS

GS4881 ELECTRICAL CHARACTERISTICS

= 5 V, R

SET

= 680 k

, T

= 25

C, unless otherwise specified)

ORDERING INFORMATION

Part Number Package Type Temperature Range

GS4881 - CDA

8 PDIP

to 70

GS4881 - CKA

8 SOIC

to 70

GS4881 - CTA

8 TAPE

to 70

GS4881 - IDA

8 PDIP

-25

to 85

GS4881 - IKA

8 SOIC

-25

to 85

GS4881 - ITA

8 TAPE

-25

to 85

Note 1: When placing the R

SET

resistor and the 0.1

F decoupling capacitor careful attention should be made to ensure that they are as close

as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.

Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.

520 - 23 - 03

Supply Voltage

4.5

13.2

Supply Current

Outputs at Logic 1 V

= 5 V

4.6

6.5

= 12 V

5.0

7.0

Video Input (Pin 2)

(a) Signal Level

= 5 V

0.5

Vp-p

(b) Clamp Current

Charge

500

650

850

Discharge - normal

- Nosync flag raised

115

130

(d) Sync Tip Clamp Voltage

1.55

Sync Slice Level

Relative to sync tip clamp voltage

SET

Pin Reference Voltage (Pin 6)

See Note 1

1.14

1.24

1.34

Composite Sync Out (Pin 1)

See Note 2

Delay from Video

= 15p

Back Porch Pulse Out (Pin 5)

= 15p

(a) Delay from Rising

Edge of Sync

400

500

650

(b) Pulse Width

2.0

2.5

3.2

Vertical Sync Out (Pin 3)

(a) Pulse Width

Serrations during vertical interval

197.7

(b) Default Starting Time

No serrations during the vertical interval

Horizontal Sync Out (Pin 7)

= 15p

(a) Delay from Video

190

290

(b) Pulse Width

5.0

7.0

9.0

Horizontal Scan Rate

Modified R

SET

130

kHz

Logic Outputs

(a) V

= 40

A V

= 5 V

4.2

4.6

= 12 V

11.2

11.6

= 1.6 mA V

= 5 V

2.4

3.4

Note 3

= 12 V

9.4

10.4

(b) V

= -1.6 mA

0.3

0.6

GS4981 ELECTRICAL CHARACTERISTICS

= 5 V, R

SET

= 680 k

, T

= 25

C, unless otherwise specified)

Note 1: When placing the R

SET

resistor and the 0.1

F decoupling capacitor careful attention should be made to ensure that they are as close

as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.

Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.

Note 3: Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 10 k

pull-up to V

PARAMETER

CONDITIONS MIN TYP MAX UNITS

ORDERING INFORMATION

Part Number Package Type Temperature Range

GS4981 - CDA

8 PDIP

to 70

GS4981 - CKA

8 SOIC

to 70

GS4981 - CTA

8 TAPE

to 70

GS4981 - IDA

8 PDIP

-25

to 85

GS4981 - IKA

8 SOIC

-25

to 85

GS4981 - ITA

8 TAPE

-25

to 85

520 - 23 - 03

TYPICAL PERFORMANCE CHARACTERISTICS

= 5V, T

= 25

C unless otherwise shown)

700

600

500

400

300

200

100

VERTICAL DEFAULT TIME (

BACK PORCH DELAY (ns)

3000

2500

2000

1500

1000

500

BACK PORCH WIDTH (ns)

NOSYNC DELAY TIME (

SET

)

HORIZONTAL WIDTH (

110

100

SET

)

Fig. 6 Nosync Delay Time vs R

SET

0 100 200 300 400 500 600 700

SET

)

Fig. 4 Back Porch Width vs R

SET

0 100 200 300 400 500 600 700

SET

)

Fig. 2 Vertical Sync Default Starting Time

vs R

SET

700

600

500

400

300

200

100

15 35 55 75 95 115 135

SCAN RATE (kHz)

Fig. 1 R

SET

vs Scan Rate

0 100 200 300 400 500 600 700

SET

)

Fig. 3 Back Porch Delay vs R

SET

8000

7000

6000

5000

4000

3000

2000

1000

0 100 200 300 400 500 600 700

SET

)

Fig. 5 Horizontal Width vs R

SET

520 - 23 - 03

TEMPERATURE CHARACTERISTICS

= 5V, R

SET

= 680 k

unless otherwise shown)

Commercial Temperature Range (0 - 70

600

500

400

300

200

100

-100

-200

-300

-25 -15 -5 5 15 25 35 45 55 65 75 85

TEMPERATURE (

Fig. 12 Horizontal Width Variation

vs Temperature

COMPOSITE SYNC DELAY

VARIATION (ns)

-2

-4

-6

Fig. 7 Composite Sync Delay Variation

vs Temperature

TEMPERATURE (

-25 -15 -5 5 15 25 35 45 55 65 75 85

TEMPERATURE (

Fig. 8 Clamping Current vs Temperature

850

740

650

550

450

350

CLAMPING CURRENT (

TEMPERATURE (

Fig. 9 Back Porch Delay Variation

vs Temperature

-10

-20

BACK PORCH DELAY VARIATION (ns)

-25 -15 -5 5 15 25 35 45 55 65 75 85

TEMPERATURE (

Fig. 11 Horizontal Delay Variation

vs Temperature

-5

-25 -15 -5 5 15 25 35 45 55 65 75 85

TEMPERATURE (

Fig. 10 Back Porch Width Variation

vs Temperature

125

100

-25

-50

-75

100

-125

BACK PORCH WIDTH VARIATION (ns)

HORIZONTAL WIDTH VARIATION (ns)

HORIZONTAL DELAY VARIATION (ns)

520 - 23 - 03

BACK PORCH OUTPUT (pin 5)

In an NTSC composite video signal, horizontal sync pulses are
followed by the back porch interval. The device generates a
negative going pulse on pin 5 during this time. It is delayed
typically 500 ns from the rising edge of sync and has a typical
width of 2.5

s. Both of these times are set by the external R

SET

resistor.

During the pre-equalizing, vertical sync, and post-equalizing
periods, composite sync doubles in frequency. The GS4881
and GS4981 maintain the back porch output at the horizontal
rate due to Back Porch Enable (BPEN), generated by the
internal windowing circuit, which forces back porch to be
asserted at the horizontal rate. This gating circuit is also the
reason for the excellent impulse noise immunity of the back
porch output as shown in Figure 14.

The GS1881 does not gate the Back Porch which allows for
total pin compatibility with the LM1881.

VERTICAL SYNC OUTPUT (pin 3)

The vertical sync interval is detected by integrating the
composite sync pulses. The first broad vertical sync pulse
causes an internal capacitor to charge past a fixed threshold
and raises an internal vertical flag. Once the vertical flag is
raised, the positive edge of the next serration clocks out the
vertical output. When the vertical sync interval ends, the first
post equalizing pulse is unable to charge the capacitor
sufficiently, causing the internal vertical flag to go high. The
rising edge of the second post-equalizing pulse then clocks
out the high flag to end the vertical sync pulse. The vertical
output is clocked in and out and therefore is a fixed width of
197.7

s (3H + 4.7

s + 2.3

s). In the case of a non-standard

vertical interval that has no serrations, a second internal
capacitor is charged and clocks the vertical pulse out after
typically 65

s. In this case the end of the vertical pulse will still

be the rising edge of the second post-equalizing pulse. As the
vertical detector is designed as a true integrator, it provides
improved noise immunity.

VIDEO INPUT

IMPULSE NOISE

COMPOSITE SYNC RECOVERY TIME without INCREASED DISCHARGE CURRENT (LM1881)

RECOVERY TIME T1

COMPOSITE SYNC RECOVERY TIME with INCREASED DISCHARGE CURRENT (GS1881, GS4881, GS4981)

RECOVERY TIME

T1 / 10

Fig. 14 Back Porch Noise Immunity

Back

Porch

Output

GS4881
GS4981

Video
Input

Impulse
Noise

CIRCUIT DESPCRIPTION

The block diagrams for the GS1881, GS4881 and GS4981,

are shown in Figures 17 through 19, with timing diagrams for

the devices shown in Figure 20.

When stimulated by a composite input signal, the GS1881

and GS4881 sync separators output composite sync,

vertical sync, back porch, and odd/even field information.

The GS4981 substitutes the odd/even output of the GS4881

with a horizontal output. An external resistor on pin 6 is used

to define internal currents allowing the devices to accommodate

horizontal scan rates from 15 kHz to 130 kHz.

COMPOSITE VIDEO INPUT (pin 2) and COMPOSITE
SYNC OUTPUT (pin 1)

Composite video is AC coupled via an external coupling

capacitor to pin 2. The device clamps the sync tip of the input

video to 1.5 V ( V

clamp

) and then slices at 77 mV above the

clamp voltage ( V

slice

). The resultant signal, provided at

pin 1, is a reproduction of the input signal with the active video

portion removed. As V

clamp

and V

slice

are supply and input

signal independent, for 0.5 V p-p signals (sync height of 143

mV) slicing will occur at just above the 50% point and for 2 V

p-p signals (sync height of 572 mV) slicing will occur at

approximately 13% of sync height.

The video signal path and composite sync slicing circuitry

have been optimized and compensated to achieve a low

propagation delay that is stable over temperature. The typical

delay is 60 ns with less than 3 ns drift over the commercial

temperature range.

The typical input clamp discharge current is 11

A. This

current is optimal under normal operating circumstances but
needs to be increased when the clamp is trying to recover
from negative going impulse noise. The device improves the
recovery time by raising a NOSYNC flag when there has not
been a sync pulse for approximately 1

horizontal lines.

When this flag is raised the discharge current is increased by
85

A so that the recovery time is sped up by nearly 10 times.

Figure 13 shows a comparison between the recovery times
with and without the increased discharge current.

Fig. 13 Impulse Noise: Recovery Time Comparison

520 - 23 - 03

ODD/EVEN FIELD OUTPUT (pin 7 GS1881, GS4881)

NTSC PAL and SECAM composite video standards are
interlaced video schemes and therefore have odd and even
fields. For odd fields the first broad vertical sync pulse is
coincident with the start of horizontal, while for even fields the
first broad vertical sync pulse starts in the middle of a horizontal
line. Therefore by comparing the vertical sync with an internally
generated horizontal sync the odd/even field information is
determined. This output is clocked out by the falling edge of
vertical sync. The odd/even output is low during even fields
and high during odd fields. This method of detecting odd and
even fields is very noise tolerant.

Noise during the pre-equalizing pulses does not affect the
output since the field decision is made at the beginning of the
vertical interval. This noise immunity is displayed in Figure 15
in which an extra pre-equalizing pulse has been added to the
video input with no negative effect on the odd/even field
information.

Video
Input

Odd/Even
Output

Even Odd

HORIZONTAL OUTPUT (pin 7 GS4981)

As mentioned above, the odd/even field output of the
GS1881 and GS4881 is generated by comparing vertical
sync with an internal horizontal sync signal. This horizontal
sync signal is a true horizontal signal (i.e. maintained during
the vertical interval) and is outputted on pin 7 for the
GS4981. A delay of 190 ns from the video input and a width
of 6.5

s are typically characteristics for this signal.

The windowing circuit which generates horizontal provides
excellent impulse noise immunity as shown in Figure 16. This
output buffer is an open collector stage with an internal
10 k

pull up resistor.

Fig. 15 Odd/Even Output

Impulse
Noise

Video
Input

Horizontal
Output

Fig. 16 Horizontal Output

520 - 23 - 03

VIDEO

0.01µF

CH1

CH2

680k

0.1µ

0.1µF

CH1

VIDEO

CH2

680k

0.1µ

APPLICATION NOTES

(1) Choosing the Appropriate Input Coupling Capacitor to
Optimize Slicing Level and Hum Rejection

The video designer can adjust the slicing level by choosing the
value of the input coupling capacitor. The relationship between
slicing level and input coupling capacitor is described by the
following equation.

SLICE

T = V

DROOP

where:

DIS

= clamp discharge current = 11

T = T

LINE

- T

SYNC

= (63.5

s - 4.7

= input coupling capacitor

DIS

137

127

117

107

SLICING LEVEL (mV)

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

INPUT COUPLING CAPACITOR (

Fig. 21 Slicing Level vs Input Coupling Capacitor

Figure 21 is a graphical representation of this equation and
photographs 1 and 2 show the input video waveforms
for 0.1

F and 0.01

F input capacitors respectively. The

advantage in choosing a smaller input coupling capacitor, is
increased hum rejection as the following analyses illustrates.

Test Circuit 1

Test Circuit 2

Photograph 2

Photograph 1

CH1

CH2

CH1

CH2

520 - 23 - 03

CLAMP

VIDEO
INPUT

CLIP

- +

680k

0.1µ

(2) FIltering

In order to keep the input to output delay small and temperature
stable, no chrominance filtering is done within the device.
External filtering may be necessary if the input signal contains
large chrominance components (less than 77 mV from sync
tip) or has significant amounts of high frequency noise. This
filter can be a simple low pass RC network constructed by a
resistance (R

) in series with the source and a capacitor (C

)

to ground. A single pole low pass filter having a corner
frequency of approximately 500 kHz will provide ample
bandwidth for passing sync pulses with almost 18 dB
attenuation at 3.58 MHz. Care should be taken in choosing
the value of the series resistor in the filter since the source
resistance seen by the sync separator affects its performance.

As the source resistance rises, the video input sync tip starts
to be clipped due to the clamping current during the sync.
This clamping current is relatively large due to the
non-symmetric duty cycle of video. To a good approximation
the amount of sync clamp current can be calculated as
follows:

(

CLAMP

) (T

SYNC

) = (

DIS

) (T

LINE

- T

SYNC

)

CLAMP

(4.7

s) = (11

A) (63. 5

s - 4.7

CLAMP

= 137.6

This clamp current flows in the source resistance causing a
voltage drop equal to :

CLIP

= (

CLAMP

) (R

)

= (137.6

) (R

)

The interfering hum component is defined by:

HUM

(t) = V

cos(2

HUM

where: V

= Peak voltage of AC hum

HUM

= Frequency of hum (50 Hz or 60 Hz)

The maximum rate of change of this hum signal occurs at the
zero crossing points and is:

HUM

t =

2 2

Since the horizontal scan period is much faster than the period
of the interference ( 63.5

s << 1/

HUM

)

a good approximation

is to assume that the maximum line to line voltage change
resulting from the interfering hum is:

HUM

LINE

where: T

LINE

= 63.5

The total line to line voltage change (

) can then be calculated

by adding the hum component (

HUM

) and the droop

component (V

DROOP

). This calculation results in two cases:

To correct for

in case A, the input stage must be able to

charge the input capacitor

volts in 4.7

This is not a

constraint as the typical clamping current of 650

A can

accomplish this for practical values of coupling capacitor.

58.8 mV

4.7

verifying that there is enough clamping current

= 29.4 mV + 29.4 mV = 58.8 mV

. i = 0.022

= 275

which is less than 650

( )

AVG

Fig. 22 Simple Chrominance Filtering

Case A

Case B

HUM

+ V

DROOP

. V

DROOP

= (63.5

- 4.7

) = 29.4 mV

0.022

The only way to compensate for

in case B is to make

DROOP

HUM

. V

DROOP

is increased by decreasing the input

coupling capacitor value. Therefore the video designer can

increase hum rejection by decreasing the value of this capacitor.

The following is a numerical example:

choosing C

= 0.022

the maximum amount of 60 Hz hum that could be rejected
would be when:

DROOP

HUM

= V

HUM

LINE

. V

= =1.23v

PEAK

HUM

DROOP

29.4mV

HUM

LINE

(60) (63.5

)

520 - 23 - 03

VIDEO

0.1µF

CH1

CH2

560

680k

0.1µ

Photograph 3 shows the amount of sync clipping for a 560

source resistor. A graph of V

CLIP

versus R

is shown in

Figure 23, and Figure 24 shows the corresponding capacitor
value for a particular series resistor to provide a corner
frequency of 500 kHz.

In applications where signal levels are small the amount of
attenuation should be minimized. It follows from Figure 23 and
Figure 24 that in order to minimize attenuation a small series
resistor and a larger capacitor to ground should be chosen.
This however, increases the capacitive loading of the signal
source.

Another way to minimize the amount of attenuation is to control
the source resistance seen by the sync separator by using a
PNP emitter follower (Figure 25). A PNP emitter follower works
well to drive the sync separator, and does not require much
DC current because the transistor provides the current when
it is needed during sync. Figure 26 is a typical application
circuit that minimizes sync tip clipping.

Test Circuit 3

Fig. 25 PNP Emitter Follower Buffer

Photograph 3

100

0 100 200 300 400 500 600 700

SERIES RESISTOR (

)

CLIP

(mV)

SERIES RESISTOR (

)

0 100 200 300 400 500 600 700

C (nF)

Fig. 23 V

CLIP

vs Series Resistor

Fig. 24 C vs Series Resistor

5.6k

VIDEO
INPUT

FILTER

-5V

680k

0.1µ

-5V

VIDEO
INPUT

5.6k

56p

5.6k

680k

0.1µ

Fig. 26 Typical NTSC Application Circuit

CH1

CH2

520 - 23 - 03

COMPOSITE

VIDEO INPUT

525 1 2 3 4 5 6 7 8

HORIZONTAL OUTPUT

GS4981

VERTICAL SYNC OUTPUT

GS4981

ODD/EVEN OUTPUT

START OF ODD FIELD

COMPOSITE

VIDEO INPUT

HORIZONTAL

GS4981

ODD/EVEN OUTPUT

VERTICAL SYNC OUTPUT

GS4981

START OF EVEN FIELD

263 264 265 266 267 268 269 270

(3) Deriving Odd/Even Using the GS4981

Odd/even field information can be derived using the vertical
and horizontal outputs from the GS4981 along with an external
positive edge D flip/flop. The horizontal output is used
as the D input and the vertical output as the clock, as
shown in Figure 27.

Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.

DOCUMENT
IDENTIFICATION

PRODUCT PROPOSAL
This data has been compiled for market investigation purposes
only, and does not constitute an offer for sale.

ADVANCE INFORMATION NOTE
This product is in development phase and specifications are
subject to change without notice. Gennum reserves the right to
remove the product at any time. Listing the product does not
constitute an offer for sale.

PRELIMINARY
The product is in a preproduction phase and specifications are
subject to change without notice.

DATA SHEET
The product is in production. Gennum reserves the right to
make changes at any time to improve reliability, function or
design, in order to provide the best product possible.

5 - 12V

BACK PORCH
OUTPUT

0.1µF

COMPOSITE

SYNC OUTPUT

COMPOSITE

VIDEO INPUT

VERTICAL

SYNC OUTPUT

HORIZONTAL

0.1µF

R SET

680k

GS4981

D FLIP/FLOP

ODD/EVEN
OUTPUT

D Q

CLK Q

At the start of an odd field the vertical output ends in the middle
of the horizontal line and a high will be latched. At the start of
an even field, the vertical output ends near the beginning of
the horizontal line and since the horizontal output is low, a low
will be latched. This timing sequence is shown in Figure 28.

Fig. 27 Derivation of Odd/Even with GS4981

Fig. 28 Timing Diagram

REVISION NOTES

The only change from 520-23-02 to 520-23-03 is that the document has been
upgraded to a full DATA SHEET. It is no longer Preliminary.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS1881-CKA

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: GS1881-CKA