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Электронный компонент: GS4901B

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www.gennum.com
GS4901B/GS4900B
SD Clock and Timing Generator
with GENLOCK
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
1 of 95
Key Features
Video Clock Synthesis
Pre-programmed for 4 video clock periods (14.32 MHz,
27 MHz, 36 MHz, and 54 MHz)
Accuracy of free-running clock frequency limited only by
crystal reference
One differential and two single-ended video clock outputs
Each clock may be individually delayed for skew control
Video output clock may be directly connected to
Gennum's serializers for a SMPTE-compliant SDI output
Audio Clock Synthesis (GS4901B only)
Three audio clock outputs
Generates any audio clock up to 512*96kHz
Pre-programmed for 7 audio clocks
Timing Generation
Generates up to 8 timing signals at a time
Choose from 9 pre-programmed timing signals: H and V
sync and blanking, F Sync, F Digital, AFS (GS4901B
only), Display Enable, 10FID, and up to 4 user-defined
timing signals
Pre-programmed to generate timing for 9 different video
formats
Genlock Capability
Clocks may be free-running or genlocked to an input
reference with a variable offset step size of 100-200ps
(depending on exact clock frequency)
Variable timing offset step size of 100-200ps up to one
frame
Output may be cross-locked to a different input reference
Freeze operation on loss of reference
Optional crash or drift lock on application of reference
Automatic input format detection
General Features
Reduces design complexity and saves board space -
9mm x 9mm package plus crystal reference replaces
multiple VCXOs, PLLs and timing generators
Pb-free and RoHS Compliant
Low power operation typically 300mW
1.8V core and 1.8V or 3.3V I/O power supplies
64-PIN QFN package
Applications
Video cameras; Digital audio and/or video recording/play
back devices; Digital audio and/or video processing
devices; Computer/video displays; DVD/MPEG devices;
Digital Set top boxes; Video projectors; High definition
video systems; Multi-media PC applications
Description
The GS4901B is a highly flexible, digitally controlled
clock synthesis circuit and timing generator with
genlock capability. It can be used to generate video and
audio clocks and timing signals, and allows multiple
devices to be genlocked to an input reference.
The GS4900B includes all the features of the GS4901B,
but does not offer audio clocks or AFS pulse generation.
The GS4901B/GS4900B will recognize input reference
signals conforming to 36 different video standards, and
will genlock the output timing information to the
incoming reference. The GS4901B/GS4900B supports
cross-locking, allowing the output to be genlocked to an
incoming reference that is different from the output
video standard selected.
The user may select to output one of 4 different video
sample clock rates. The chosen clock frequency can be
further divided using internal dividers, and is available
on two video clock outputs and one LVDS video clock
output pair. The video clocks are frequency and
phased-locked to the horizontal timing reference, and
can be individually delayed with respect to the timing
outputs for clock skew control.
Eight user-selectable timing outputs are provided that
can automatically produce the following timing signals
for 9 different video formats: HSync, Hblanking, VSync,
Vblanking, F sync, F digital, AFS (GS4901B only), DE,
and 10FID. These timing outputs may be locked to the
input reference signal for genlock timing and may be
phase adjusted via internal registers.
In addition, the GS4901B provides three audio sample
clock outputs that can produce audio clocks up to 512fs
with fs ranging from 9.7kHz to 96kHz. Audio to video
phasing is accomplished by an external 10FID input
reference, a 10FID signal specified via internal
registers, or a user-programmed audio frame
sequence.
The GS4901B/GS4900B is Pb-free, and the
encapsulation compound does not contain halogenated
flame retardant (RoHS Compliant).
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
2 of 95
GS4901B Functional Block Diagram
Clock Synthesis
and Control
Flywheel and Video
Timing Generator
Input Reference
Rate Identification
and Control
Crosspoint
Video Clock
Divide
Audio Clock
Divide
3x Video Clock
Delay Adjust
Application Programming Interace
HSYNC
VSYNC
FSYNC
10FID
LOCK_LOST
REF_LOST
VID_STD[5:0]
ASR_SEL[2:0]
X1
X2
TIMING_OUT_8
TIMING_OUT_7
TIMING_OUT_6
TIMING_OUT_5
TIMING_OUT_4
TIMING_OUT_3
TIMING_OUT_2
TIMING_OUT_1
PCLK1
PCLK2
PCLK3
ACLK1
ACLK2
ACLK3
PCLK3
GENLOCK
pclk
aclk_512
aclk_384
10FID
DE
H blanking
H sync
user[4:1]
ref_rate
27MHz
Clock
Phase
Adjust
JT
AG/HOST
SCLK_TCLK
SDIN_TDI
SDOUT_TDO
CS_TMS
V blanking
V sync
F digital
F sync
AFS
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
3 of 95
GS4900B Functional Block Diagram
Clock Synthesis
and Control
Flywheel and Video
Timing Generator
Input Reference
Rate Identification
and Control
Crosspoint
Video Clock
Divide
3x Video Clock
Delay Adjust
Application Programming Interace
HSYNC
VSYNC
FSYNC
10FID
REF_LOST
VID_STD[5:0]
X1
X2
TIMING_OUT_8
TIMING_OUT_7
TIMING_OUT_6
TIMING_OUT_5
TIMING_OUT_4
TIMING_OUT_3
TIMING_OUT_2
TIMING_OUT_1
PCLK1
PCLK2
PCLK3
PCLK3
GENLOCK
pclk
10FID
DE
H blanking
H sync
user[4:1]
ref_rate
27MHz
Clock
Phase
Adjust
JT
AG/HOST
SCLK_TCLK
SDIN_TDI
SDOUT_TDO
CS_TMS
V blanking
V sync
F digital
F sync
LOCK_LOST
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
4 of 95
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................8
1.1 GS4901B Pin Assignment ..............................................................................8
1.2 GS4900B Pin Assignment ..............................................................................9
1.3 Pin Descriptions ............................................................................................10
1.4 Pre-Programmed Recognized Video Standards ...........................................20
1.5 Output Timing Signals ...................................................................................24
2. Electrical Characteristics.........................................................................................28
2.1 Absolute Maximum Ratings ..........................................................................28
2.2 DC Electrical Characteristics ........................................................................28
2.3 AC Electrical Characteristics .........................................................................30
2.4 Solder Reflow Profiles ...................................................................................33
3. Detailed Description ................................................................................................34
3.1 Functional Overview .....................................................................................34
3.2 Modes of Operation ......................................................................................34
3.2.1 Genlock Mode......................................................................................35
3.2.2 Free Run Mode....................................................................................38
3.3 Output Timing Format Selection ...................................................................39
3.4 Input Reference Signals ................................................................................40
3.4.1 HSYNC, VSYNC, and FSYNC.............................................................40
3.4.2 10FID ...................................................................................................41
3.4.3 Automatic Polarity Recognition............................................................41
3.5 Reference Format Detector ..........................................................................42
3.5.1 Horizontal and Vertical Timing Characteristic Measurements .............42
3.5.2 Input Reference Validity.......................................................................43
3.5.3 Behaviour on Loss and Re-acquisition of the Reference Signal..........44
3.5.4 Allowable Frequency Drift on the Reference .......................................46
3.6 Genlock .........................................................................................................46
3.6.1 Adjustable Locking Time......................................................................47
3.6.2 Adjustable Loop Bandwidth .................................................................48
3.6.3 Locking to Digital Timing from a Deserializer ......................................51
3.7 Clock Synthesis ............................................................................................52
3.7.1 Video Clock Synthesis .........................................................................52
3.7.2 Audio Clock Synthesis (GS4901B only) ..............................................53
3.8 Video Timing Generator ................................................................................57
3.8.1 10 Field ID Pulse .................................................................................57
3.8.2 Audio Frame Synchronizing Pulse (GS4901B only) ............................58
3.8.3 USER_1~4...........................................................................................59
GS4901B/GS4900B Preliminary Data Sheet
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April 2006
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3.8.4 TIMING_OUT Pins...............................................................................61
3.9 Extended Audio Mode for HD Demux using the Gennum Audio Core .........62
3.10 GSPI Host Interface ....................................................................................63
3.10.1 Command Word Description..............................................................64
3.10.2 Data Read and Write Timing .............................................................64
3.10.3 Configuration and Status Registers ...................................................66
3.11 JTAG ...........................................................................................................87
3.12 Device Power-Up ........................................................................................88
3.12.1 Power Supply Sequencing.................................................................88
3.13 Device Reset ...............................................................................................88
4. Application Reference Design.................................................................................89
4.1 GS4901B Typical Application Circuit ............................................................89
4.2 GS4900B Typical Application Circuit ............................................................90
5. References & Relevant Standards..........................................................................91
6. Package & Ordering Information.............................................................................92
6.1 Package Dimensions ....................................................................................92
6.2 Recommended PCB Footprint ......................................................................93
6.3 Packaging Data .............................................................................................93
6.4 Ordering Information .....................................................................................94
7. Revision History ......................................................................................................95