www.gennum.com
GS9062 HD-LINXTM II
SD-SDI and DVB-ASI Serializer
GS9062 Data Sheet
22209 - 5
May 2005
1 of 46
Key Features
SMPTE 259M-C compliant scrambling and
NRZ
NRZI encoding (with bypass)
DVB-ASI sync word insertion and 8b/10b encoding
adjustable loop bandwidth
user selectable additional processing features
including:
ANC data checksum, and line number
calculation and insertion
TRS and EDH packet generation and insertion
illegal code remapping
internal flywheel for noise immune TRS generation
20-bit / 10-bit CMOS parallel input data bus
27MHz / 13.5MHz parallel digital input
automatic standards detection and indication
Pb-free and RoHS compliant
1.8V core power supply and 3.3V charge pump
power supply
3.3V digital I/O supply
JTAG test interface
small footprint compatible with GS1560A, GS1561,
GS1532, and GS9060
Applications
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
Description
The GS9062 is a dual-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1525 Voltage Controlled Oscillator, a transmit
solution can be realized for SD-SDI and DVB-ASI
applications.
In addition to serializing the input, the GS9062 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats. An appropriate parallel
clock input signal is also required.
The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode and
adjustable signal swing.
The GS9062 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
re-map illegal code words and insert SMPTE 352M
payload identifier packets. All processing features are
optional and may be enabled/disabled via external
control pin(s) and/or host interface programming.
The GS9062 is Pb-free, and the encapsulation
compound does not contain halogenated flame
retardant (RoHS compliant).
GS9062 Data Sheet
22209 - 5
May 2005
2 of 46
GS9062 Functional Block Diagram
SDO
SDO
SDO_EN/DIS
RSET
CP_CAP
H
V
F
DIN[19:0]
IOPROC_EN/DIS
DVB_ASI
I/O
Buffer
&
demux
SMPTE
352M
generation
TRS insertion,
data blank, code-
re-map and
flywheel
dvb-asi
bypass
RESET_TRST
Reset
HOST Interface /
JTAG test
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JT
AG/HOST
LOCKED
V
CO
VCO
LF
LB_CONT
VCO_VCC
VCO_GND
20bit/10bit
DVB-ASI sync
word insert &
8b/10b encode
EDH
generation
& SMPTE
scramble
PCLK
BLANK
DETECT_TRS
SMPTE_BYP
ASS
Phase detector, charge
pump, VCO control &
power supply
P -> S
GS9062 Data Sheet
22209 - 5
May 2005
3 of 46
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics........................................................................................12
2.1 Absolute Maximum Ratings ..........................................................................12
2.2 DC Electrical Characteristics ........................................................................12
2.3 AC Electrical Characteristics.........................................................................13
2.4 Solder Reflow Profiles...................................................................................15
2.5 Input/Output Circuits .....................................................................................16
2.6 Host Interface Maps......................................................................................18
2.6.1 Host Interface Map (Read only registers) ...........................................19
2.6.2 Host Interface Map (R/W configurable registers)................................20
3. Detailed Description ...............................................................................................21
3.1 Functional Overview .....................................................................................21
3.2 Parallel Data Inputs.......................................................................................21
3.2.1 Parallel Input in SMPTE Mode............................................................22
3.2.2 Parallel Input in DVB-ASI Mode..........................................................22
3.2.3 Parallel Input in Data-Through Mode..................................................22
3.2.4 Parallel Input Clock (PCLK) ................................................................23
3.3 SMPTE Mode................................................................................................23
3.3.1 Internal Flywheel.................................................................................23
3.3.2 HVF Timing Signal Extraction.............................................................24
3.4 DVB-ASI Mode..............................................................................................25
3.4.1 Control Signal Inputs ..........................................................................25
3.5 Data-Through Mode......................................................................................26
3.6 Additional Processing Functions...................................................................26
3.6.1 Input Data Blank .................................................................................26
3.6.2 Automatic Video Standard Detection..................................................26
3.6.3 Packet Generation and Insertion ........................................................28
3.7 Parallel-To-Serial Conversion .......................................................................34
3.8 Serial Digital Data PLL..................................................................................35
3.8.1 External VCO......................................................................................35
3.8.2 Lock Detect Output .............................................................................35
3.9 Serial Digital Output ......................................................................................36
3.9.1 Output Swing ......................................................................................36
3.9.2 Serial Digital Output Mute...................................................................36
3.10 GSPI Host Interface ....................................................................................37
GS9062 Data Sheet
22209 - 5
May 2005
4 of 46
3.10.1 Command Word Description.............................................................37
3.10.2 Data Read and Write Timing ............................................................38
3.10.3 Configuration and Status Registers ..................................................39
3.11 JTAG...........................................................................................................39
3.12 Device Power Up ........................................................................................41
3.13 Device Reset...............................................................................................41
4. Application Reference Design................................................................................42
4.1 Typical Application Circuit.............................................................................42
5. References & Relevant Standards.........................................................................43
6. Package & Ordering Information............................................................................44
6.1 Package Dimensions ....................................................................................44
6.2 Packaging Data.............................................................................................45
6.3 Ordering Information .....................................................................................45
7. Revision History .....................................................................................................46
GS9062 Data Sheet
22209 - 5
May 2005
5 of 46
1. Pin Out
1.1 Pin Assignment
DVB_ASI
IOPROC_EN/DIS
SDOUT_TDO
SDIN_TDI
SCLK_TCK
F
V
H
DIN0
DIN1
IO_GND
BLANK
CORE_GND
CORE_VDD
JTAG/HOST
CS_TMS
RESET_TRST
VCO_VCC
CP_GND
VCO_GND
LF
VCO
LOCKED
CP_CAP
CORE_GND
CORE_VDD
DIN19
DIN18
IO_VDD
PCLK
LB_CONT
VCO
DETECT_TRS
CP_VDD
PD_VDD
PD_GND
20bit/10bit
SMPTE_BYPASS
RSET
DIN17
IO_VDD
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
IO_GND
IO_VDD
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
IO_GND
1
80
NC
2
3
4
5
6
7
79
78
77
76
75
74
73
8
9
10
11
12
13
14
72
71
70
69
68
67
66
65
64
63
62
61
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
NC
CD_VDD
SDO
SDO
CD_GND
SDO_EN/DIS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RSV
NC
NC
9062
PDF 
ZIP