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Электронный компонент: GLT6200L08LL-85ST

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G -LINK
GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Aug 2001(Rev. 1.2)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
Low-power consumption.
-active: 30mA at 55ns.
-stand by :
10
A (CMOS input / output)
2
A (CMOS input / output, SL)
Single +2.7 to 3.6V power supply.
Equal access and cycle time.
55/70/85 ns access time.
1.0V data retention mode.
TTL compatible, tri-state input/output.
Automatic power-down when deselected.
Industrial grade (-40
C ~ 85
C)
available.
Package available: 32-sTSOP.
48Ball CSP-BGA
The GLT6200L08 is a low power CMOS Static
RAM organized as 262,144 x 8 bits. Easy memory
expansion is provided by an active LOW
CE1
an
active LOW
OE
, and Tri-state I/O's. This device has
an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking
chip Enable 1 (
CE1
) with Write Enable (
WE
) LOW.
Reading from the device is performed by taking Chip
Enable 1 (
CE1
) with Output Enable (
OE
) LOW
while Write Enable (
WE
) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance
state when the device is deselected : the outputs are
disabled during a write cycle.
The GLT6200L08 comes with a 1V data retention
feature and Lower Standby Power. The GLT6200L08
is available in a 32-pin sTSOP packages.
Function Block Diagram :
ROW DECODER
Cell
Array
SENSE AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
OE
WE
CE1
CE2
I/O
7
I/O
0
Column Address
Row Address
G -LINK
GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Aug 2001(Rev. 1.2)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configurations :
sTSOPI
GLT6200L08
A
16
A
7
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
26
25
24
23
GND
OE
A
10
14
27
28
I/O
7
I/O
6
20
A
0
7
WE
V
CC
15
16
29
30
31
32
A
11
A
9
A
8
A
13
CE
2
A
15
A
14
A
12
A
6
A
5
A
4
A
3
A
2
A
1
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
CE
1
A
17
48 Ball fpBGA :
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
1
A0
I/O4
I/O5
VSS
VCC
I/O6
I/O7
A9
2
A1
A2
NC
NC
NC
NC
OE
A10
3
CE2
WE
NC
NC
NC
NC
CE1
A11
4
A3
A4
A5
NC
NC
A17
A16
A12
5
A6
A7
NC
NC
NC
NC
A15
A13
6
A8
I/O0
I/O1
VCC
VSS
I/O2
I/O3
A14
Bottom View
Bottom View
Note
:
NC means no Ball.
Pin Descriptions:
Name
Function
A
0
A
17
Address Inputs
CE
1
and CE2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O
0
I/O
7
Data Input and Data Output
V
CC
2.7V~3.6V Power Supply
GND
Ground
NC
No Connection
G -LINK
GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Aug 2001(Rev. 1.2)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Truth Table:
CE
1
CE
2
WE
OE
Data
Mode
H
X
X
X
High-Z
Standby
X
L
X
X
High-Z
Standby
L
H
H
L
Data Out
Active, Read
L
H
H
H
High-Z
Active, Output Disable
L
H
L
X
Data Out
Active, Write
*Key : X = Don't Care, L = Low, H = High
Absolute Maximum Ratings*
Parameter
Symbol
Minimum
Maximum
Unit
Voltage on Any Pin Relative to Gnd
Vt
-0.5
Vcc+0.5
V
Power Dissipation
P
T
-
1.0
W
Storage Temperature (Plastic)
Tstg
-55
+150
C
Temperature Under Bias
Tbias
-40
+85
C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions ( T
A
= -25
C to + 85
C)
Parameter
Symbol
Min
Typ
Max
Unit
V
CC
2.7
3
3.6
V
Supply Voltage
Gnd
0.0
0.0
0.0
V
V
IH
2.0
-
V
CC
+0.2
V
Input Voltage
V
IL
-0.5*
-
0.6
V
* V
IL
min = -1.0V for pulse width less than t
RC
/2.
G -LINK
GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Aug 2001(Rev. 1.2)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
DC Operating Characteristics
( Vcc=2.7V to 3.6V, T
A
=-25
C to + 85
C)
55
70
85
Parameter
Sym.
Test Conditions
Min
Max
Min
Max
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= Max,
Vin = Gnd to V
CC
1
1
1
A
Output Leakage
Current
I
LO
CE
1
=V
IH
or CE2 = V
IH
V
CC
= Max, V
OUT
= Gnd to V
CC
1
1
1
A
Operating Power
Supply Current
I
CC
CE
1
=V
IL
,CE2 = V
IH
V
IN
=V
IH
or V
IL
, I
OUT
=0mA
3
3
3
mA
I
CC1
CE
1
=V
IL
,CE2 = V
IH
I
OUT
= 0mA,
Min Cycle, 100% Duty
30
30
25
mA
Average Operating
Current
I
CC2
CE
1
=0.2V
CE2 = V
CC
0.2V
I
OUT
= 0mA,
Cycle Time=1
s, 100% Duty
3
3
3
mA
Standby Power Supply
Current(TTL Level)
I
SB
CE
1
=V
IH
or CE2 = V
IL
0.5
0.5
0.5
mA
G6200L08LL
10
10
10
A
Standby Power Supply
Current (CMOS Level)
I
SB1
CE
1
V
CC
-
0.2V or
CE2
0.2V,
f=0
V
IN
0.2V or
V
IN
V
CC
-0.2V
G6200L08SL
2
2
2
A
Output Low Voltage
V
OL
I
OL
= 2 mA
0.4
0.4
0.4
V
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
2.4
2.4
V
Data Retention
Parameter
Sym.
Test Conditions
Min.
Max.
Unit
V
CC
for Data retention
V
DR
1.0
-
V
Data Retention Current
I
CCDR
-
2
A
Chip Deselect to Data Retention Time
t
CDR
0
-
ns
Operating Recovery Time
(2)
t
R
CE
1
V
CC
-0.2V or
CE
2
+0.2V,
V
IN
V
CC
-0.2V or
V
IN
0.2V
t
RC
-
ns
G -LINK
GLT6200L08
Ultra Low Power 256k x 8 CMOS SRAM
Aug 2001(Rev. 1.2)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
Data Retention Waveform
(TA = -25
C to + 85
C)
Data Retention Mode
Vcc
CE
V
DR
V
DR >= 1.0V
t
R
t
CDR
2.7V
2.7V
V
IH
V
IH
AC Test Conditions
AC Test Loads and Waveforms
C
L
*
TTL
Output Load Condition
*Including Scope and Jig Capacitance
C
L
= 30pf + 1TTL Load
Read Cycle
(3,9)
( Vcc=2.7V to 3.6V, T
A
=-25
C to + 85
C)
55
70
85
Unit Note
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
55
70
85
ns
Address Access Time
t
AA
55
70
85
ns
Chip Enable Access Time
t
ACE
55
70
85
ns
Output Enable Access Time
t
OE
40
40
40
ns
Output Hold from address Change
t
OH
10
10
10
ns
Chip Enable to Output in Low-Z
t
CLZ
10
10
10
ns
4,5
Chip Disable to Output in High-Z
t
CHZ
25
30
35
ns
4,5
Output Enable to Output in Low-Z
t
OLZ
5
5
5
ns
4,5
Output Disable to Output in High-Z
t
OHZ
20
25
30
ns
4,5
Power-Up Time
t
PU
0
0
0
ns
5
Power-Down Time
t
PD
55
70
85
ns
5
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Time
Input and Output Timing
Reference Level
5 ns
1.4V