G -LINK
GLT6400M08
Ultra Low Power 512k x 8 CMOS SRAM
Aug 2001(Rev.3.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features :
Description :
Low-power consumption.
-active: 30mA at 120ns.
-stand by :
20
A (CMOS input / output)
5
A (CMOS input / output, SL)
Single +2.3 to 2.7V power supply.
Equal access and cycle time.
85/120 ns access time.
1.0V data retention mode.
TTL compatible, tri-state input/output.
Automatic power-down when deselected.
Industrial grade (-40
C ~ 85
C)
availabel.
Package available: sTSOP and SOP.
The GLT6400M08 is a low power CMOS Static
RAM organized as 524,288 x 8 bits. Easy memory
expansion is provided by an active LOW
CE1
an
active LOW
OE
, and Tri-state I/O's. This device has
an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking
chip Enable 1 (
CE1
) with Write Enable (
WE
) LOW.
Reading from the device is performed by taking Chip
Enable 1 (
CE1
) with Output Enable (
OE
) LOW
while Write Enable (
WE
) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance
state when the device is deselected : the outputs are
disabled during a write cycle.
The GLT6400M08 comes with a 1V data retention
feature and Lower Standby Power. The
GLT6400M08 is available in a 32-pin sTSOP and
SOP packages.
Function Block Diagram :
ROW DECODER
Cell
Array
SENSE AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
OE
WE
CE1
CE2
I/O
7
I/O
1
Column Address
Row Address
G -LINK
GLT6400M08
Ultra Low Power 512k x 8 CMOS SRAM
Aug 2001(Rev.3.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configurations :
GLT6400M08 GLT6400M08
sTSOPI SOP
A
16
A
7
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
26
25
24
23
GND
OE
A
10
14
27
28
I/O
7
I/O
6
20
A
0
7
WE
V
CC
15
16
29
30
31
32
A
11
A
9
A
8
A
13
A
17
A
15
A
14
A
12
A
6
A
5
A
4
A
3
A
2
A
1
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
CE
1
A
18
1
2
3
4
5
6
7
9
10
11
12
13
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
18
A
16
A
14
A
12
A
6
A
5
A
3
A
2
A
1
A
0
I/O
0
GND
I/O
3
I/O
7
CE
A
10
OE
A
11
WE
A
15
A
7
A
4
I/O
1
I/O
2
I/O
4
I/O
5
I/O
6
A
9
A
8
A
13
A
17
V
CC
Pin Descriptions:
Name
Function
A
0
A
18
Address Inputs
CE
1
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O
0
I/O
7
Data Input and Data Output
V
CC
2.5V Power Supply
GND
Ground
NC
No Connection
Truth Table:
CE
1
WE
OE
Data
Mode
H
X
X
High-Z
Standby
L
H
L
Data Out
Active, Read
L
H
H
High-Z
Active, Output Disable
L
L
X
Data Out
Active, Write
*Key : X = Don't Care, L = Low, H = High
G -LINK
GLT6400M08
Ultra Low Power 512k x 8 CMOS SRAM
Aug 2001(Rev.3.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings*
Parameter
Symbol
Minimum
Maximum
Unit
Voltage on Any Pin Relative to Gnd
Vt
-0.5
Vcc+0.3
V
Power Dissipation
P
T
-
1.0
W
Storage Temperature (Plastic)
Tstg
-55
+150
C
Temperature Under Bias
Tbias
-40
+85
C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions ( T
A
= -25
C to + 85
C)
Parameter
Symbol
Min
Typ
Max
Unit
V
CC
2.3
2.5
2.7
V
Supply Voltage
Gnd
0.0
0.0
0.0
V
V
IH
2.0
-
V
CC
+0.2
V
Input Voltage
V
IL
-0.5*
-
0.6
V
* V
IL
min = -1.0V for pulse width less than t
RC
/2.
G -LINK
GLT6400M08
Ultra Low Power 512k x 8 CMOS SRAM
Aug 2001(Rev.3.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
DC Operating Characteristics
( Vcc=2.3V to 2.7V, T
A
=-25
C to + 85
C)
85
120
Parameter
Sym.
Test Conditions
Min
Max
Min
Max
Unit
Input Leakage Current
I
LI
V
CC
= Max,
Vin = Gnd to V
CC
1
1
A
Output Leakage
Current
I
LO
CE
1
=V
IH
V
CC
= Max, V
OUT
= Gnd to V
CC
1
1
A
Operating Power
Supply Current
I
CC
CE
1
=V
IL
,
V
IN
=V
IH
or V
IL
, I
OUT
=0mA
5
5
mA
I
CC1
CE
1
=V
IL
,
I
OUT
= 0mA,
Min Cycle, 100% Duty
45
30
mA
Average Operating
Current
I
CC2
CE
1
=0.2V
I
OUT
= 0mA,
Cycle Time=1
s, 100% Duty
5
5
mA
Standby Power Supply
Current(TTL Level)
I
SB
CE
1
=V
IH
0.3
0.3
mA
GLT6400M08
LL
20
20
A
Standby Power Supply
Current (CMOS Level)
I
SB1
CE
1
V
CC
-
0.2V or f=0
V
IN
0.2V or
V
IN
V
CC
-0.2V
GLT6400M08
SL
5
5
A
Output Low Voltage
V
OL
I
OL
= 2 mA
0.4
0.4
V
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
2.0
V
Data Retention
Parameter
Sym.
Test Conditions
Min.
Max.
Unit
V
CC
for Data retention
V
DR
1.0
-
V
Data Retention Current
I
CCDR
-
4
A
Chip Deselect to Data Retention Time
t
CDR
0
-
ns
Operating Recovery Time
(2)
t
R
CE
1
V
CC
-0.2V or
V
IN
V
CC
-0.2V or
V
IN
0.2V
t
RC
-
ns
G -LINK
GLT6400M08
Ultra Low Power 512k x 8 CMOS SRAM
Aug 2001(Rev.3.0)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
Data Retention Waveform
(TA = -25
C to + 85
C)
Data Retention Mode
Vcc
CE
V
DR
V
DR >= 1.0V
t
R
t
CDR
2.7V
2.7V
V
IH
V
IH
AC Test Conditions
AC Test Loads and Waveforms
C
L
*
TTL
Output Load Condition
*Including Scope and Jig Capacitance
C
L
= 30pf + 1TTL Load
Read Cycle
(3,9)
( Vcc=2.3V to 2.7V, T
A
=-25
C to + 85
C)
85
120
Unit Note
Parameter
Symbol
Min
Max
Min
Max
Read Cycle Time
t
RC
85
120
ns
Address Access Time
t
AA
85
120
ns
Chip Enable Access Time
t
ACE
85
120
ns
Output Enable Access Time
t
OE
40
60
ns
Output Hold from address Change
t
OH
10
15
ns
Chip Enable to Output in Low-Z
t
CLZ
10
10
ns
4,5
Chip Disable to Output in High-Z
t
CHZ
35
0
35
ns
4,5
Output Enable to Output in Low-Z
t
OLZ
5
5
ns
4,5
Output Disable to Output in High-Z
t
OHZ
30
0
35
ns
4,5
Power-Up Time
t
PU
0
0
ns
5
Power-Down Time
t
PD
85
120
ns
5
Input Pulse Levels
0.4V to 2.2V
Input Rise and Fall Time
Input and Output Timing
Reference Level
5 ns
1.1V
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