Rev: 2.16 3/2002
1/47
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz
133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
Features
NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAMTM, NoBLTM and
ZBTTM SRAMs
2.5 V or 3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
ZQ mode pin for user-selectable high/low output drive
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip write parity checking; even or odd selectable
On-chip parity encoding and error detection
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 119-, 165-, or 209-Bump BGA package
Functional Description
The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit
Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,
NtRAM, NoBL or other pipelined read/double late write or
flow through read/single late write SRAMs, allow utilization
of all available bus bandwidth by eliminating the need to insert
deselect cycles when the device is switched from read to write
cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by
the user to operate in Pipeline or Flow Through mode.
Operating as a pipelined synchronous device, in addition to the
rising-edge-triggered registers that capture input signals, the
device incorporates a rising edge triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge-triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with
GSI's high performance CMOS technology and is available in
a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &
x36), or 209-bump (x72) BGA package.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
280
330
430
255
300
395
230
270
350
200
230
300
185
215
270
165
190
245
mA
mA
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
275
320
410
250
295
380
230
265
335
195
225
290
180
210
260
165
185
235
mA
mA
mA
Flow
Through
2-1-1-1
t
KQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr (x18)
Curr (x36)
Curr (x72)
175
200
255
165
190
240
160
180
225
150
170
115
145
165
210
135
150
185
mA
mA
mA
2.5 V
Curr (x18)
Curr (x36)
Curr (x72)
175
200
255
165
190
240
160
180
225
150
170
115
145
165
210
135
150
185
mA
mA
mA
Rev: 2.16 3/2002
2/47
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 Pad Out
209-Bump BGA
--
Top View (Package C)
1
2
3
4
5
6
7
8
9
10
11
A
DQG5
DQG1
A13
E2
A14
ADV
A15
E3
A17
DQB1
DQB5
B
DQG6
DQG2
B
C
B
G
NC
W
A16
B
B
B
F
DQB2
DQB6
C
DQG7
DQG3
B
H
B
D
NC
E1
NC
B
E
B
A
DQB3
DQB7
D
DQG8
DQG4
V
SS
NC
NC
G
NC
NC
V
SS
DQB4
DQB8
E
DQG9
DQC9
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQF9
DQB9
F
DQC4
DQC8
V
SS
V
SS
V
SS
ZQ
V
SS
V
SS
V
SS
DQF8
DQF4
G
DQC3
DQC7
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQF7
DQF3
H
DQC2
DQC6
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
DQF6
DQF2
J
DQC1
DQC5
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQF5
DQF1
K
NC
NC
CK
NC
V
SS
MCL
V
SS
NC
NC
NC
NC
L
DQH1
DQH5
V
DDQ
V
DDQ
V
DD
FT
V
DD
V
DDQ
V
DDQ
DQA5
DQA1
M
DQH2
DQH6
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
DQA6
DQA2
N
DQH3
DQH7
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
DQA7
DQA3
P
DQH4
DQH8
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
DQA8
DQA4
R
DQD9
DQH9
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
DQA9
DQE9
T
DQD8
DQD4
V
SS
NC
NC
LBO
PE
NC
V
SS
DQE4
DQE8
U
DQD7
DQD3
NC
A12
NC
A11
NC
A10
NC
DQE3
DQE7
V
DQD6
DQD2
A9
A8
A7
A1
A6
A5
A4
DQE2
DQE6
W
DQD5
DQD1
TMS
TDI
A3
A0
A2
TDO
TCK
DQE1
DQE5
Rev 10
11 x 19 Bump BGA
--
14 x 22 mm
2
Body
--
1 mm Bump Pitch
Rev: 2.16 3/2002
3/47
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 BGA Pin Description
Pin Location
Symbol
Type
Description
W6, V6
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,
U4, A3, A5, A7, B7, A9
An
I
Address Inputs
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
DQ
E1
DQ
E9
DQ
F1
DQ
F9
DQ
G1
DQ
G9
DQ
H1
DQ
H9
I/O
Data Input and Output pins (x36 Version)
C9, B8, B3, C4, C8, B9, B4, C3
B
A
, B
B
, B
C
,B
D,
B
E
, B
F
, B
G
,B
H
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
DQ
F
, DQ
G
, DQ
H
I/Os; active low
B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K9,
K10, K11, T4, T5, T8, U3, U5, U7, U9
NC
--
No Connect
K3
CK
I
Clock Input Signal; active high
B6
W
I
Write Enable. Writes all enabled bytes; active low
C6, A8
E
1,
E
3
I
Chip Enable; active low
A4
E
2
I
Chip Enable; active high
D6
G
I
Output Enable; active low
P6
ZZ
I
Sleep Mode control; active high
L6
FT
I
Flow Through or Pipeline mode; active low
T6
LBO
I
Linear Burst Order mode; active low
G6, J6, N6
MCH
I
Must Connect High
H6, K6, M6
MCL
Must Connect Low
Rev: 2.16 3/2002
4/47
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
T7
PE
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36
Mode)
B6
BW
I
Byte Enable; active low
F6
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
W3
TMS
I
Scan Test Mode Select
W4
TDI
I
Scan Test Data In
W8
TDO
O
Scan Test Data Out
W9
TCK
I
Scan Test Clock
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,
R6, R7
V
DD
I
Core power supply
D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,
P4, P5, P7, P8, P9, T3, T9
V
SS
I
I/O and Core Ground
E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9
V
DDQ
I
Output driver power supply
GS8162Z72 BGA Pin Description
Pin Location
Symbol
Type
Description
Rev: 2.16 3/2002
5/47
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
165 Bump BGA--x18 Commom I/O--Top View (Package D)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
E1
B
B
NC
E3
CKE
ADV
A17
A
A19
A
B
NC
A
E2
NC
B
A
CK
W
G
A18
A
NC
B
C
NC
NC
V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
DQPA
C
D
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
D
E
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
E
F
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
F
G
NC
DQB
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC
DQA
G
H
FT
MCH
NC
V
DD
V
SS
V
SS
V
SS
V
DD
NC
ZQ
ZZ
H
J
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
J
K
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
K
L
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
L
M
DQB
NC
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
DQA
NC
M
N
DQPB
DNU
V
DDQ
V
SS
NC
NC
NC
V
SS
V
DDQ
NC
NC
N
P
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC
P
R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch
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