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Электронный компонент: 820H32A

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Rev: 1.04 3/2000
1/23
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
64K x 32
2M Synchronous Burst SRAM
150Mhz - 66Mhz
9ns - 18ns
3.3V VDD
3.3V & 2.5V I/O
TQFP, QFP
Commercial Temp
Industrial Temp
Features
FT pin for user configurable flow through or pipelined operation.
Single Cycle Deselect (SCD) Operation.
High Output Drive current.
3.3V +10%/-5% Core power supply
2.5V or 3.3V I/O supply.
LBO pin for linear or interleaved burst mode.
Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
Byte write (BW) and/or global write (GW) operation.
Common data inputs and data outputs.
Clock Control, registered, address, data, and control.
Internal Self-Timed Write cycle.
Automatic power-down for portable applications.
JEDEC standard 100-lead TQFP or QFP package.
Functional Description
Applications
The GS820H32A is a 2,097,152 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU's, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/O's, chip enables (E
1
, E
2
, E
3
), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through / Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FP-
BGA). Holding the FT mode pin/bump low, places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
Pipelined Reads
The GS820H32A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS820H32A operates on a 3.3V power supply and all inputs/
outputs are 3.3V and 2.5V compatible. Separate output power (V
DDQ
)
pins are used to de-couple output noise from the internal circuit.
-150
-138
-133
-117
-100
-66
Pipeline
3-1-1-1
tCycle
t
KQ
I
DD
6.6ns
3.8ns
270mA
7.25ns
4ns
245mA
7.5ns
4ns
240mA
8.5ns
4.5
210mA
10ns
5ns
180mA
12.5ns
6ns
150mA
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
10.5ns
9ns
170mA
15ns
9.7ns
120mA
15ns
10ns
120mA
15ns
11ns
120mA
15ns
12ns
120mA
20ns
18ns
95mA
Rev: 1.04 3/2000
2/23
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A 100 Pin TQFP and QFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
N
C
N
C
V
S
S
V
D
D
N
C

N
C

A
1
0

A
1
1

A
1
2

A
1
3

A
1
4
N
C
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
G
W
B
W
V
D
D
V
S
S
G
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9

A
1
5
64K x 32
Top View
DQ
B5
NC
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
NC
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
NC
DQ
C5
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.04 3/2000
3/23
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
TQFP Pin Description
H
Pin Location
Symbol
Type
Description
37, 36
A
0
, A
1
I
Address field LSB's and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
A
2
-
15
I
Address Inputs
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
DQ
A1
-DQ
A8
DQ
B1
-DQ
B8
DQ
C1
-DQ
C8
DQ
D1
-DQ
D8
I/O
Data Input and Output pins.
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
NC
No Connect
87
BW
I
Byte Write. Writes all enabled bytes. Active Low.
93, 94
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/O's. Active Low.
95, 96
B
C
, B
D
I
Byte Write Enable for DQ
C
, DQ
D
Data I/O's. Active Low.
89
CK
I
Clock Input Signal. Active High.
88
GW
I
Global Write Enable. Writes all bytes. Active Low.
98, 92
E
1
, E
3
I
Chip Enable. Active Low.
97
E
2
I
Chip Enable. Active High.
86
G
I
Output Enable. Active Low.
83
ADV
I
Burst address counter advance enable. Active Low.
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller). Active Low.
64
ZZ
I
Sleep Mode control. Active High.
14
FT
I
Flow Through or Pipeline mode. Active Low.
31
LBO
I
Linear Burst Order mode. Active Low.
15, 41, 65, 91
V
DD
I
Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
V
SS
I
I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
I
Output driver power supply.
Rev: 1.04 3/2000
4/23
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
GS820H32A Block Diagram
A1
A0
A0
A1
D0
D1
Q1
Q0
Counter
Load
D
Q
D
Q
Register
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
Register
D
Q
R
e
g
i
s
t
e
r
D
Q
R
e
g
i
s
t
e
r
A0-An
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
B
B
B
C
B
D
E
1
FT
G
ZZ
Power Down
Control
Memory
Array
32
32
4
A
Q
D
E
2
E
3
DQx1-DQx8
Rev: 1.04 3/2000
5/23
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
E
GS820H32AT/Q-150/138/133/117/100/66
Note:
There are pull up devices on LBO and FT pins and a pull down device on and ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Byte Write Truth Table
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O's remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, I
DD
= I
SB
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte
A
H
L
L
H
H
H
2, 3
Write byte
B
H
L
H
L
H
H
2, 3
Write byte
C
H
L
H
H
L
H
2, 3, 4
Write byte
D
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00