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Электронный компонент: 841Z18A

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Rev: 1.00 10/2001
1/30
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS841Z18/36AT-200/180/166/150/100
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
200 MHz100 MHz
3.3 V V
DD
2.5 V and 3.3 V V
DDQ
100-Pin TQFP
Commercial Temp
Industrial Temp
Product Preview
Features
256K x 18 and 128K x 36 configurations
User-configurable Pipelined and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
Fully pin-compatible with both pipelined and flow through
NtRAMTM, NoBLTM and ZBTTM SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
3.3 V +10%/5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleave Burst mode
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
Clock Control, registered, address, data, and control
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
Functional Description
The GS841Z18/36AT is an 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS841Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS841Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
200
180
166
150
100
Pipeline
3-1-1-1
tCycle
t
KQ
I
DD
5.0 ns
3.0 ns
205 mA
5.5 ns
3.2 ns
185 mA
6.0 ns
3.5 ns
170 mA
6.6 ns
3.8 ns
155 mA
10 ns
4.5 ns
105 mA
Flow
Through
2-1-1-1
t
KQ
tCycle
I
DD
7.5 ns
8.8 ns
115 mA
8 ns
9.1 ns
115 mA
8.5 ns
10 ns
105 mA
10 ns
12 ns
100 mA
12 ns
15 ns
80 mA
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 1.00 10/2001
2/30
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS841Z18/36AT-200/180/166/150/100
Product Preview
GS841Z18AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
V
SS
V
DDQ
V
DDQ
V
SS
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
T
M
S
T
D
I
V
S
S
V
D
D
T
D
O
T
C
K

A
1
0

A
1
1

A
1
2

A
1
3

A
1
4

A
1
6
A
6
A
7
E
1
E
2
N
C
N
C
B
B
B
A
E
3
C
K
W
C
K
E
V
D
D
V
S
S
G
A
D
V
N
C
N
C
A
8
A
9

A
1
5
256K x 18
Top View
DQ
A9
A
17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 10/2001
3/30
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS841Z18/36AT-200/180/166/150/100
Product Preview
GS841Z36AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
DDQ
V
SS
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
V
SS
V
DDQ
V
DDQ
V
SS
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
V
SS
V
DDQ
L
B
O
A
5
A
4
A
3
A
2
A
1
A
0
T
M
S
T
D
I
V
S
S
V
D
D
T
D
O
T
C
K

A
1
0

A
1
1

A
1
2

A
1
3

A
1
4

A
1
6
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
C
K
W
C
K
E
V
D
D
V
S
S
G
A
D
V
N
C
N
C
A
8
A
9

A
1
5
128K x 36
Top View
DQ
B5
DQ
B9
DQ
B7
DQ
B8
DQ
B6
DQ
A6
DQ
A5
DQ
A8
DQ
A7
DQ
A9
DQ
C7
DQ
C8
DQ
C6
DQ
D6
DQ
D8
DQ
D7
DQ
D9
DQ
C5
DQ
C9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.00 10/2001
4/30
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS841Z18/36AT-200/180/166/150/100
Product Preview
100-Pin TQFP Pin Descriptions
Pin Location
Symbol
Typ
e
Description
37, 36
A
0
, A
1
In
Burst Address Inputs--Preload the burst counter
35, 34, 33, 32, 100, 99, 82, 81,
50, 49, 48, 47, 46, 45, 44
A
2
A
16
In
Address Inputs
80
A
17
In
Address Input (x18 Version Only)
89
CK
In
Clock Input Signal
93
B
A
In
Byte Write signal for data inputs DQ
A1
DQ
A9
; active low
94
B
B
In
Byte Write signal for data inputs DQ
B1
DQ
B9
; active low
95
B
C
In
Byte Write signal for data inputs DQ
C1
DQ
C9
; active low (x36 Version Only)
96
B
D
In
Byte Write signal for data inputs DQ
D1
DQ
D9
; active low (x36 Version Only)
88
W
In
Write Enable; active low
98
E
1
In
Chip Enable; active low
97
E
2
In
Chip Enable; active low; for self decoded depth expansion
92
E
3
In
Chip Enable; active low; for self decoded depth expansion
86
G
In
Output Enable; active low
85
ADV
In
Advance / Load--Burst address counter control pin
87
CKE
In
Clock Input Buffer Enable; active low
58, 59, 62,63, 68, 69, 72, 73, 74 DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins (x18 Version Only)
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins (x18 Version Only)
51, 52, 53, 56, 57, 75, 78, 79,
1, 2, 3, 6, 7, 25, 28, 29, 30
NC
--
No Connect (x18 Version Only)
51, 52, 53, 56, 57, 58, 59, 62,63 DQ
A1
DQ
A9
I/O
Byte A Data Input and Output pins (x36 Versions Only)
68, 69, 72, 73, 74, 75, 78, 79, 80 DQ
B1
DQ
B9
I/O
Byte B Data Input and Output pins (x36 Versions Only)
1, 2, 3, 6, 7, 8, 9, 12, 13
DQ
C1
DQ
C9
I/O
Byte C Data Input and Output pins (x36 Versions Only)
18, 19, 22, 23, 24, 25, 28, 29, 30 DQ
D1
DQ
D9
I/O
Byte D Data Input and Output pins (x36 Versions Only)
64
ZZ
In
Power down control; active high
14
FT
In
Pipeline/Flow Through Mode Control; active low
31
LBO
In
Linear Burst Order; active low
38
TMS
--
Scan Test Mode Select
39
TDI
--
Scan Test Data In
42
TDO
--
Scan Test Data Out
43
TCK
--
Scan Test Clock
15, 41, 65, 91
V
DD
In
3.3 V power supply
5,10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
V
SS
In
Ground
4, 11, 20, 27, 54, 61, 70, 77
V
DDQ
In
3.3 V output power supply for noise reduction
42, 43,, 84, 16, 66
NC
--
No Connect
Rev: 1.00 10/2001
5/30
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GS841Z18/36AT-200/180/166/150/100
Product Preview
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A Write
Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte "a"
L
L
H
H
H
Write Byte "b"
L
H
L
H
H
Write Byte "c"
L
H
H
L
H
Write Byte "d"
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H