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Электронный компонент: 842Z18A

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Rev: 1.01 3/2002
1/33
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS842Z18/36AB-200/180/166/150/100
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
200 MHz100 MHz
3.3 V V
DD
2.5 V and 3.3 V V
DDQ
119-Bump BGA
Commercial Temp
Industrial Temp
Features
256K x 18 and 128K x 36 configurations
User configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin compatible with both pipelined and flow through
NtRAMTM, NoBLTM and ZBTTM SRAMs
Pin-compatible with 2M, 8M, and 16M devices
3.3 V +10%/10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleave Burst mode
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
Clock Control, registered address, data, and control
ZZ Pin for automatic power-down
JEDEC-standard 119-bump BGA package
Functional Description
The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS842Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS842Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump BGA package.
200
180
166
150
100
Pipeline
3-1-1-1
tCycle
t
KQ
I
DD
5.0 ns
3.0 ns
370 mA
5.5 ns
3.2 ns
335 mA
6.0 ns
3.5 ns
310 mA
6.6 ns
3.8 ns
280 mA
10 ns
4.5 ns
190 mA
Flow
Through
2-1-1-1
t
KQ
tCycle
I
DD
7.5 ns
8.8 ns
220 mA
8 ns
9.1 ns
210 mA
8.5 ns
10 ns
190 mA
10 ns
12 ns
165 mA
12 ns
15 ns
135 mA
A
B
C
D
E
F
R
W
R
W
R
W
Q
A
D
B
Q
C
D
D
Q
E
Q
A
D
B
Q
C
D
D
Q
E
Clock
Address
Read/Write
Flow Through
Data I/O
Pipelined
Data I/O
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Rev: 1.01 3/2002
2/33
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18A Pad Out
119 Bump BGA
--
Top View
1
2
3
4
5
6
7
A
V
DDQ
A
6
A
7
NC
A
8
A
9
V
DDQ
B
NC
E
2
A
4
ADV
A
15
E
3
NC
C
NC
A
5
A
3
V
DD
A
14
A
16
NC
D
DQ
B1
NC
V
SS
ZQ
V
SS
DQ
A9
NC
E
NC
DQ
B2
V
SS
E
1
V
SS
NC
DQ
A8
F
V
DDQ
NC
V
SS
G
V
SS
DQ
A7
V
DDQ
G
NC
DQ
B3
B
B
NC
NC
NC
DQ
A6
H
DQ
B4
N
C
V
SS
W
V
SS
DQ
A5
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQ
B5
V
SS
CK
V
SS
NC
DQ
A4
L
DQ
B6
NC
NC
NC
B
A
DQ
A3
NC
M
V
DDQ
DQ
B7
V
SS
CKE
V
SS
NC
V
DDQ
N
DQ
B8
NC
V
SS
A
1
V
SS
DQ
A2
NC
P
NC
DQ
B9
V
SS
A
0
V
SS
NC
DQ
A1
R
NC
A
2
LBO
V
DD
FT
A
13
NC
T
NC
A
10
A
11
NC
A
12
A
17
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
Rev: 1.01 3/2002
3/33
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z36A Pad Out
119 Bump BGA
--
Top View
1
2
3
4
5
6
7
A
V
DDQ
A
6
A
7
NC
A
8
A
9
V
DDQ
B
NC
E
2
A
4
ADV
A
15
E
3
NC
C
NC
A
5
A
3
V
DD
A
14
A
16
NC
D
DQ
C4
DQ
C9
V
SS
ZQ
V
SS
DQ
B9
DQ
B4
E
DQ
C3
DQ
C8
V
SS
E
1
V
SS
DQ
B8
DQ
B3
F
V
DDQ
DQ
C7
V
SS
G
V
SS
DQ
B7
V
DDQ
G
DQ
C2
DQ
C6
B
C
NC
B
B
DQ
B6
DQ
B2
H
DQ
C1
DQ
C5
V
SS
W
V
SS
DQ
B5
DQ
B1
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
DQ
D1
DQ
D5
V
SS
CK
V
SS
DQ
A5
DQ
A1
L
DQ
D2
DQ
D6
B
D
NC
B
A
DQ
A6
DQ
A2
M
V
DDQ
DQ
D7
V
SS
CKE
V
SS
DQ
A7
V
DDQ
N
DQ
D3
DQ
D8
V
SS
A
1
V
SS
DQ
A8
DQ
A3
P
DQ
D4
DQ
D9
V
SS
A
0
V
SS
DQ
A9
DQ
A4
R
NC
A
2
LBO
V
DD
FT
A
13
NC
T
NC
NC
A
10
A
11
A
12
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
Rev: 1.01 3/2002
4/33
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
GS842Z18/36A Pin Description
Pin Location
Symbol
Type
Description
P4, N4
A
0
, A
1
I
Address field LSBs and Address Counter Preset Inputs
A2, A3, A5, A6, B3, B5, C2, C3, C5,
C6, R2, R6, T3, T5
An
I
Address Inputs
T4
An
I
Address Inputs (x36 Version)
A4, T2, T6
NC
--
No Connect (x36 Version)
T2, T6
An
I
Address Inputs (x18 Version)
K7, L7, N7, P7, K6, L6, M6, N6, P6
H7, G7, E7, D7, H6, G6, F6, E6, D6
H1, G1, E1, D1, H2, G2, F2, E2, D2
K1, L1, N1, P1, K2, L2, M2, N2, P2
DQ
A1
DQ
A9
DQ
B
1
DQ
B
9
DQ
C1
DQ
C
9
DQ
D
1
DQ
D
9
I/O
Data Input and Output pins (x36 Version)
L5, G5, G3, L3
B
A
, B
B
, B
C
, B
D
I
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
A
I/Os; active low ( x36 Version)
P7, N6, L6, K7, H6, G7, F6, E7, D6
D1, E2, G2, H1, K2, L1, M2, N1, P2
DQ
A1
DQ
A9
DQ
B
1
DQ
B
9
I/O
Data Input and Output pin (x18 Version)
L5, G3
B
A
, B
B
I
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low ( x18 Version)
P6, N7, M6, L7, K6, H7, G6, E6, D7,
D2, E1, F2, G1, H2, K1, L2, N2, P1,
G5, L3, T4, A4
NC
--
No Connect (x18 Version)
K4
CK
I
Clock Input Signal; active high
M4
CKE
I
Clock Input Buffer Enable; active low
H4
W
I
Write Enable. Writes all enabled bytes; active low
E4, B6
E
1
, E
3
I
Chip Enable; active low
B2
E
2
I
Chip Enable; active high
F4
G
I
Output Enable; active low
B4
ADV
I
Burst address counter advance enable; active high
T7
ZZ
I
Sleep Mode control; active high
R5
FT
I
Flow Through or Pipeline mode; active low
R3
LBO
I
Linear Burst Order mode; active low
D4
ZQ
I
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
B1, C1, R1, T1, L4, B7, C7, U6, J3,
J5, G4, R7
NC
--
No Connect
U2
TMS
I
Scan Test Mode Select
Rev: 1.01 3/2002
5/33
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Preliminary
GS842Z18/36AB-200/180/166/150/100
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E
1
, E
2,
and E
3
). Deassertion of any one of the Enable
inputs will deactivate the device.

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (B
A
, B
B
, B
C,
and B
D
) determine which bytes will be written. All or none may be activated. A write cycle
U3
TDI
I
Scan Test Data In
U5
TDO
O
Scan Test Data Out
U4
TCK
I
Scan Test Clock
J2, C4, J4, R4, J6
V
DD
I
Core power supply
D3, E3, F3, H3, K3, M3, N3, P3, D5,
E5, F5, H5, K5, M5, N5, P5
V
SS
I
I/O and Core Ground
A1, F1, J1, M1, U1, A7, F7,
J7, M7, U7
V
DDQ
I
Output driver power supply
K4
CK
I
Clock Input Signal; active high
Function
W
B
A
B
B
B
C
B
D
Read
H
X
X
X
X
Write Byte "a"
L
L
H
H
H
Write Byte "b"
L
H
L
H
H
Write Byte "c"
L
H
H
L
H
Write Byte "d"
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort/NOP
L
H
H
H
H
GS842Z18/36A Pin Description
Pin Location
Symbol
Type
Description