Rev: 1.10 10/2002
1/12
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS70328SJ/TS
32K x 8
256Kb Asynchronous SRAM
7, 8, 10, 12, 15 ns
3.3 V V
DD
Corner V
DD
and V
SS
SOJ, TSOP
Commercial Temp
Industrial Temp
Features
Fast access time: 7, 8, 10, 12, 15 ns
75/65/50/50/50 mA at max cycle rate
Single 3.3 V 0.3 V power supply
All inputs and outputs are TTL-compatible
Fully static operation
Industrial Temperature Option: 40 to 85C
Package line up
SJ: 300 mil, 28-pin SOJ package
TS: 8 mm x 13.4 mm, 28-pin TSOP Type I package
Description
The GS70328 is a high speed CMOS static RAM organized as
32,763 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS70328 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS70328 is available in 300 mil, 28-pin SOJ
and 8 x 13.4 mm
2
, 28-pin TSOP Type-I packages.
Pin Descriptions
Symbol
Description
A
0
A
14
Address input
DQ
1
DQ
8
Data input/output
CE
Chip enable input
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC
No connect
Top view
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
V
SS
V
DD
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
28-pin
300 mil
5
6
7
8
9
10
11
12
13
14
28- pin
8 x 13.4 TSOP I
1
2
OE
A
11
SOJ
3
4
A
9
A
8
A
13
WE
V
DD
A
14
A
12
A
7
A
6
A
5
A
4
A
3
24
23
22
21
20
19
18
17
16
15
28
27
A
10
CE
26
25
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
V
SS
DQ
3
DQ
2
DQ
1
A
0
A
1
A
2
Pin Configuration
Rev: 1.10 10/2002
2/12
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS70328SJ/TS
Note: X: "H" or "L"
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Truth Table
CE
OE
WE
DQ
1
to DQ
8
V
DD
Current
H
X
X
Not Selected
ISB
1
, ISB
2
L
L
H
Read
I
DD
L
X
L
Write
L
H
H
High Z
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
V
DD
0.5 to +4.6
V
Input Voltage
V
IN
0.5 to V
DD
+ 0.5
(
4.6 V max.)
V
Output Voltage
V
OUT
0.5 to V
DD
+ 0.5
(
4.6 V max.)
V
Allowable power dissipation
PD
0.7
W
Storage temperature
T
STG
55 to 150
o
C
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
14
Block Diagram
DQ
8
Rev: 1.10 10/2002
3/12
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS70328SJ/TS
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns.
Notes:
1. Tested at T
A
= 25C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Supply Voltage for -7/8/10/12
V
DD
3.0
3.3
3.6
V
Input High Voltage
V
IH
2.0
--
V
DD
+ 0.3
V
Input Low Voltage
V
IL
0.3
--
0.8
V
Ambient Temperature,
Commercial Range
T
Ac
0
--
70
o
C
Ambient Temperature,
Industrial Range
T
A
I
40
--
85
o
C
Capacitance
Parameter
Symbol
Test Condition
Maximum
Unit
Input Capacitance
C
IN
V
IN
= 0 V
5
pF
Output Capacitance
C
OUT
V
OUT
= 0 V
7
pF
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
I
IL
V
IN
= 0 to V
DD
1uA
1uA
Output Leakage Current
I
LO
Output High Z
V
OUT
= 0 to V
DD
1uA
1uA
Output High Voltage
V
OH
I
OH
= 4 mA
2.4 V
--
Output Low Voltage
V
OL
I
LO
= +4 mA
--
0.4 V
Rev: 1.10 10/2002
4/12
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS70328SJ/TS
Power Supply Currents
AC Test Conditions
Parameter Symbol
Test Conditions
0 to 70C
-40 to 85C
7 ns
8 ns 10 ns 12 ns 15 ns 7 ns
8 ns 10 ns 12 ns 15 ns
Operating
Supply
Current
IDD
CE
VIL
All other inputs
VIH or
VIL
Min. cycle time
IOUT = 0 mA
75 mA 65 mA 50 mA 50 mA 50 mA 80 mA 70 mA 55 mA 55 mA 55 mA
Standby
Current
ISB1
CE
VIH
All other inputs
VIH or
VIL
Min. cycle time
35 mA 30 mA 25 mA 25 mA 25 mA 40 mA 35 mA 30 mA 30 mA 30 mA
Standby
Current
ISB2
CE
V
DD
0.2 V
All other inputs
V
DD
0.2 V or
0.2 V
1 mA
2 mA
DQ
VT = 1.4 V
50
30pF
1
DQ
3.3 V
Output Load 1
Output Load 2
589
434
5pF
1
Notes:
1. Include scope and jig capacitance
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted
3. Output load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
Parameter
Conditions
Input high level
V
IH
= 2.4 V
Input low level
V
IL
= 0.4 V
Input rise time
tr = 1 V/ns
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output reference level
1.4 V
Output load
Fig. 1& 2
Rev: 1.10 10/2002
5/12
1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS70328SJ/TS
AC Characteristics
* These parameters are sampled and are not 100% tested
Read Cycle
Parameter
Symbol
-7
-8
-10
-12
-15
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
t
RC
7
--
8
--
10
--
12
--
15
--
ns
Address access time
t
AA
--
7
--
8
--
10
--
12
--
15
ns
Chip enable access time (CE)
t
AC
--
7
--
8
--
10
--
12
--
15
ns
Output enable to output valid (OE)
t
OE
--
3.5
--
4
--
5
--
6
--
7
ns
Output hold from address change
t
OH
2
--
2
--
2
--
3
--
3
--
ns
Chip enable to output in low Z (CE)
t
LZ
*
2
--
2
--
2
--
3
--
3
--
ns
Output enable to output in low Z (OE)
t
OLZ
*
0
--
0
--
0
--
0
--
0
--
ns
Chip disable to output in High Z (CE)
t
HZ
*
--
3.5
--
4
--
5
--
6
--
7
ns
Output disable to output in High Z (OE)
t
OHZ
*
--
3
--
3.5
--
4
--
5
--
6
ns
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