HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 1 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

GENERAL DESCRIPTION

The HDD64M72D18RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory

module. The module consists of eighteen CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages
and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM. The HDD64M72D18RPW is a DIMM( Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.

FEATURES

Part Identification

HDD64M72D18RPW

10A : 100MHz (CL=2)

HDD64M72D18RPW

13A : 133MHz (CL=2)

HDD64M72D18RPW

13B : 133MHz (CL=2.5)

512MB(64Mx72) Registered DDR DIMM based on 32Mx8 DDR SDRAM

2.5V

0.2V VDD and VDDQ power supply

Auto & self refresh capability (8K Cycles / 64ms)

All input and output are compatible with SSTL_2 interface

Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

MRS cycle with address key programs

- Latency (Access from column address) : 2, 2.5

- Burst length : 2, 4, 8

- Data scramble : Sequential & Interleave

Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock

All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock

The used device is 8M x 8bit x 4Banks DDR SDRAM

DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K
Ref., 184Pin-DIMM with PLL & Register Part No. HDD64M72D18RPW

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 2 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

PIN ASSIGNMENT

These pins should be NC in the system which does not support SPD

PIN

PIN DESCRIPTION

PIN

PIN DESCRIPTION

A0~A12

Address input

VDD

Power supply(2.5V)

BA0~BA1

Bank Select Address

VDDQ

Power supply for DQs(2.5V)

DQ0~DQ63

Data input/output

VREF

Power supply for reference

CB0~CB7

Check Bit

VDDSPD

Serial EEPROM Power supply(3.3)

DQS0~DQS8

Data Strobe input/output

VSS

Ground

DM0~DM8

Data-in Mask

SA0~SA2

Address in EEPROM

CK0~/CK0

Clock input

SDA

Serial data I/O

CKE0~CKE1

Clock enable input

SCL

Serial clock

/CS0~/CS1

Chip Select input

VDDID

VDD identification flag

/RAS

Row Address strobe

No connection

/CAS

Column Address strobe

PIN

Front

PIN

Back

PIN

Frontl

PIN

Back

PIN

Front

PIN

Back

VREF

DDQ

124

154

/RAS

DQ0

DQ24

/WE

DQ4

125

155

DQ45

DQ41

DQ5

126

DQ28

156

DDQ

DQ1

DQ25

/CAS

DDQ

127

DQ29

157

/CS0

DQS0

DQS3

DM0

128

DDQ

158

/CS1

DQ2

DQS5

DQ6

129

DM3

159

DM5

DQ42

DQ7

130

160

DQ3

DQ26

DQ43

100

131

DQ30

161

DQ46

DQ27

101

132

162

DQ47

/RESET

* /CS2

102

133

DQ31

163

* /CS3

DQ48

103

*A13

134

CB4

164

DDQ

DQ8

DQ49

104

DDQ

135

CB5

165

DQ52

DQ9

CB0

105

DQ12

136

DDQ

166

DQ53

DQS1

CB1

* CK2

106

DQ13

137

CK0

167

DDQ

* /CK2

107

DM1

138

/CK0

168

* CK1

DQS8

DDQ

108

139

169

DM6

* /CK1

DQS6

109

DQ14

140

DM8

170

DQ54

CB2

DQ50

110

DQ15

141

A10

171

DQ55

DQ10

DQ51

111

CKE1

142

CB6

172

DDQ

DQ11

CB3

112

DDQ

143

DDQ

173

CKE0

BA1

VDDID

113

* BA2

144

CB7

174

DQ60

DDQ

KEY

DQ56

114

DQ20

KEY

175

DQ61

DQ16

DQ32

DQ57

115

A12

145

176

DQ17

DDQ

116

146

DQ36

177

DM7

DQS2

DQ33

DQS7

117

DQ21

147

DQ37

178

DQ62

DQS4

DQ58

118

A11

148

179

DQ63

DQ34

DQ59

119

DM2

149

DM4

180

DDQ

DQ18

120

150

DQ38

181

SA0

BA0

121

DQ22

151

DQ39

182

SA1

DDQ

DQ35

SDA

122

152

183

SA2

DQ19

DQ40

SCL

123

DQ23

153

DQ44

184

VDDSPD

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 4 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CK, /CK

Clock

CK and CK are differential clock inputs. All address and control input signals are

sam-pled on the positive edge of CK and negative edge of CK. Output (read) data

is referenced to both edges of CK. Internal clock signals are derived from CK/CK.

CKE

Clock Enable

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device

input buffers and output drivers. Deactivating the clock provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE

POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions

except for disabling outputs, which is achieved asynchronously. Input buffers,

excluding CK, CK and CKE are disabled during power-down and self refresh

modes, providing low standby power. CKE will recognizean LVCMOS LOW level

prior to VREF being stable on power-up.

/CS

Chip Select

CS enables(registered LOW) and disables(registered HIGH) the command

decoder.

All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the

command code.

A0 ~ A12

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9

BA0 ~ BA1 Bank select address

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE

command is being applied.

/RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

/CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

/WE

Write enable

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

DQS0~8

Data Strobe

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DM0~8

Input Data Mask

DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. DM pins include dummy loading internally, to matches the

DQ and DQS load-ing.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

CB0~CB7

Check Bit

Check Bit Input/Output pins

VDDQ

Supply

DQ Power Supply : +2.5V

0.2V.

VDD

Supply

Power Supply : +2.5V

0.2V (device specific).

VSS

Supply

DQ Ground.

VREF

Supply

SSTL_2 reference voltage.

VDDSPD

Supply

Serial EEPROM Power Supply : 3.3v

VDDID

VDD identification Flag

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

UNTE

Voltage on any pin relative to Vss

, V

OUT

-0.5 ~ 3.6

Voltage on V

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

DDQ

supply relative to Vss

DDQ

-0.5 ~ 3.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Notes: Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS

(Recommended operating conditions (Voltage referenced to Vss = 0V, T

= 0 to 70

C) )

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTE

Supply Voltage

2.3

2.7

I/O Supply Voltage

DDQ

2.3

2.7

I/O Reference Voltage

REF

DDQ

/2 - 50mA

DDQ

/2 +

50mA

I/O Termination Voltage(system)

REF

0.04

REF

+ 0.04

Input High Voltage

(DC)

REF

+ 0.15

REF

+ 0.3

Input Low Voltage

(DC)

-0.3

REF

- 0.15

Input Voltage Level, CK and /CK inputs

(DC)

-0.3

DDQ

+ 0.3

Input Differential Voltage, CK and /CK inputs

(DC)

0.3

DDQ

+ 0.6

Input crossing point Voltage, CK and /CK

inputs

(DC)

1.15

1.35

Input leakage current

-2

Output leakage current

-5

Output High current (V

OUT

= 1.95V)

-16.8

Output Low current (V

OUT

= 0.35V)

16.8

Notes :

1. Includes

25mV margin for DC offset on V

REF

, and a combined total of

50mV margin for all AC noise and DC

offset on V

REF

, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V

REF

and

internal DRAM noise coupled to V

REF

, both of which may result in V

REF

noise. V

REF

should be de-coupled with an

inductance of

3nH.

2. V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set

equal to V

REF

, and must track variations in the DC level of V

REF

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the

pad in simulation. The AC and DC input specifications are relative to a V

REF

envelop that has been bandwidth limited

to 200MHZ.

5. The value of V

is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of

the same.

6. These charactericteristics obey the SSTL-2 class II standards.

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 6 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

CAPACITANCE

= min to max, V

DDQ

= 2.5V

to 2.7V, T

= 25

C, f = 100MHz)

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)

IN1

Input capacitance(CKE0,CKE1)

IN2

Input capacitance(/CS0,/CS1)

IN3

Input capacitance(CK0~/CK1)

IN4

Input capacitance(DM0~DM8)

IN5

Data & DQS input/output capacitance (DQ0 ~ DQ63,

DQS0~DQS8)

OUT1

Data input/output capacitance (CB0~CB7))

OUT2

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, V

= 2.5V, T =25

version

pARAMETER

Symbo

TEST

Condition

-10A

-13A

-13B

Unit

Operating current
(One bank

active-Precharge)

DD0

(min), t

CK=100MHz

for DDR200,133MHz for

DDR266A & DDR266B

DQ,DM and DQS inputs changing twice per clock
cycle Address and control inputs changing once per
clock cycle

1515

1695

Operating current
(One bankOperation)

DD1

One bank open, BL=4,Reads-Refer to the following
page for detailed test condition

1605

1875

Precharge

power-

down

standby current

DD2P

All banks idle, power-down mode
CKE

(max), t

CK=100MHz

for DDR200,133MHz for

DDR266A & DDR266B V

= V

REF

for DQ,DQS and

885

1020

Precharge Floating

standby current

DD2F

/CS

(min), All banks idle

CKE

(min), t

CK=100MHz

for DDR200,133MHz for

DDR266A & DDR266B

Address and control inputs changing once per clock
cycle V

= V

REF

for DQ,DQS and DM

1020

1155

Precharge Quiet
Standby current

DD2Q

/CS

(min), All banks idle

CKE

(min), t

CK=100MHz

for DDR200,133MHz for

DDR266A & DDR266B Address and other control
inputs stable with keeping

(min) or

(max)

= V

REF

for DQ,DQS and DM

975

1110

Active power-down
Mode standby current

DD3P

One bank active; power-down mode;
CKE

(max), t

CK=100MHz

for DDR200,133MHz for

DDR266A & DDR266B V

= V

REF

for DQ,DQS and

DM.

1020

1155

Active standby

current

DD3N

CS# >= VIH(min), CKE>=VIH(min)
one bank active, active

precharge, tRC=tRASmax

tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B, DQ, DQS and DM inputs changing

twice per clock cycle Address and other control
inputs changing once per clock cycle

1110

1290

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

Operating current

(burst read)

DD4R

BL = 2, reads, continuous burst
One bank open, Address and control inputs
changing once per clock cycle, I

OUT

= 0mA

2055

2415

Operating current
(Bust write)

DD4W

BL = 2, write, continuous burst
One bank open, Address and control inputs
changing once per clock cycle

2415

2955

Auto refresh current

DD5

tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz,
distributed refresh

2055

2415

Normal

354

Self
refresh
current

Low Power

DD6

CKE =< 0.2V, External clock should be on
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B

327

Operating current
(Four bank operation)

DD7A

Four bank interleaving with BL=4
-Refer to the following page for detailed test
condition

3315

3945

Notes: Operation at above absolute maximum rating can adversely affect device reliability

AC OPERATING CONDITIONS

PARAMETER

STMBOL

MIN

MAX

UNIT

NOTE

Input High (Logic 1) Voltage, DQ, DQS and DM signals

(AC)

VREF + 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

(AC)

VREF - 0.31

Input Differential Voltage, CK and CK inputs

(AC)

0.7

VDDQ+0.6

Input Crossing Point Voltage, CK and CK inputs

(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Notes:

1. VID is the magnitude of the difference between the input level on CK and the input on CK.

The value of V

is expected to equal 0.5* V

DDQ

of the transmitting device and must track variations in the DC level

of the same

These parameters should be tested at the pim on actual components and may be checked at either the pin or the
pad in
simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited
20MHz.

AC OPERATING TEST CONDITIONS

PARAMETER

VALUE

UNIT

NOTE

Input reference voltage for Clock

0.5 * V

DDQ

Input signal maximum peak swing

1.5

Input signal minimum slew rate

1.0

Input Levels(V

)

REF

+0.35/V

REF

Input timing measurement reference level

REF

Output timing measurement reference level

Output load condition

See Load Circuit

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 8 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

AC CHARACTERISTICS

(These AC charicteristics were tested on the Component)

DDR200

DDR266A

DDR266B

-10A

-13A

-13B

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNIT NOTE

Row cycle time

Refresh row cycle time

RFC

1,2

Row active time

RAS

120K

1,2

/RAS to /CAS delay

RCD

Row precharge time

Row active to Row active delay

RRD

Write recovery time

Last data in to Read command

CDLR

Col. address to Col. address delay

CCD

CL=2.0

7.5

Clock cycle time

CL=2.5

7.5

Clock high level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock low level width

0.45

0.55

0.45

0.55

0.45

0.55

DQS-out access time from CK/CK

DQSCK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

Output data access time from CK/CK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

Data strobe edge to ouput data edge

DQSQ

+0.6

+0.5

Read Preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

Read Postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 9 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

Data out high impedence time from

CK-/CK

HZQ

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

CK to valid DQS-in

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS-in setup time

WPRES

DQS-in hold time

WPREH

0.25

DQS-in falling edge to CK rising-setup

time

DSS

0.2

DQS-in falling edge to CK rising hold

time

DSH

0.2

DQS-in high level width

DQSH

0.35

DQS-in low level width

DQSL

0.35

DQS-in cycle time

DSC

0.9

1.1

0.9

1.1

0.9

1.1

Address and Control Input setup time

1.1

0.9

Address and Control Input hold time

1.1

0.9

Mode register set cycle time

MRD

DQ & DM setup time to DQS

0.6

0.5

DQ & DM hold time to DQS

0.6

0.5

DQ & DM input pulse width

DIPW

1.75

Power down exit time

PDEX

Exit self refresh to write command

XSW

116

Exit self refresh to bank active

command

XSA

Exit self refresh to read command

XSR

200

Cycle

Refresh interval time

REF

7.8

Output DQS valid window

0.35

DQS write postamble time

WPST

0.25

Notes :

1. Maximum burst refresh of 8.
2. t

HZQ

transitions occurs in the same assess time windows as valid data transitions. These parameters are not

referenced to a specific voltage level, but specify when the device output is no longer driving.

3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going

from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on t

DQSS.

4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

HANBit HDD64M72D18RPW

URL : www.hbe.co.kr 10 HANBit Electronics Co.,Ltd.
REV 1.0 (August.2002)

SIMPLIFIED TRUTH TABLE

COMMAND

n-1

/CS

/WE DM

0,1

A10/

A11,A12

A9~A0

NOTE

Extended MRS

OP code

1,2

Mode register set

OP code

1,2

Auto refresh

Entry

Refresh

Self
refresh Exit

Bank active & row addr.

Row address

Auto

precharge

disable

Read &
column
address

Auto precharge eable

Column

Address

(A0 ~A9)

Auto precharge
disable

Write &
column
address

Auto precharge
enable

Column

Address

(A0 ~ A9)

4,6

Burst Stop

Bank selection

Precharg
e

All banks

Entry

Clock suspend or
active power down

Exit

Entry

Precharge power
down mode

Exit

No operation command

(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :

1. OP Code : Operand code

A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t

after the end of burst.

6. Burst stop command is valid at every burst length.
7. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges

(Write DM latency is 0)

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