1
Semiconductor
Features
Fully Static Operation
Buffered Inputs
Common Reset
Negative-Edge Clocking
Typical f
MAX
= 60 MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
PKG.
NO.
CD74HC393E
-55 to 125
14 Ld PDIP
E14.3
CD74HCT393E
-55 to 125
14 Ld PDIP
E14.3
CD74HC393M
-55 to 125
14 Ld SOIC
M14.15
CD74HCT393M
-55 to 125
14 Ld SOIC
M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
1CP
1MR
1Q0
1Q1
1Q2
1Q3
GND
V
CC
2CP
2MR
2Q0
2Q1
2Q2
2Q3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
September 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1997
File Number
1653.1
CD74HC393,
CD74HCT393
High Speed CMOS Logic
Dual 4 -Stage Binary Counter
2
Functional Diagram
GND = 7
V
CC
= 14
1Q
2
5
6
1Q
3
1Q
1
4
1Q
0
3
2Q
2
9
8
2Q
3
2Q
1
10
2Q
0
11
BINARY
BINARY
13
1
1CP
2CP
COUNTER
COUNTER
1MR
2
12
2MR
TRUTH TABLE
CP COUNT
OUTPUTS
Q
0
Q
1
Q
2
Q
3
0
L
L
L
L
1
H
L
L
L
2
L
H
L
L
3
H
H
L
L
4
L
L
H
L
5
H
L
H
L
6
L
H
H
L
7
H
H
H
L
8
L
L
L
H
9
H
L
L
H
10
L
H
L
H
11
H
H
L
H
12
L
L
H
H
13
H
L
H
H
14
L
H
H
H
15
H
H
H
H
CP COUNT
MR
OUTPUT
L
No Change
L
Count
X
H
L L L L
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care,
= Transition from Low to High Level,
= Transition from High to Low.
CD74HC393, CD74HCT393
3
Logic Diagram
CP
MR
1(13)
2(12)
Q
Q
Q
0
Q
1
Q
2
Q
3
3(11)
4(10)
5(9)
6(8)
R
Q
Q
Q
Q
Q
Q
R
R
R
CD74HC393, CD74HCT393
4
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
CD74HC393, CD74HCT393
5
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE: For dual-supply systems theorectical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
nCP
0.4
nMR
1
NOTE: Unit Load is
I
CC
limit specified in DC Electrical Table, e.g.,
360
A max at 25
o
C.
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Maximum Clock
Frequency
f
MAX
2
6
-
-
5
-
4
-
ns
4.5
30
-
-
24
-
20
-
ns
6
35
-
-
28
-
24
-
ns
Clock Pulse Width
t
W
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
Reset Recovery Time
t
REC
2
5
-
-
5
-
5
-
ns
4.5
5
-
-
5
-
5
-
ns
6
5
-
-
5
-
5
-
ns
CD74HC393, CD74HCT393
6
Reset Pulse Width
t
W
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
27
-
-
22
-
18
-
MHz
Clock Pulse Width
t
W
4.5
19
-
-
24
-
29
-
ns
Reset Recovery Time
t
REC
4.5
5
-
-
5
-
5
-
ns
Reset Pulse Width
t
W
4.5
16
-
-
20
-
24
-
ns
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay Time
(Figure 1)
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
45
-
55
-
70
ns
Q
n
to Q
n
+ 1
4.5
-
-
9
-
11
-
14
ns
C
L
=15pF
5
-
4
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
8
-
9
-
12
ns
nCP to nQ
0
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
150
-
190
-
225
ns
4.5
-
-
30
-
38
-
59
ns
C
L
=15pF
5
-
12
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
26
-
33
-
50
ns
nCP to nQ
1
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
190
-
245
-
295
ns
4.5
-
-
38
-
49
-
59
ns
6
-
-
33
-
42
-
50
ns
nCP to nQ
2
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
240
-
300
-
360
ns
4.5
-
-
48
-
60
-
72
ns
6
-
-
41
-
51
-
61
ns
nCP to nQ
3
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
285
-
355
-
430
ns
4.5
-
57
-
71
-
86
ns
6
-
-
48
-
60
-
73
ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
135
-
170
-
205
ns
4.5
-
-
27
-
34
-
41
ns
C
L
=15pF
5
-
11
-
-
-
-
-
ns
C
L
= 50pF
6
-
-
23
-
29
-
35
ns
Output Transition Time
(Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
IN
C
L
= 50pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
C
L
=15pF
5
-
20
-
-
-
-
-
pF
Prerequisite for Switching Specifications
(Continued)
PARAMETER
SYMBOL
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD74HC393, CD74HCT393
7
HCT TYPES
Propagation Delay Time
(Figure 1)
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
12
-
15
-
18
ns
Q
n
to Q
n
+ 1
C
L
=15pF
5
-
4
-
-
-
-
-
ns
nCP to nQ
0
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
32
-
40
-
48
ns
C
L
=15pF
5
-
13
-
-
-
-
-
ns
nCP to nQ
1
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
44
-
55
-
66
ns
nCP to nQ
2
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
50
-
63
-
75
ns
nCP to nQ
3
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
62
-
78
-
93
ns
MR to Q
n
t
PLH,
t
PHL
C
L
= 50pF
4.5
-
-
32
-
40
-
48
ns
C
L
=15pF
5
-
13
-
-
-
-
-
ns
Output Transition
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C
IN
C
L
=15pF
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
C
L
=15pF
5
-
21
-
-
-
-
-
pF
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per stage.
5. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications
Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD74HC393, CD74HCT393
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