HT2201
CMOS 1K 2-Wire Serial EEPROM
Block Diagram
Pin Assignment
Pin Description
Pin Name
I/O
Description
SDA
I/O
Serial data inputs/output
SCL
I
Serial clock data input
VSS
Negative power supply, ground
VCC
Positive power supply
Rev. 1.20
1
January 6, 2006
Features
Operating voltage: 2.2V~5.5V
Low power consumption
-
Operation: 5mA max.
-
Standby: 4
mA max.
Internal organization: 128
8
2-wire serial interface
Write cycle time: 5ms max.
Automatic erase-before-write operation
Write operation with built-in timer
40-year data retention
10
6
erase/write cycles per word
Industrial temperature range (
-40C to +85C)
4-pin SIP, SOT-25 package
General Description
The HT2201 is a 1K-bit serial read/write non-volatile
memory device using the CMOS floating gate process.
Its 1024 bits of memory are organized into 128 words
and each word is 8 bits. The device is optimized for use
in many industrial and commercial applications where
low power and low voltage operation are essential. The
HT2201 is guaranteed for 1 million erase/write cycles
and 40-year data retention.
1
2
3
4
V
C
C
S
C
L
S
D
A
G
N
D
1
2
3
4
5
N
C
G
N
D
S
C
L
S
D
A
V
C
C
H T 2 2 0 1
4 S I P - A
H T 2 2 0 1
S O T - 2 5 - A
I / O
C o n t r o l
L o g i c
M e m o r y
C o n t r o l
L o g i c
S C L
S D A
A d d r e s s
C o u n t e r
V C C
V S S
X
D
E
C
E E P R O M
A r r a y
P a g e B u f
Y D E C
S e n s e A M P
R / W C o n t r o l
H V P u m p
Absolute Maximum Ratings
Supply Voltage ..........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage .............................V
SS
-0.3V to V
CC
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=
-40C~85C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Conditions
V
CC
Operating Voltage
2.2
5.5
V
I
CC1
Operating Current
5V
Read at 100kHz
2
mA
I
CC2
Operating Current
5V
Write at 100kHz
5
mA
V
IL
Input Low Voltage
-1
0.3V
CC
V
V
IH
Input High Voltage
0.7V
CC
V
CC
+0.5
V
V
OL
Output Low Voltage
2.4V
I
OL
=2.1mA
0.4
V
I
LI
Input Leakage Current
5V
V
IN
=0 or V
CC
1
mA
I
LO
Output Leakage Current
5V
V
OUT
=0 or V
CC
1
mA
I
STB1
Standby Current
5V
V
IN
=0 or V
CC
4
mA
I
STB2
Standby Current
2.4V
V
IN
=0 or V
CC
3
mA
C
IN
Input Capacitance (See Note)
f=1MHz 25
C
6
pF
C
OUT
Output Capacitance (See Note)
f=1MHz 25
C
8
pF
Note: These parameters are periodically sampled but not 100% tested
HT2201
Rev. 1.20
2
January 6, 2006
A.C. Characteristics
Ta=
-40C~85C
Symbol
Parameter
Remark
Standard Mode*
V
CC
=5V
10%
Unit
Min.
Max.
Min.
Max.
f
SK
Clock Frequency
100
400
kHz
t
HIGH
Clock High Time
4000
600
ns
t
LOW
Clock Low Time
4700
1200
ns
t
r
SDA and SCL Rise Time
Note
1000
300
ns
t
f
SDA and SCL Fall Time
Note
300
300
ns
t
HD:STA
START Condition Hold Time
After this period the
first clock pulse is
generated
4000
600
ns
t
SU:STA
START Condition Setup Time
Only relevant for
repeated START
condition
4000
600
ns
t
HD:DAT
Data Input Hold Time
0
0
ns
t
SU:DAT
Data Input Setup Time
200
100
ns
t
SU:STO
STOP Condition Setup Time
4000
600
ns
t
AA
Output Valid from Clock
3500
900
ns
t
BUF
Bus Free Time
Time in which the bus
must be free before a
new transmission can
start
4700
1200
ns
t
SP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression
time
100
50
ns
t
WR
Write Cycle Time
5
5
ms
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means V
CC
=2.2V to 5.5V
For relative timing, refer to timing diagrams
HT2201
Rev. 1.20
3
January 6, 2006
HT2201
Rev. 1.20
4
January 6, 2006
Functional Description
Serial clock (SCL)
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
Memory Organization
HT2201, 1K-bit serial EEPROM
Internally organized with 128
8-bit words, the
HT2201 requires an 8-bit data word address for ran-
dom word addressing.
Device Operations
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (re-
fer to Start and Stop Definition Timing Diagram).
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
Device Addressing
The HT2201 requires an 8-bit device address word fol-
lowing a start condition to enable the chip for a read or
write operation. The device address word consist of a
mandatory one, zero sequence for the first four most
significant bits (refer to the diagram showing the Device
Address). This is common to all the EEPROM device.
The next three bits are fixed to zeros.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Write Operations
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
Read operations
The HT2201 supports three read operations, namely,
current address read, random address read and se-
quential read. During read operation execution, the
read/write select bit should be set to
1.
S C L
S D A
D a t a a l l o w e d
t o c h a n g e
A d d r e s s o r
a c k n o w l e d g e
v a l i d
S t o p
c o n d i t i o n
S t a r t
c o n d i t i o n
N o A C K
s t a t e
R / W
1
0
D e v i c e A d d r e s s
1
0
0
0
0
S e n d W r i t e C o m m a n d
S e n d S t o p C o n d i t i o n
t o I n i t i a t e W r i t e C y c l e
S e n d S t a r t
S e n d C o t r o l l B y t e
w i t h R / W = 0
( A C K = 0 ) ?
N e x t O p e r a t i o n
N o
Y e s
Acknowledge Polling Flow
HT2201
Rev. 1.20
5
January 6, 2006
Current address read
The internal data word address counter maintains the
last address accessed during the last read or write op-
eration, incremented by one. This address stays valid
between operations as long as the chip power is main-
tained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write se-
lect bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is seri-
ally clocked out. The microcontroller should respond a
No ACK (High) signal and following stop condition (re-
fer to Current read timing).
Random read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start con-
dition. The microcontroller now initiates a current ad-
dress read by sending a device address with the
read/write select bit high. The EEPROM acknowl-
edges the device address and serially clocks out the
data word. The microcontroller should respond with a
no ACK signal (high) followed by a stop condition.
(refer to Random read timing).
Sequential read
Sequential reads are initiated by either a current ad-
dress read or a random address read. After the
microcontroller receives a data word, it responds with an
acknowledgment. As long as the EEPROM receives an
acknowledgment, it will continue to increment the data
word address and serially clock out sequential data
words. When the memory address limit is reached, the
data word address will roll over and the sequential read
continues. The sequential read operation is terminated
when the microcontroller responds with a
no ACK sig-
nal (high) followed by a stop condition.
R / W
S
P
D e v i c e a d d r e s s
W o r d a d d r e s s
D A T A
A C K
S t o p
S t a r t
S D A
A C K
A C K
Byte Write Timing
S
P
D e v i c e a d d r e s s
D A T A
A C K
S t o p
S t a r t
S D A
N o A C K
Current Read Timing
P
D e v i c e a d d r e s s
W o r d a d d r e s s
A C K
S t o p
S t a r t
S D A
A C K
N o A C K
S
A C K
D A T A
S
D e v i c e a d d r e s s
S t a r t
Random Read Timing
P
D e v i c e a d d r e s s
D A T A n
S t o p
S t a r t
S D A
A C K
S
A C K
D A T A n + 1
D A T A n + x
N o A C K
Sequential Read Timing
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