HT46R63/HT46C63
A/D with LCD Type 8-Bit MCU
Rev. 1.90
1
May 17, 2004
General Description
The HT46R63/HT46C63 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C63 is fully pin and
functionally compatible with the OTP version HT46R63
device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
Features
Operating voltage:
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
Operating frequency: External RC or Crystal
32.768kHz crystal oscillator used for timing purposes
Watchdog enable or disable function
1x16 bits timer with an overflow interrupt (TMR)
Time base generator (clock source: 32.768kHz)
and RTC interrupts
4K
15 program memory
208
8 data memory RAM
Maximum of 32 I/O lines (shared with INT0, INT1,
TMR, AN0~AN7, PWM0~PWM3)
8-level stack
Up to 0.5
ms instruction cycle with 8MHz system clock
at V
DD
=5V
2 external interrupts (high/low going trigger)
One comparator
LCD: 20
3 or 194, 1/3 bias with 12 pins logical
outputs options. (select by options in unit of 4 pins,
8
high sink)
Built-in R type bias generator
8 channels 8-bits resolution A/D converter
4 channels PWM outputs
56-pin SSOP, 100-pin QFP package
Block Diagram
HT46R63/HT46C63
Rev. 1.90
2
May 17, 2004
I N T 0 / I N T 1
O S C 2
O S C 1
M U X
T M R
W D T
P D C
P D
P O R T D
P D 0 / P W M 0 ~ P D 3 / P W M 3
P D 4 / I N T 0
P D 5 / I N T 1
P D 6 / T M R
P D 7
P O R T B
T M R C
T M R
f
S Y S
/ 4
P r o g r a m
R O M
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
S t a c k
8 L e v e l s
I N T C 0
I N T C 1
D A T A
R A M
( 2 0 8 8 )
I n s t r u c t i o n
R e g i s t e r
M
U
X
I n s t r u c t i o n
D e c o d e r
S T A T U S
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
W D T
G e n e r a t o r
M
U
X
M
U
X
M P
P B
P B C
P B 0 / A N 0 ~ P B 7 / A N 7
P A C
P A
P O R T A
P A 0 ~ P A 7
P W M
8 - C h a n n e l A / D C o n v e r t e r
O p t i o n
P R O M
L V R
4 k 1 5
R E S
V D D
V S S
A V D D
O S C 3
O S C 4
E N / D I S
R T C O S C
W D T O S C
f
S Y S
/ 4
T i m e B a s e / R T C / L C D G e n e r a t o r
P C C
P C
P O R T C
P C 0 ~ P C 7
C o m p a r a t o r
E N / D I S
H A L T
C H G O , C M P O
C M P P , C M P N
R - B I A S
L C D
4 1 9 / 3 2 0
L o g i c a l O u t p u t O p t i o n
C O M 0 ~ C O M 3 / S E G 1 9
S E G 0 ~ S E G 1 8
H i g h
M i d d l e
L o w
V L C D
f
R T C
Pin Assignment
HT46R63/HT46C63
Rev. 1.90
3
May 17, 2004
H T 4 6 R 6 3 / H T 4 6 C 6 3
1 0 0 Q F P - A
N C
N C
N C
N C
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
V S S
P B 0 / A N 0
P B 1 / A N 1
P B 2 / A N 2
P B 3 / A N 3
P B 4 / A N 4
P B 5 / A N 5
P B 6 / A N 6
P B 7 / A N 7
A V D D
N C
N C
N C
N C
N C
N C
N C
N C
N
C
N
C
N
C
N
C
P
D
7
P
D
6
/
T
M
R
P
D
5
/
I
N
T
1
P
D
4
/
I
N
T
0
P
D
3
/
P
W
M
3
P
D
2
/
P
W
M
2
P
D
1
/
P
W
M
1
P
D
0
/
P
W
M
0
P
C
7
P
C
6
P
C
5
P
C
4
P
C
3
P
C
2
P
C
1
P
C
0
N C
N C
N C
N C
N C
N C
C O M 0
C O M 1
C O M 2
C O M 3 / S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
N C
N
C
N
C
V
L
C
D
C
M
P
N
C
M
P
P
C
M
P
O
C
H
G
O
O
S
C
4
O
S
C
3
V
D
D
O
S
C
2
O
S
C
1
R
E
S
N
C
N
C
N
C
N
C
N
C
N
C
N
C
8 1
5 1
8 0
3 1
3 0
5 0
1 0 0
1
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
H T 4 6 R 6 3 / H T 4 6 C 6 3
5 6 S S O P - A
C H G O
C M P O
C M P P
C M P N
V L C D
C O M 0
C O M 1
C O M 2
C O M 3 / S E G 1 9
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
P D 7
P D 6 / T M R
P D 5 / I N T 1
P D 4 / I N T 0
O S C 4
O S C 3
V D D
O S C 2
O S C 1
R E S
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
V S S
P B 0 / A N 0
P B 1 / A N 1
P B 2 / A N 2
P B 3 / A N 3
A V D D
P C 0
P C 1
P C 2
P C 3
P D 0 / P W M 0
P D 1 / P W M 1
P D 2 / P W M 2
P D 3 / P W M 3
Pad Assignment
HT46C63
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pin Description
Pin Name
I/O
Option
Description
PA0~PA7
I/O
Pull-high
Wake-up
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PAC). Each line of PA can be optioned
as a wake-up input (bit option). I/O configurations: Schmitt trigger/CMOS
PB0/AN0~
PB7/AN7
I/O
Pull-High
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PBC). I/O configurations: Schmitt trig-
ger/CMOS. Each PB line is pin shared with an A/D converter input.
PC0~PC6,
PC7
I/O
Pull-High
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PCC). I/O configurations: Schmitt trig-
ger/CMOS.
PD0/PWM0~
PD3/PWM3,
PD4/INT0,
PD5/INT1,
PD6/TMR,
PD7
I/O
Pull-High PWM
Interrupt Falling
and/or Rising
I/O lines with pull-high resistors (bit option). I/O modes of each line are con-
trolled by related control register bit (PDC). I/O configurations: Schmitt trig-
ger/CMOS. The PD0~PD3 can be selected as PWM outputs. INT0/INT1
are falling/rising edge selectable triggers.
HT46R63/HT46C63
Rev. 1.90
4
May 17, 2004
7 2
1
2
3
4
5
6
7
8
7 1
7 0
6 9
6 8
6 7
6 6 6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 6
4 5
4 4
4 3
4 2
4 7
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 0
9
( 0 , 0 )
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
V S S
V S S
A N 0 / P B 0
A N 1 / P B 1
A N 2 / P B 2
A N 3 / P B 3
A N 4 / P B 4
A N 5 / P B 5
A N 6 / P B 6
A N 7 / P B 7
S
E
G
0
P
D
7
P
D
6
/
T
M
R
P
D
5
/
I
N
T
1
P
D
4
/
I
N
T
0
P
D
3
/
P
W
M
3
P
D
2
/
P
W
M
2
P
D
1
/
P
W
M
1
P
D
0
/
P
W
M
0
P
C
7
P
C
6
P
C
5
P
C
4
P
C
3
P
C
2
P
C
1
P
C
0
A
V
D
D
S E G 6
S E G 1
S E G 2
S E G 3
S E G 4
S E G 5
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 1 3
C O M 3 / S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
C O M 1
C O M 2
C
O
M
0
V
L
C
D
T
R
I
M
3
C
M
P
N
T
R
I
M
2
C
M
P
P
T
R
I
M
1
C
M
P
O
C
H
G
O
O
S
C
4
O
S
C
3
V
D
D
O
S
C
2
O
S
C
1
R
E
S
Pin Name
I/O
Option
Description
OSC1
OSC2
I
O
RC or crystal
A resistor across OSC1 and VDD or a crystal across OSC1 and OSC2 will
generate a system clock.
OSC3
OSC4
I
O
32768Hz crystal across OSC3 and OSC4 will generate RTC clock signal
which only provides system timing.
CMPN
I
Negative input for comparator
CMPP
I
Positive input for comparator
CMPO
O
Comparator output
CHGO
O
Comparator output with 32768Hz carrier
VDD
Positive power supply
AVDD
A/D converter Positive power supply, AVDD should be externally con-
nected to VDD
VSS
Negative power supply, ground
RES
I
Schmitt trigger reset input
VLCD
I/O
LCD highest voltage; should be connected to VDD with external resistor.
SEG0~SEG18
O
SEG7~SEG18
logical CMOS
LCD segment signal driving outputs SEG7~SEG10 can be optioned as out-
put lines. SEG11~SEG14, SEG15~SEG18 can be optioned as a high sink-
ing output lines.
COM0~COM2
COM3/SEG19
O
COM3 or
SEG19
LCD common signal driving outputs
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
f
SYS
=8MHz
3.3
5.5
V
I
DD1
Operating Current (RC OSC)
(Analog Circuit Disabled)
3V
No load, f
SYS
=4MHz
1
2
mA
5V
3
5
I
DD2
Operating Current
(RC OSC)
3V
No load, f
SYS
=4MHz
1
2
mA
5V
3
5
I
DD3
Operating Current
5V
No load, f
SYS
=8MHz
3
5
mA
I
STB1
Standby Current
(WDT OSC On, RTC Off, LCD Off)
3V
No load,
System HALT
5
mA
5V
15
I
STB2
Standby Current
(WDT OSC Off, RTC Off, LCD Off)
3V
System HALT
1
mA
5V
1
HT46R63/HT46C63
Rev. 1.90
5
May 17, 2004
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