HT48E50
I/O Type 8-Bit MTP MCU With EEPROM
Rev. 0.00
1
September 29, 2004
General Description
The HT48E50 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Features
Operating voltage:
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
Low voltage reset function
33 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler
On-chip crystal and RC oscillator
Watchdog Timer
4096
15 program memory ROM (MTP)
256
8 data memory EEPROM
160
8 data memory RAM
HALT function and wake-up feature reduce power
consumption
6-level subroutine nesting
Up to 0.5
ms instruction cycle with 8MHz system clock
at V
DD
=5V
Bit manipulation instruction
15-bit table read instruction
63 powerful instructions
10
6
erase/write cycles EEPROM data memory
EEPROM data retention > 10 years
All instructions in one or two machine cycles
In system programming (ISP)
28-pin SKDIP/SOP, 48-pin SSOP package
Preliminary
Block Diagram
HT48E50
Rev. 0.00
2
September 29, 2004
Preliminary
P G 0 / I N T
O S C 2
O S C 1
R E S
V D D
M U X
T M R 0
T M R 0 C
T M R 0
V S S
P r e s c a l e r
f
S Y S
P G 0
P r o g r a m
M e m o r y
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
S T A C K
I N T C
D A T A
M e m o r y
I n s t r u c t i o n
R e g i s t e r
M
U
X
I n s t r u c t i o n
D e c o d e r
S T A T U S
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
M
U
X
M P
W D T S
W D T
W D T O S C
W D T P r e s c a l e r
M
U
X
E N / D I S
D a t a M e m o r y
E E P R O M
P D C
P O R T D
P D 0 ~ P D 7
P G C
P G
P O R T G
P B C
P O R T B
P B 0 / B Z
P B 1 / B Z
P B 2 ~ P B 7
B Z / B Z
P B
P A C
P O R T A
P A 0 ~ P A 7
P A
P D
P C
P O R T C
P C 0 ~ P C 7
P C C
T M R 1 C
T M R 1
M
U
X
T M R 1
f
S Y S
/ 4
f
S Y S
/ 4
B P
E E C R
P G 0 / I N T
Pin Assignment
Pad Assignment
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT48E50
Rev. 0.00
3
September 29, 2004
Preliminary
( 0 , 0 )
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 1
3 0
2 9
2 8
2 7
4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2
T R I M 1
T R I M 2
T R I M 3
P B 3
P B 2
P B 1
P B 0
P D 7
P D 6
P D 5
P D 4
P
D
3
P
D
2
P
D
1
P
D
0
T
M
R
0
P
G
0
V
S
S
P
C
7
P
C
6
P
C
5
P
C
4
P
C
3
P
C
2
P
C
1
P
C
0
O S C 2
O S C 1
V D D
R E S
T M R 1
P
A
7
P
A
6
P
A
5
P
A
4
P
B
7
P
B
6
P
B
5
P
B
4
P
A
3
P
A
2
P
A
1
P
A
0
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5 / T M R 1
P C 4
P C 3
P C 2
P B 5
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 / B Z
P B 0 / B Z
V S S
P G 0 / I N T
P C 0 / T M R 0
P C 1
H T 4 8 E 5 0
2 8 S K D I P - A / S O P - A
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
H T 4 8 E 5 0
4 8 S S O P - A
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
N C
N C
N C
N C
O S C 2
O S C 1
V D D
R E S
T M R 1
P D 3
P D 2
P D 1
P D 0
P C 7
P C 6
P C 5
P C 4
P C 3
P B 5
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 / B Z
P B 0 / B Z
N C
N C
N C
N C
P D 7
P D 6
P D 5
P D 4
V S S
P G 0 / I N T
T M R 0
P C 0
P C 1
P C 2
Pad Description
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Pull-high*
Wake-up
CMOS/Schmitt
trigger Input
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by options. Software instructions determine the CMOS out-
put or Schmitt trigger input or CMOS input with pull-high resistor (determined
by pull-high options).
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
I/O or BZ/BZ
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
The PB0 and PB1 are pin-shared with BZ and BZ, respectively. Once the
PB0 and PB1 are selected as buzzer driving outputs, the output signals
come from an internal PFD generator (shared with Timer/Event Counter 0).
PD0~PD7
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tions).
VSS
Negative power supply, ground
PG0/INT
I/O
Pull-high*
Bidirectional I/O line. Software instructions determine the CMOS output or
Schmitt trigger input with pull-high resistor (determined by pull-high op-
tions). The external interrupt input INT, is pin-shared with PG0 and is acti-
vated on a high to low transition.
TMR0
I
Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor)
PC0~PC7
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high op-
tions).
TMR1
I
Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor)
RES
I
Schmitt trigger reset input. Active low.
VDD
Positive power supply
OSC1
OSC2
I
O
Pull-high*
Crystal
or RC
OSC1, OSC2 are connected to an RC network or Crystal (determined by
options) for the internal system clock. In the case of RC operation, OSC2 is
the output terminal for 1/4 system clock.
Note:
* The pull-high resistors of each I/O port (PA, PB, PC, PD, PG) are controlled by options.
CMOS or Schmitt trigger option of port A is controlled by an option.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT48E50
Rev. 0.00
4
September 29, 2004
Preliminary
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
f
SYS
=8MHz
3.3
5.5
V
I
DD1
Operating Current (Crystal OSC)
3V
No load, f
SYS
=4MHz
1
2
mA
5V
3
5
mA
I
DD2
Operating Current (RC OSC)
3V
No load, f
SYS
=4MHz
1
2
mA
5V
2.5
4
mA
I
DD3
Operating Current
(Crystal OSC, RC OSC)
5V
No load, f
SYS
=8MHz
4
8
mA
I
STB1
Standby Current
(WDT Enabled)
3V
No load, system HALT
5
mA
5V
10
mA
I
STB2
Standby Current
(WDT Disabled)
3V
No load, system HALT
1
mA
5V
2
mA
V
IL1
Input Low Voltage for I/O Ports
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset
LVRenabled
2.7
3.0
3.3
V
I
OL
I/O Port Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
5V
V
OL
=0.1V
DD
10
20
mA
I
OH
I/O Port Source Current
3V
V
OH
=0.9V
DD
-2
-4
mA
5V
V
OH
=0.9V
DD
-5
-10
mA
R
PH
Pull-high Resistance
3V
20
60
100
k
W
5V
10
30
50
k
W
HT48E50
Rev. 0.00
5
September 29, 2004
Preliminary
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