HI-1567, HI-1568
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The HI-1567 and HI-1568 are low power CMOS dual
transceivers designed to meet the requirements of
MIL-STD-1553 /1760 specifications.
The transmitter section of each channel takes
complimentary CMOS / TTL digital input data and converts
it to bi-phase Manchester encoded 1553 signals suitable
for driving the bus isolation transformer. Separate
transmitter inhibit control signals are provided for each
transmitter.
The receiver section of the each channel converts the 1553
bus bi-phase data to complimentary CMOS / TTL data
suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used to
force the output of the receiver to a logic 0 (HI-1567) or
logic 1 (HI-1568).
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer. For designs requiring
independent access to transmitter and receiver 1553
signals, please contact your Holt Sales representative.
VDDA 1
BUSA 2
3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
8
RXENB 9
GNDB 10
BUSA
BUSB
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Compliant to MIL-STD-1553A & B,
MIL-STD-1760
CMOS technology for low standby power
Smallest footprint available in 20 pin plastic
ESOIC (thermally enhanced SOIC) package
Less than 1.0W maximum power dissipation
Available in DIP, Flatpack and small outline
(ESOIC) package options
Military processing options
Industry standard pin configurations
20 Pin Ceramic DIP package
20
19 TXA
18 TXINHA
17 RXA
16
15
14 TXB
13 TXINHB
12 RXB
11
TXA
RXA
TXB
RXB
VDDA
BUSA
RXENA
GNDA
VDDB
BUSB
RXENB
GNDB
BUSA
BUSB
TXA
RXA
TXB
RXB
TXA
TXINHA
RXA
TXB
TXINHB
RXB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20 Pin Plastic ESOIC - WB package
March 2001
(DS1567 Rev. B)
03/01
HOLT INTEGRATED CIRCUITS
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HI-1567, HI-1568
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
VDDA
power supply
+5 volt power for channel A
2
BUSA
analog output
MIL-STD-1533 bus driver A, positive signal
3
analog output
MIL-STD-1553 bus driver A, negative signal
4
RXENA
digital input
Receiver A enable. If low, forces RXA and
low (HI-1567) or High (HI-1568)
5
GNDA
power supply
Ground for channel A
6
VDDB
7
BUSB
9
RXENB
10
GNDB
11
12
RXB
digital output
Receiver B outpot, non-invertedl
13
TXINHB
digital input
Transmit inhibit, channel B. If high BUSB,
disabled
14
TXB
digital input
Transmitter B digital data input, non-inverted
15
digital input
Transmitter B digital data input, inverted
16
digital output
BUSA
RXA
BUSB
TXB
RXA
power supply
+5 volt power for channel B
analog output
MIL-STD-1533 bus driver B, positive signal
8
analog output
MIL-STD-1553 bus driver B, negative signal
digital input
Receiver B enable. If low, forces RXB and
low (HI-1567) or High (HI-1568)
power supply
Ground for channel B
digital output
Receiver B output, inverted
Receiver A output, inverted
17
RXA
digital output
Receiver A output, non-inverted
18
TXINHA
digital input
Transmit inhibit, channel A. If high BUSA,
disabled
19
TXA
digital input
Transmitter A digital data input, non-inverted
15
digital input
Transmitter A digital data input, inverted
BUSB
RXB
RXB
BUSA
TXA
The HI-1567 family of data bus transceivers contain differ-
ential voltage source drivers and differential receivers.
They are intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
Data input to the transmitter section of these devices is
from the complimentary CMOS /TTL inputs TXA/B and
. This produces a nominal 30V peak to peak signal
across a 140 ohm load. The transmitter is connected to the
bus via a 1:2.5 transformer whose secondary is connected
to two 52 ohm isolation resisters which feed the terminated
70 ohm bus. This will produce a nominal voltage on the bus
of 7.5 volts peak to peak.
TRANSMITTER
TXA/B
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and
are ei-
ther at a logic "1" or logic "0" simultaneously. A logic "1:" ap-
plied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
The receiver outputs can both be forced to a logic "0"
(HI-1567) or logic "1" (HI-1568) by setting RXENA or
RXENB low.
TXA/B
TXA/B
RECEIVER
The receiver is transformer coupled to the bus by a 1:1
transformer. Its differential input stage drives a filter and
threshold comparator. CMOS/TTL data is outputted at the
RXA/B and
pins.
RXA/B
HOLT INTEGRATED CIRCUITS
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PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Operating Voltage
VDD
4.75
5
5.25
V
Total Supply Current
ICC1
Not Transmitting
22
mA
ICC2
Transmit one channel @
320
340
mA
50% duty cycle
ICC3
Transmit one channel @
570
615
mA
100% duty cycle
Power Dissipation
PD1
Not Transmitting
0.4
W
PD2
Transmit one channel @
0.95
W
100% duty cycle
Min. Input Voltage
(HI)
V
Digital inputs
2.0
1.4
V
Max. Input Voltage
(LO)
V
Digital inputs
1.4
0.8
V
Min. Input Current
(HI)
I
V
= 4.9V, Digital inputs
20
A
Max. Input Current
(LO)
I
V
= 0.1V, Digital inputs
-20
A
Min. Output Voltage
(HI)
V
I
= -0.4mA, Digital outputs
2.7
V
Max. Output Voltage
(LO)
V
I
= 4.0mA, Digital outputs
0.4
V
Input resistance
Rin
Differential
20
kohm
Input capacitance
Cin
Differential
5
pF
Common mode rejection ratio
CMRR
40
dB
Input Level
Vin
Differential
8
Vp-p
Input common mode voltage
VICM
-5.0
5.0
V-pk
Threshold Voltage
VTH
1 MHz Sine Wave
0.56
1.2
Vp-p
Output Voltage
35 ohm load
7.0
9.0
Vp-p
140 ohm load
28.0
36.0
Vp-p
Output Noise
VON
Differential, inhibited
10.0
mVp-p
Output Dynamic Offset Voltage
Across 35 ohm load
-90
90
mV
Across 140 ohm load
-360
360
mV
Output resistance
Rout
Differential, not transmitting
10
kohm
Output Capacitance
Cout
1 MHz sine wave
15
pF
IH
IL
IH
IH
IL
IL
OH
OUT
IH
OUT
RECEIVER
TRANSMITTER
(Measured at Point "A" in Figure 2)
(Measured at Point "V " in Figure 2)
IN
Vout
Vdyn
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
Supply voltage (
Logic input voltage range
Power dissipation at 25C
0.5 W
ceramic DIL, derate
7mW/C
Solder Temperature
275C for 10 sec
Storage Temperature
-65C to +150C
VDD)
-0.3 V to +7 V
-0.3 V dc to +5.5 V
Receiver differential voltage
10 Vp-p
Driver peak output current
+1.0 A
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Temperature Range
Industrial Screening.........-40C to +85C
Hi-Temp Screening........-55C to +125C
Military Screening..........-55C to +125C
VDD....................................... 5V... 5%
VDD = 5.0V, V
= 0V, T = Operating Temperature Range (unless otherwise specified).
SS
A
HI-1567, HI-1568
HOLT INTEGRATED CIRCUITS
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PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Receiver Enable Delay
tREN
From RXENA/B rising or falling edge to
40
ns
RXA/B or
Driver Delay
tDT
TXA/B, TXA/B to BUSA/B, BUSA/B
150
ns
Rise time
tr
35 ohm load
100
300
ns
Fall Time
tf
35 ohm load
100
300
ns
Inhibit Delay
tDI-H
Inhibited output
100
ns
tDI-L
Active output
150
ns
RECEIVER
TRANSMITTER
(Measured at Point "V " in Figure 2)
(Measured at Point "A" in Figure 2)
IN
Receiver Delay
tDR
From input zero crossing to RXA/B or
450
ns
RXA/B
RXA/B
VCC = 5.0V, V
= 0V, T =Operating Temperature Range (unless otherwise specified).
SS
A
HI-1567, HI-1568
Figure 2. Test circuit
TXA/B
TXA/B
TXINHA/B
TRANSMITTER
RECEIVER
1:2.5
A
55
55
35
2.5:1
55
55
35
RXENA/B
BUSA/B
BUSA/B
V
IN
RXA/B
RXA/B
HOLT INTEGRATED CIRCUITS
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