HI-3182, HI-3183, HI-3184, HI-3185
HI-3186, HI-3187, HI-3188
The HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187 and
HI-3188 bus interface products are silicon gate CMOS devices
designed as a line driver in accordance with the ARINC 429 bus
specifications. In addition to being functional upgrades of Holt's
HI-8382 & HI-8383 products, they are also alternate sources for
the HS-3182 ( Intersil/Harris), the RM3182 (Fairchild /Raytheon)
and a variety of similar DEI/DDC line driver products.
Inputs are provided for clocking and synchronization. These
signals are AND'd with the DATA inputs to enhance system
performance and allow the HI-318X series of products to be
used in a variety of applications. Both logic and synchronization
inputs feature built-in 2,000V minimum ESD input protection as
well as TTL and CMOS compatibility.
The differential outputs of the HI-318X series of products are
independently programmable to either the high speed or low
speed ARINC 429 output rise and fall time specifications through
the use of two external capacitors. The output voltage swing is
also adjustable by the application of an external voltage to the
VREF input. Products with 0, 13 or 37.5 ohm resistors in series
with each ARINC output are available. In addition, the
fuse in series with
each output.
The HI-318X series of line drivers are intended for use where
logic signals must be converted to ARINC 429 levels such as
when using an ASIC, the HI-8282 ARINC 429 Serial Transmit-
ter/Dual Receiver, the HI-6010 ARINC 429 Transmitter/Receiver
or the HI-8783 ARINC Interface Device.
Holt products are
readily available for both industrial and military applications.
Please contact the Holt Sales Department for additional
information.
HI-3182,
HI-3184 and HI-3187 products also have a
PIN CONFIGURATION
(Top View)
GENERAL DESCRIPTION
!
!
!
!
!
!
Low power CMOS
TTL and CMOS compatible inputs
Programmable output voltage swing
Plastic 14 & 16-pin thermally enhanced SOIC
packages available
Pin-for-Pin alternative for DEI/DDC/Intersil/Fairchild
applications
Operates at data rates up to 100 Kbits
Overvoltage protection
Industrial and Military temperature ranges
!
!
!
Adjustable ARINC rise and fall times
FEATURES
HI-3184PS, HI-3185PS, HI-3186PS
& HI-3187PS
14 - PIN PLASTIC SMALL OUTLINE (ESOIC)**
FUNCTION
ARINC 429 DIFFERENTIAL LINE DRIVER
+
TRUTH TABLE
SYNC CLOCK DATA(A) DATA(B) AOUT
BOUT COMMENTS
X
L
X
X
0V
0V
NULL
L
X
X
X
0V
0V
NULL
H
H
L
L
0V
0V
NULL
H
H
L
H
-V
+V
LOW
H
H
H
L
+V
-V
HIGH
H
H
H
H
0V
0V
NULL
REF
REF
REF
REF
March 2001
14 V
13 CLOCK
12 DATA (B)
11 C
10 B
9
+V
8
GND
1
B
OUT
V
1
GND (See Note * ) 2
SYNC 3
DATA (A) 4
C
5
A
6
-V
7
REF
A
OUT
(See Page 5 for additional package pin configurations)
Notes: * Pin 2 may be left floating
** Thermally Enhanced SOIC Package
(DS3182 Rev. B )
03/01
HOLT INTEGRATED CIRCUITS
1
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input. Each logic
input, including the power enable (
) input, are
TTL/CMOS compatible.
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-3182;
typically +15V, -15V and +5V. The chip also works with 12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing.
The
differential output voltage swing will equal 2V
. If a value of
V
other than +5V is needed, a separate +5V power supply
is required for pin V .
With the DATA (A) input at a logic high and DATA (B) input at a
logic low, A
will switch to the +V
rail and B
will
switch to the -V
rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULL state).
The driver output impedance, R
, is nominally 75, 26 or 0
ohms depending on the option chosen. The rise and fall times
of the outputs can be calibrated through the selection of two
external capacitor values th
re connected to the C and C
input pins. Typical values for high-speed operation
(100KBPS) are C = C = 75pF and for low-speed operation
(12.5 to 14KBPS) C = C = 500pF.
STROBE
REF
REF
OUT
REF
OUT
REF
OUT
1
A
B
A
B
A
B
at a
The C and C pins swing between +5V and ground allowing
the switching of capacitor values with an external single-
supply analog switch.
A
B
The ARINC outputs can be put in a tri-state mode by applying
a logic high to the
input pin. If this feature is not
being used, the pin should be tied to ground. The
function is not available in the 14 & 16-pin SOIC package
configurations where the pin is internally connected to
ground.
The ARINC outputs of the HI-3182, HI-3184 and HI-3187 are
protected by internal fuses capable of sinking between 800 -
900 mA for short periods of time (125 s).
STROBE
STROBE
DATA (A)
OUT
DATA (B)
INPUTS
TO ARINC BUS
B
REF
V
1
V
SYNC
CLOCK
-V
+V
STROBE
GND
C
C
-15V
+15V
+5V
Figure 1. ARINC 429 BUS APPLICATION
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
Figure 2. FUNCTIONAL BLOCK DIAGRAM
OUT
B
Shorted on
HI-3186, HI-3187, HI-3188
C
L
REF
F
A
R
L
F
B
OUTPUT
DRIVER (B)
OUTPUT
DRIVER (A)
B
C
GND
-V
DATA (A)
DATA (B)
SYNC
CLOCK
V
1
STROBE
A
C
+V
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
CURRENT
REGULATOR
13
24.5
13
24.5
Shorted on
HI-3183, HI-3186
HI-3187, HI-3188
Shorted on
HI-3183, HI-3185
HI-3186, HI-3188
HOLT INTEGRATED CIRCUITS
2
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
OPERATING RANGE
MAXIMUM
UNIT
Differential Voltage
V
Voltage between +V and -V terminals
40
V
Supply Voltage
+V
+10.8 to +16.5
V
-V
-10.8 to -16.5
V
V
+5 10%
+7
V
Voltage Reference
V
For ARINC 429
+5 5%
6
V
For Applications other than ARINC
0 to 6
6
V
Input Voltage Range
V
GND -0.3
V
V1 +0.3
V
Output Short-Circuit Duration
See Note: 1
Output Overvoltage Protection
See Note: 2
Operating Temperature Range
T
Hi-temp & Military
-55 to +125
C
Industrial
-40 to +85
C
Storage Temperature Range
T
Ceramic & Plastic
-65 to +150
C
Lead Temperature
Soldering, 10 seconds
+275
C
Junction Temperature
T
+175
C
Note 1. Heatsinking may be required for Output Short Circuit at +125C and for 100KBPS at +125C.
Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater
than 12.0V with respect to GND. (HI-3182, 3184 & 3187 only)
DIF
1
REF
IN
A
STG
J
>
<
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SYMBOL
FUNCTION
DESCRIPTION
V
POWER
Reference voltage used to determine the output voltage swing
INPUT
A logic high tri-states the ARINC outputs. Not available in the 14-pin SOIC package (tied to GND internally).
SYNC
INPUT
Synchronizes data inputs
DATA (A)
INPUT
Data input terminal A
C
INPUT
Connection for DATA (A) slew-rate capacitor
A
OUTPUT
ARINC output terminal A
-V
POWER
-12V to -15V
GND
POWER
0.0V
+V
POWER
+12V to +15V
B
OUTPUT
B
C
INPUT
DATA (B)
INPUT
B
CLOCK
INPUT
Synchronizes data inputs
V
POWER
+5V 5%
REF
A
OUT
OUT
B
1
STROBE
ARINC output terminal
Connection for DATA (B) slew-rate capacitor
Data input terminal
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
HOLT INTEGRATED CIRCUITS
3
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Supply Current +V (Operating)
(+V)
No Load
(0 - 100KBPS)
+16
mA
Supply Current -V (Operating)
(-V)
No Load
(0 - 100KBPS)
-16
mA
Supply Current
(Operating)
(
)
No Load
(0 - 100KBPS)
500
A
Supply Current
(Operating)
(
)
No Load,
REF = 5V (0 - 100KBPS)
-1.0
mA
Supply Current +V (During Short Circuit Test)
(+V)
Short to Ground
(See Note: 1)
150
mA
Supply Current -V (During Short Circuit Test)
(-V)
Short to Ground
(See Note: 1)
-150
mA
Output Short Circuit Current (Output High)
Short to Ground
=0 (See Note: 2)
-80
mA
Output Short Circuit Current (Output Low)
Short to Ground
=0 (See Note: 2)
+80
mA
Input Current (Input High)
1.0
A
Input Current (Input Low)
-1.0
A
Input Voltage High
2.0
V
Input Voltage Low
0.5
V
Output Voltage High (Output to Ground)
No Load
(0 -100KBPS)
+V
+V
V
-.
+.
Output Voltage Low (Output to Ground)
No Load
(0 -100KBPS)
-V
-V
V
-.
+.
Output Voltage Null
No Load
(0-100KBPS)
-250
+250
mV
Input Capacitance
15
pF
I
I
V
I
V
V
I
V
V
I
I
I
V
I
V
I
I
V
V
V
V
V
C
CCOP
CCOP
1
CCOP
1
REF
CCOP
REF
SC
SC
OHSC
MIN
OLSC
MIN
IH
IL
IH
IL
OH
25
25
OL
25
25
NULL
IN
See Note 1
REF
REF
REF
REF
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter.
Note 2. Interchangeability of force and sense is acceptable.
+V = +15V, -V = -15V, V = V
= +5.0V, T
= Operating Temperature Range (unless otherwise specified).
1
REF
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Rise Time (
,
)
=
= 75pF
See Figure 3.
1.0
2.0
s
Fall Time (
,
)
=
= 75pF
See Figure 3.
1.0
2.0
s
Propagtion Delay Input to Output
=
= 75pF
See Figure 3.
3.0
s
Propagtion Delay Input to Output
=
= 75pF
See Figure 3.
3.0
s
A
B
t
C
C
A
B
t
C
C
t
C
C
t
C
C
OUT
OUT
R
A
B
OUT
OUT
F
A
B
PLH
A
B
PHL
A
B
Figure 3. SWITCHING WAVEFORMS
-9.5V to -10.5V
+9.5V to +10.5V
-4.75V to -5.25V
2.0V
+4.75V to +5.25V
2.0V
0.5V
0.5V
-4.75V to -5.25V
+4.75V to +5.25V
DATA (A) 0V
DATA (B) 0V
A
OUT
0V
B
OUT
0V
DIFFERENTIAL
OUTPUT 0V
(
)
A
B
OUT -
OUT
50%
50%
V
REF
ADJUST
BY
C
A
t
PHL
ADJUST
BY
C
A
-V
REF
50%
50%
t
PLH
t
R
+V
REF
-V
REF
ADJUST
BY
C
B
ADJUST
BY
C
B
t
F
2V
REF
-2V
REF
HIGH
NULL
LOW
NOTE: OUTPUTS UNLOADED
+V = +15V, -V = -15V, V = V
= +5.0V, T
= Operating Temperature Range (unless otherwise specified).
1
REF
A
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
HOLT INTEGRATED CIRCUITS
4
ADDITIONAL PIN CONFIGURATIONS
(See page 1 for 14-Pin Small Outline SOIC)
5
6
7
8
9 10 11 12 13
30
31
32
1
2
3
4
20
19
18
17
16
15
14
N/C
N/C
+V
GND
N/C
-V
N/C
CLOCK
V
N/C
V
SYNC
N/C
1
REF
STROBE
HI-3182CR
HI-3183CR
32 - PIN
CERQUAD
29 28 27 26 25 24 23 22 21
VREF
STROBE
SYNC
DATA(A)
CA
AOUT
-V
GND
+V
N/C
BOUT
CB
DATA(B)
CLOCK
V1
N/C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HI-3182CD
HI-3183CD
16 - PIN
CERAMIC
DIP
V
- 1
GND (See Note * ) - 2
SYNC - 3
DATA(A) - 4
C
- 5
A
- 6
-V - 7
GND - 8
REF
A
OUT
16 - V
15 - N/C
14 - CLOCK
13 - DATA(B)
12 - C
11 - B
10 - N/C
9 - +V
1
B
OUT
16 - PIN
PLASTIC
SMALL
OUTLINE
(ESOIC)**
CLOCK
N/C
DATA (B)
C
N/C
N/C
N/C
B
12 13 14 15 16 17 18
5
6
7
8
9
10
11
N/C
DATA (A)
N/C
N/C
C
N/C
N/C
A
HI-3182PJ
HI-3183PJ
28 - PIN
PLASTIC
PLCC
4
3
2
1 28 27 26
25
24
23
22
21
20
19
4
3
2
1 28 27 26
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
CLOCK
N/C
DATA (B)
C
N/C
N/C
N/C
B
N/C
DATA (A)
N/C
N/C
C
N/C
N/C
A
HI-3182CL
HI-3183CL
28 - PIN
CERAMIC
LCC
HI-3182PS, HI-3183PS, HI-3188PS
Notes:
** Thermally Enhanced SOIC package
* Pin 2 may be left floating
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3187, HI-3188
HOLT INTEGRATED CIRCUITS
5
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