HOLT INTEGRATED CIRCUITS
www.holtic.com
ARINC INPUTS TESTA TESTB OUTA OUTB
INA - INB
-2.5 to +2.5 V
0
0
0
0
< -6.5 V
0
0
0
1
> +6.5 V
0
0
1
0
X
0
1
0
1
X
1
0
1
0
X
1
1
0
0
FUNCTION TABLE
44-Pin Plastic Quad Flat Pack (PQFP)
44
-
IN2
AX
43
-
IN1
BY
42
-
IN1
AY
41
-
IN1
BX
40
-
IN1
AX
39
-
N/C
38
-
OUT1
AX
37
-
OUT1
BX
36
-
OUT1
AY
35
-
OUT1
BY
34
-
OUT2
AX
33 - OUT2 BX
32 - OUT2 AY
31 - OUT2 BY
30 - N/C
29 - VDD
28 - N/C
27 - VSS
26 - N/C
25 - OUT3 AX
24 - OUT3 BX
23 - OUT3 AY
IN3
BY
-1
2
IN4
AX
-1
3
IN4
BX
-1
4
IN4
AY
-
1
5
IN4
BY
-1
6
N/C
-1
7
OUT4
BY
-1
8
OUT4
AY
-
1
9
OUT4
BX
-2
0
OUT4
AX
-2
1
OUT3
BY
-2
2
IN2 BX - 1
IN2 AY - 2
IN2 BY - 3
N/C - 4
TESTA(X) - 5
TESTB(X) - 6
TESTA(Y) - 7
TESTB(Y) - 8
IN3 AX - 9
IN3 BX - 10
IN3 AY - 11
HI-8448PQ
HI-8448PQ-10
Octal
Receiver
HI-8444PS
HI-8444PS-10
&
HI-8445PS
HI-8445PS-10
Quad
Receiver
HI-8444, HI-8445, HI-8448
Quad / Octal ARINC 429 Line Receivers
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The HI-8444 and HI-8445 are quad ARINC 429 line
receiver ICs available in a 20-pin TSSOP package. The HI-
8448 contains 8 independent ARINC 429 line receivers.
The technology is analog / digital CMOS. The device is
designed to operate from either a 5V or 3.3V supply. Each
receiver channel translates incoming ARINC 429 data bus
signals to a pair of TTL / CMOS outputs.
The optional HI-8444-10, HI-8445-10 and HI-8448-10 are
designed to be used with an external 10 Kohm series
resistor. The "-10" devices meet the lightning protection
requirements of DO-160C/D level 3, waveforms 3, 4, and
5A.
The TESTA and TESTB inputs bypass the analog inputs for
testing purposes. They force the receiver outputs to the
specified ZERO, ONE or NULL state. The ARINC inputs
are ignored when the device is in the test mode.
The HI-8445 is identical to the HI-8444 except the TESTA
and TESTB pins are not available.
!
!
!
!
!
Direct ARINC 429 quad or octal line receivers in small
footprint packages
3.3V or 5.0V single supply operation
Test inputs bypass analog inputs and force digital
outputs to a one, zero, or null state
ARINC inputs are internally lightning protected per DO-
160C/D level 3 (-10 configuration only)
Military processing options available
IN1 A
IN1 B
IN2 A
IN2 B
TESTA (8444 only)
TESTB (8444 only)
IN3 A
IN3 B
IN4 A
IN4 B
OUT1 A
OUT1 B
OUT2 A
OUT2 B
VDD
VSS
OUT3 A
OUT3 B
OUT4 A
OUT4 B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20 Pin Plastic TSSOP package
January 2003
(DS8444 Rev. C)
01/03
PIN DESCRIPTIONS (HI-8444, HI-8445)
HOLT INTEGRATED CIRCUITS
2
BLOCK DIAGRAMS
IN1 A
IN1 B
IN2 A
IN2 B
IN3 A
IN3 B
IN4 A
IN4 B
TESTA
TESTB
OUT1 A
OUT1 B
OUT2 A
OUT3 A
OUT3 B
OUT4 A
OUT4 B
OUT2 B
IN1 A
IN1 B
IN2 A
IN2 B
IN3 A
IN3 B
IN4 A
IN4 B
OUT1 A
OUT1 B
OUT2 A
OUT3 A
OUT3 B
OUT4 A
OUT4 B
OUT2 B
HI-8444
HI-8445
IN4 AX
OUT1 AX
OUT4 A
OUT4 B
IN1 AX
IN1 BX
IN2 AX
IN2 BX
IN3 AX
IN3 BX
IN4 BX
TESTA(X)
TESTB(X)
OUT1 BX
OUT2 AX
OUT3 AX
OUT3 BX
OUT4 AX
OUT4 BX
OUT2 BX
TESTA(Y)
TESTB(Y)
IN4 AY
IN1 AY
IN1 BY
IN2 AY
IN2 BY
IN3 AY
IN3 BY
IN4 BY
OUT1 AY
OUT1 BY
OUT2 AY
OUT3 AY
OUT3 BY
OUT4 AY
OUT4 BY
OUT2 BY
HI-8448
HI-8444, HI-8445, HI-8448
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
IN1 A
ARINC input
Receiver 1 positive input
2
IN1 B
ARINC input
3
IN2 A
4
IN2 B
5
TESTA
Logic input
Test input. (Not available on HI-8445)
6
TESTB
7
IN3 A
9
IN4 A
10
IN4 B
11
OUT4 B
12
OUT4 A
13
OUT3 B
14
OUT3 A
15
VSS
Power
Ground
16
VDD
Power
Positive supply voltage 3.3V or 5.0 V
Receiver 1 negative input
ARINC input
Receiver 2 positive input
ARINC input
Receiver 2 negative input
Logic input
Test input. (Not available on HI-8445)
ARINC input
Receiver 3 positive input
8
IN3 B
ARINC input
Receiver 3 negative input
ARINC input
Receiver 4 positive input
ARINC input
Receiver 4 negative input
Logic output
Receiver 4 "ZERO" output
Logic output
Receiver 4 "ONE" output
Logic output
Receiver 3 "ZERO" output
Logic output
Receiver 3 "ONE" output
17
OUT2 B
Logic output
Receiver 2 "ZERO" output
18
OUT2 A
Logic output
Receiver 2 "ONE" output
19
OUT1 B
Logic output
Receiver 1 "ZERO" output
20
OUT1 A
Logic output
Receiver 1 "ONE" output
HI-8444, HI-8445, HI-8448
PIN DESCRIPTIONS (HI-8448)
PIN
SYMBOL
FUNCTION
RECEIVER SET
DESCRIPTION
1
IN2 BX
ARINC input
X
2
IN2 AY
ARINC input
Y
3
IN2 BY
4
N/C
Not connected
5
TESTA(X)
Logic input
X
Test input
6
TESTB(X)
7
TESTA(Y)
9
IN3 AX
10
IN3 BX
11
IN3 AY
12
IN3 BY
13
IN4 AX
14
IN4 BX
15
IN4 AY
Y
16
IN4 BY
Y
Receiver 2 negative input
Receiver 2 positive input
ARINC input
Y
Receiver 2 negative input
Logic input
X
Test input
Logic input
Y
Test input
8
TESTB(Y)
Logic input
Y
Test input
ARINC input
X
Receiver 3 positive input
ARINC input
X
Receiver 3 negative input
ARINC input
Y
Receiver 3 positive input
ARINC input
Y
Receiver 3 negative input
ARINC input
X
Receiver 4 positive input
ARINC input
X
Receiver 4 negative input
ARINC input
Receiver 4 positive input
ARINC input
Receiver 4 negative input
17
N/C
Not connected
18
OUT4 BY
Logic output
Y
Receiver 4 "ZERO" output
19
OUT4 AY
Logic output
Y
Receiver 4 "ONE" output
20
OUT4 BX
Logic output
X
Receiver 4 "ZERO" output
21
OUT4 AX
Logic output
X
Receiver 4 "ONE" output
22
OUT3 BY
Logic output
Y
Receiver 3 "ZERO" output
23
OUT3 AY
Logic output
Y
Receiver 3 "ONE" output
24
OUT3 BX
Logic output
X
Receiver 3 "ZERO" output
25
OUT3 AX
Logic output
X
Receiver 3 "ONE" output
26
N/C
Not connected
27
VSS
Power
Ground supply
28
N/C
Not connected
29
VDD
Power
Positive supply voltage 3.3V or 5.0 V
30
N/C
Not connected
31
OUT2 BY
Logic output
Y
Receiver 2 "ZERO" output
32
OUT2 AY
Logic output
Y
Receiver 2 "ONE" output
33
OUT2 BX
Logic output
X
Receiver 2 "ZERO" output
34
OUT2 AX
Logic output
X
Receiver 2 "ONE" output
35
OUT1 BY
Logic output
Y
Receiver 1 "ZERO" output
36
OUT1 AY
Logic output
Y
Receiver 1 "ONE" output
37
OUT1 BX
Logic output
X
Receiver 1 "ZERO" output
38
OUT1 AX
Logic output
X
Receiver 1 "ONE" output
39
N/C
Not connected
40
IN1 AX
ARINC input
X
Receiver 1 positive input
41
IN1 BX
ARINC input
X
Receiver 1 negative input
42
IN1 AY
ARINC input
Y
Receiver 1 positive input
43
IN1 BY
ARINC input
Y
Receiver 1 negative input
44
IN2 AX
ARINC input
X
Receiver 2 positive input
HOLT INTEGRATED CIRCUITS
3
HI-8444, HI-8445, HI-8448
HOLT INTEGRATED CIRCUITS
4
NOTE: Stresses above absolute maximum ratings or
outside recommended operating conditions may cause
permanent damage to the device.
These are stress
ratings only. Operation at the limits is not recommended.
Supply voltage (
Logic input voltage range
Power dissipation at 25C
350 mW
Solder Temperature
275C for 10 sec
Storage Temperature
-65C to +150C
VDD)
-0.3 V to +7 V
-0.3 V to +5.5 V
ARINC input voltage
-30 V to + 30 V
Driver peak output current
+1.0 A
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Operating Temperature Range
Industrial Screening .........
-40C to +85C
Hi-Temp Screening ........
-55C to +125C
VDD .................................. 3.0 V to 5.5 V
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
ARINC INPUTS
Input voltage
ONE or ZERO
V
Differential input voltage
6.5
10
13
V
NULL
V
Differential input voltage
2.5
V
Common mode
V
With respect to GND
5.0
V
Input resistance
INA to INB
R
Supplies floating
30
75
K
Input to V
or V
R
Supplies floating
19
40
K
Input hysteresis
V
0.5
1.0
V
Input capacitance
ARINC differential
C
5
10
pF
ARINC single ended to V
C
10
pF
TEST INPUTS
Logic input voltage
High
V
2.0
V
Low
V
0.8
V
Logic input current
Sink
I
V =2.0V
200
Source
I
V =0.8V
-1.0
OUTPUTS
Logic output voltage
High
V
I
=-5mA, V
=5.0V
2.4
V
I
=-4mA, V
=3.3V
2.4
V
Low
V
I
=5mA, V
=5.0V
0.4
V
I
=4mA, V
=3.3V
0.4
V
Logic output voltage (CMOS)
High
V
I
=-100
Low
V
I
=100
SUPPLY CURRENT
V
current
I
HI-8444, HI-8445
5.5
10
mA
HI-8448
11
20.0
mA
SWITCHING CHARACTERISTICS (
Propagation delay
IN to OUT
t
C =50 pF
600
ns
t
600
ns
Output rise time
t
10% to 90%
50
80
ns
Output fall time
t
90% to 10%
50
80
ns
Propagation delay
TEST to OUT
t
50
ns
t
50
ns
DIN
NIN
COM
DIFF
SS
DD
SUP
HYS
AD
SS
AS
IH
IL
IH
IH
IL
IL
OH
OH
DD
OH
DD
OL
OL
DD
OL
DD
OHC
OH
OLC
OL
DD
DD
LH
L
HL
R
F
TOH
TOL
W
W
A
A
A
V
-0.2
V
A
V
+0.2
V
T = 25 C)
C =50 pF
DD
SS
A
L
ELECTRICAL CHARACTERISTICS
VDD = 5.0V
, V
= 0V, T = Operating Temperature Range (unless or otherwise specified).
SS
A
or
5%
3.3V 5%
HOLT INTEGRATED CIRCUITS
5
HI-8444, HI-8445, HI-8448
HI-8444PSI
20 PIN PLASTIC TSSOP
-40C TO +85C
I
None
NO
SOLDER
HI-8444PSI-10
20 PIN PLASTIC TSSOP
-40C TO +85C
I
10K
NO
SOLDER
HI-8444PST
20 PIN PLASTIC TSSOP
-55C TO +125C
T
None
NO
SOLDER
HI-8444PST-10
20 PIN PLASTIC TSSOP
-55C TO +125C
T
10K
NO
SOLDER
HI-8445PSI
20 PIN PLASTIC TSSOP
-40C TO +85C
I
None
NO
SOLDER
HI-8445PSI-10
20 PIN PLASTIC TSSOP
-40C TO +85C
I
10K
NO
SOLDER
HI-8445PST
20 PIN PLASTIC TSSOP
-55C TO +125C
T
None
NO
SOLDER
HI-8445PST-10
20 PIN PLASTIC TSSOP
-55C TO +125C
T
10K
NO
SOLDER
HI-8448PQI
44 PIN PLASTIC QUAD FLATPACK (PQFP)
-40C TO +85C
I
None
NO
SOLDER
HI-8448PQI-10
44 PIN PLASTIC QUAD FLATPACK (PQFP)
-40C TO +85C
I
10K
NO
SOLDER
HI-8448PQT
44 PIN PLASTIC QUAD FLATPACK (PQFP)
-55C TO +125C
T
None
NO
SOLDER
HI-8448PQT-10 44 PIN PLASTIC QUAD FLATPACK (PQFP)
-55C TO +125C
T
10K
NO
SOLDER
W
W
W
W
W
W
TIMING DIAGRAMS
1.5V
1.5V
t
LH
t
HL
t
LH
t
HL
IN A
IN B
OUT A
OUT B
1.5V
t
TOH
t
TOL
1.5V
TEST A
/
TEST B
OUT A
/
OUT B
ARINC 429 Receiver Timing
Test Mode Timing
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
PART
NUMBER
LEAD
FINISH
ORDERING INFORMATION
PROCESS
FLOW
BURN
IN
INTERNAL LIGHTNING PROTECTION (-10 Only)
The HI-8444-10, HI-8445-10 and HI-8488-10 are similar to the
"non -10" configurations with the exception that an external
10 Kohm resistor must be added in series with each ARINC input
in order to properly detect the ARINC 429 specified input
thresholds. This option is especially useful in applications where
external lightning protection circuitry is required.
The HI-8444-10, HI-8445-10 and HI-8448-10 will meet the
requirements of DO-160D, Level 3, waveforms 3, 4 and 5A with
the 10 Kohm series resistors in place.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightening protection of Holt
Line Drivers and Receivers.
EXTERNAL
RESISTOR
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