HI-8581

PIN CONFIGURATION

(Top View)

GENERAL DESCRIPTION

The HI-8581 device from Holt Integrated Circuits is a silicon
gate CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. The device provides
two receivers, an independent transmitter and line driver
capability in a single package. The receiver input circuitry
and logic are designed to meet the ARINC 429
specifications for loading, level detection, timing, and
protocol. The transmitter section provides the ARINC 429
communication protocol and the line driver circuits provide
the ARINC 429 output levels.

The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.

Timing of all the circuitry begins with the master clock input,
CLK.

For ARINC 429 applications, the master clock

frequency is 1 MHz.

Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8581 examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.

The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.

APPLICATIONS

Avionics data communication

Serial to parallel conversion

Parallel to serial conversion

FEATURES

ARINC specification 429 compatible
Direct receiver and transmitter interface to
ARINC bus in a single device.
16-Bit parallel data bus.
Timing control 10 times the data rate
Selectable data clocks
Receiver error rejection per ARINC

specification 429
Automatic transmitter data timing
Self test mode
Parity functions
Low power
Industrial & full military temperature ranges

June 2001

33 -
32 - N/C
31 - V+
30 - TXB(OUT)
29 - TXA(OUT)
28 - V-
27 - GND
26 - TX/R
25 -
24 -
23 -

ENTX

BD00

PL2
PL1

429DI2(B) - 1

- 2
- 3

SEL - 4

- 5
- 6

BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10

BD11 - 11

D/R1
D/R2

EN1
EN2

HI-8581PQI

HI-8581PQT

HOLT INTEGRATED CIRCUITS

(DS8581 Rev. A)

06/01

(See page 13 for additional pin configurations)

SIGNAL

FUNCTION

DESCRIPTION

POWER

+5V ±5%

BD05

I/O

Data Bus

BD04

I/O

Data Bus

BD03

I/O

Data Bus

BD02

I/O

Data Bus

TX/R

OUTPUT

Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
After transmission and FIFO empty.

V+

POWER

+9.5V to +12.6V

V-

POWER

-9.5V to -12.6V

429DI1 (A)

INPUT

ARINC receiver 1 positive input

429DI1 (B)

INPUT

ARINC receiver 1 negative input

429DI2 (A)

INPUT

ARINC receiver 2 positive input

429DI2 (B)

INPUT

ARINC receiver 2 negative input

OUTPUT

Receiver 1 data ready flag

OUTPUT

Receiver 2 data ready flag

SEL

INPUT

Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)

INPUT

Data Bus control, enables receiver 1 data to outputs

INPUT

Data Bus control, enables receiver 2 data to outputs if

is high

BD15

I/O

Data Bus

BD14

I/O

Data Bus

BD13

I/O

Data Bus

BD12

I/O

Data Bus

BD11

I/O

Data Bus

BD10

I/O

Data Bus

BD09

I/O

Data Bus

BD08

I/O

Data Bus

BD07

I/O

Data Bus

BD06

I/O

Data Bus

GND

POWER

0 V

BD01

I/O

Data Bus

BD00

I/O

Data Bus

INPUT

Latch enable for byte 1 entered from data bus to transmitter FIFO.

INPUT

Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow

TXA(OUT)

OUTPUT

Line driver output - A side

TXB(OUT)

OUTPUT

Line driver output - B side

ENTX

INPUT

Enable Transmission

INPUT

Clock for control word register

CLK

INPUT

Master Clock input

TX CLK

OUTPUT

Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.

INPUT

Master Reset, active low

D/R1
D/R2

EN1
EN2

EN1

PL1
PL2

PL1

CWSTR

HI-8581

HOLT INTEGRATED CIRCUITS

FUNCTIONAL DESCRIPTION

DATA

BUS

FUNCTION CONTROL

DESCRIPTION

PIN

If enabled, an internal connection

BDO5

SELF TEST

0 = ENABLE

is made passing 429DO and

to the receiver logic inputs

RECEIVER 1

If enabled, ARINC bits 9 and,

BDO6

DECODER

1 = ENABLE

10 must match the next two

control word bits

If Receiver 1 Decoder is

BDO7

enabled, the ARINC bit 9

must match this bit

If Receiver 1 Decoder is

BDO8

enabled, the ARINC bit 10

must match this bit

RECEIVER 2

If enabled, ARINC bits 9 and

BDO9

DECODER

1 = ENABLE

10 must match the next two

control word bits

If Receiver 2 Decoder is

BD10

enabled, then ARINC bit 9

must match this bit

If Receiver 2 Decoder is

BD11

enabled, then ARINC bit 10

must match this bit

INVERT

Logic 0 enables normal odd parity

BD12

XMTR

1 = ENABLE

and Logic 1 enables even parity

PARITY

output in transmitter 32nd bit

BD13

XMTR DATA

0 = ÷10

CLK is divided either by 10 or

CLK SELECT

1 = ÷80

80 to obtain XMTR data clock

BD14

RCVR DTA

0 = ÷10

CLK is divided either by 10 or

CLK SELECT

1 = ÷80

80 to obtain RCVR data clock

429DO

CONTROL WORD REGISTER

The HI-8581 contains 10 data flip flops whose D inputs are con-

nected to the data bus and clocks connected to

. Each

flip flop provides options to the user as follows:

CWSTR

THE RECEIVERS

ARINC BUS INTERFACE

Figure 1 shows the input circuit for each receiver. The ARINC 429

specification requires the following detection levels:

The HI-8581 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13V signal level).

The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the

nulls, the chip rejects the data.

STATE

DIFFERENTIAL VOLTAGE

ONE

+6.5 Volts to +13 Volts

NULL

+2.5 Volts to -2.5 Volts

ZERO

-6.5 Volts to -13 Volts

BYTE 2

DATA

BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD

BUS

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

ARINC

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14

BIT

ARINC 429 DATA FORMAT

The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.

DATA

BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD

BUS

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

ARINC

13 12 11 10

31 30 32

BIT

BYTE 1

HI-8581

HOLT INTEGRATED CIRCUITS

RECEIVER LOGIC OPERATION

BIT TIMING

BIT RATE

PULSE RISE TIME

PULSE FALL TIME

PULSEWIDTH

Figure 2 shows a block diagram of the logic section of each receiver.

The ARINC 429 specification contains the following timing
specification for the received data:

100K BPS ± 1% 12K -14.5K BPS

1.5 ± 0.5 µsec

10 ± 5 µsec

1.5 ± 0.5 µsec

10 ± 5 µsec

5 µsec ± 5%

34.5 to 41.7 µsec

Again the HI-8581 accepts signals that meet these specifications

and rejects outside the tolerances. The way the logic operation
achieves this is described below:

1. Key to the performance of the timing checking logic is an ac-

curate 1MHz clock source. Less than 0.1% error is recom-
mended.

2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid

data. Additionally, for data bits, the One or Zero in the upper bits
of the sampling shift registers must be followed by a Null in the
lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the mini-

mum pulse width is guaranteed.

HIGH SPEED

LOW SPEED

FUNCTIONAL DESCRIPTION (con't)

3. Each data bit must follow its predecessor by not less than

8 samples and no more than 12 samples. In this manner the

bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:

83K BPS

10.4K BPS

125K BPS

15.6K BPS

4. TheWordGaptimersamplestheNullshiftregister every
10 input clocks (80 for low speed) after the last data bit of a

Valid reception. If the Null is present, theWordGapcounter
Is incremented. A count of 3 will enable the next reception.

The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.

HIGH SPEED

LOW SPEED

DATA BIT RATE MIN

DATA BIT RATE MAX

RECEIVER PARITY

RETRIEVING DATA

Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1",

(or both) will go low. The

data flag for a receiver will remain low until after

ARINC bytes

from that receiver are retrieved. This is accomplished by first
activating

with SEL, the byte selector, low to retrieve the first

byte and then activating

with SEL high to retrieve the second

byte.

retrieves data from receiver 1 and

retrieves data

from receiver 2.

If another ARINC word is received, and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new

word.

D/R1

D/R2

ENI

EN2

both

SEL

D/R

DECODER

CONTROL

BITS

MUX

CONTROL

LATCH

ENABLE

CONTROL

32 TO 16 DRIVER

32 BIT LATCH

32 BIT SHIFT REGISTER

TO PINS

CONTROL

BIT BD14

CLOCK

OPTION

CLOCK

CLK

BIT

COUNTER

AND

END OF

SEQUENCE

PARITY

CHECK

32ND

BIT

DATA

BIT CLOCK

EOS

WORD GAP

WORD GAP

TIMER

BIT CLOCK

END

START

SEQUENCE

CONTROL

ERROR

CLOCK

ERROR

DETECTION

SHIFT REGISTER

NULL

ZEROS

SHIFT REGISTER

ONES

EOS

BITS 9 & 10

FIGURE 2.

RECEIVER BLOCK DIAGRAM

HI-8581

HOLT INTEGRATED CIRCUITS

TRANSMITTER

A block diagram of the transmitter section is shown in Figure 3.

The FIFO is loaded sequentially by first pulsing

to load byte 1

and then

to load byte 2. The control logic automatically loads

the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the

available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.

When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or

. The 31 bits in the

data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:

ARINC DATA BIT TIME

10 Clocks

80 Clocks

DATA BIT TIME

5 Clocks

40 Clocks

NULL BIT TIME

5 Clocks

40 Clocks

WORD GAP TIME

40 Clocks

320 Clocks

The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.

FIFO OPERATION

DATA TRANSMISSION

PL1

PL2

429DO

HIGH SPEED

LOW SPEED

TRANSMITTER PARITY

The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.

If the BD05 control word bit is set low, 429DO or

become

inputs to the receiver bypassing the interface circuitry.

The two receivers are independent of the transmitter. Therefore,

control of data exchanges is strictly at the option of the user. The
only restrictions are:

1. The received data may be overwritten if not retrieved
within one ARINC word cycle.

2. The FIFO can store 8 words maximum and ignores

attempts to load addition data if full.

3. Byte 1 of the transmitter data must be loaded first.

4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.

5. After ENTX, transmission enable, goes high it cannot go

low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.

SELF TEST

SYSTEM OPERATION

429DO

HI-8581

HOLT INTEGRATED CIRCUITS

REPEATER OPERATION

Repeater mode of operation allows a data word that has been
received by the HI-8581 to be placed directly into its FIFO for
transmission. Repeater operation is similar to normal receiver

operation. In normal operation, either byte of a received data
word may be read from the receiver latches first by use of SEL
input. During repeater operation however, the lower byte of the
data word must be read first. This is necessary because, as the
data is being read, it is also being loaded into the FIFO and the

transmitter FIFO is always loaded with the lower byte of the data
word first. Signal flow for repeater operation is shown in the
Timing Diagrams section.

LINE DRIVER OPERATION

The line driver in the HI-8581 is designed to directly drive the ARINC
429 bus. The two ARINC outputs (TXA(OUT) and TXB(OUT))
provide a differential voltage to produce a +10 volt One, a -10 volt

Zero, and a 0 volt Null. Setting Control Register bit 13 to zero
causes a slope of 1.5 s on the ARINC outputs; a one in Control
Register bit 13 causes a slope of 10 s. Timing is set by on-chip
resistor and capacitor and tested to be within ARINC requirements.

The HI-8581

has 37.5 ohms in series with each line driver output.

No additional hardware is required to control the slope.

TXA(OUT)

ARINC BIT

TXB(OUT)

NULL

DATA

NULL

WORD GAP

BIT 1

NEXT WORD

BIT 32

BIT 31

BIT 30

CWHLD

CWSET

CWSTR

DATA BUS

CWSTR

VALID

DATA BUS

SELEN

D/R

ENSEL

DATAEN

D/REN

END/R

ENSEL

SELEN

DATAEN

ENDATA

ENEN

HI-8581

HOLT INTEGRATED CIRCUITS

LIMITS

PARAMETER

CONDITIONS

UNIT

SYMBOL

Differential Input Voltage:

ONE

Pins 4 to 5, 6 to 7: Common

6.5

10.0

13.0

ZERO

mode voltage less than ±4V

-13.0

-10.0

-6.5

NULL

with respect to GND

-2.5

2.5

Input Resistance:

Differential

To GND

To Vcc

Input Current:

Input Sink

200

µA

Input Source

-450

µA

Input Capacitance:

Differential

Pins 4 to 5, 6 to 7

(Guaranteed but not tested)

To GND

To Vcc

Input Voltage:

Input Voltage HI

2.1

Input Voltage LO

0.7

Input Current:

Input Sink

1.5

µA

Input Source

-1.5

µA

Input Voltage:

Input Voltage HI

3.5

Input Voltage LO

0.7

Input Current:

Input Sink

µA

Input Source

-20

MIN

TYP

MAX

ARINC INPUTS

BI-DIRECTIONAL INPUTS

OTHER INPUTS

NUL

G
H

Vcc = 5V ±5%,

GND = 0V, TA = Operating Temperature Range (unless otherwise specified).

V+ = 10V , V- = -10V,

Power Dissipation at 25C

Plastic PLCC/PQFP

1.5 W, derate 10mW/ C

Ceramic J-LEAD CERQUAD

1.0 W, derate 7mW/

DC Current Drain per pin

±10mA

Operating Temperature Range:

(Industrial)

-40°C to +85°C

(Military)

-55°C to +125°C

°C

Storage Temperature Range:

-65°C to +150°C

Supply Voltages Vcc

-0.3V to +7V

V+

+13.0V

V-

-13.0V

Voltage at pins ARINC inputs

-29V to +29V

Voltage at any other pin

-0.3V to Vcc +0.3V

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

HI-8581

HOLT INTEGRATED CIRCUITS

LIMITS

PARAMETER

CONDITIONS

UNIT

SYMBOL

Output Voltage:

Logic "1" Output Voltage

= -1.5mA

2.7

Logic "0" Output Voltage

= 2.6mA

0.4

Output Current:

Output Sink

= 0.4V

3.0

(Bi-directional Pins)

Output Source

= V

- 0.4V

1.1

Output Current:

Output Sink

= 0.4V

2.6

(All Other Outputs)

Output Source

= V

- 0.4V

1.1

Output Capacitance:

4.75

5.25

V+

9.5

12.6

V-

-9.5

-12.6

MIN

TYP

MAX

ARINC OUTPUTS

OTHER OUTPUTS

Operating Voltage Range

Operating Supply Current

OUT

CC1

ARINC output voltage

One or zero

no load and magnitude at pin

4.50

5.00

5.50

Null

-0.25

0.25

ARINC output current

V+

V-

DOUT
NOUT

OUT

DD1

EE1

Vcc = 5V ±5%, V+ = 10V, V- = -10V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).

HI-8581

HOLT INTEGRATED CIRCUITS

LIMITS

PARAMETER

SYMBOL

UNITS

MIN

TYP

MAX

CONTROL WORD TIMING

RECEIVER TIMING

FIFO TIMING

TRANSMISSION TIMING

LINE DRIVER OUTPUT TIMING

Pulse Width -

Setup - DATA BUS Valid to

HIGH

Hold -

HIGH to DATA BUS Hi-Z

Delay - Start ARINC 32nd Bit to

LOW: High Speed

µs

Low Speed

128

µs

Delay -

LOW to

L0W

Delay -

LOW to

HIGH

200

Setup - SEL to

L0W

Hold - SEL to

HIGH

Delay -

L0W to DATA BUS Valid

Delay -

HIGH to DATA BUS Hi-Z

Pulse Width -

Spacing -

HIGH to next

L0W

Pulse Width -

Setup - DATA BUS Valid to

HIGH

Hold -

HIGH to DATA BUS Hi-Z

Spacing -

Delay -

HIGH to TX/R LOW

840

Spacing -

HIGH to ENTX HIGH

µs

Delay - 32nd ARINC Bit to TX/R HIGH

Spacing - TX/R HIGH to ENTX L0W

Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed

Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed

200

Line driver transition differential times:

high to low

1.0

1.5

2.0

low to high

1.0

1.5

2.0

CWSTR

D/R

EN1

EN2

PL1

PL2

PL1

PL2

CWSTR
CWSET
CWHLD

D/R
D/R

D/REN
END/R

SELEN
ENSEL

ENDATA
DATAEN

ENEN

DWSET
DWHLD

PL12

TX/R

PL2EN

DTX/R

ENTX/R

ENDAT

fx
rx

µs
µs

(High Speed)

µs
µs

(Low Speed)

high to low

5.0

µs

low to high

5.0

µs

fx
rx

Vcc = 5V, V+=10V, V- = -10V, GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz 0.1% with 60/40 duty cycle

HI-8581

HOLT INTEGRATED CIRCUITS

HI-8581 PACKAGE DIMENSIONS

inches (millimeters)

ACKAGE YPE

Package Type:

HOLT INTEGRATED CIRCUITS

.620

.012

(15.748

.305)

.688

.005

(17.475

.127)

MAX.

SQ.

.650

.010

(16.510

.254)

SQ.

.050

(1.270)

.019

.002

(.483

.051)

44-PIN CERQUAD J-LEAD

PIN NO. 1 IDENT

.045 x 45°

.050

.005

(1.27

.127)

.045 x 45°

PIN NO. 1

44-PIN PLASTIC J-LEAD PLCC

SEE DETAIL

.172

.008

(4.369

.203)

DETAIL A

.020 MIN

(.508

)

.025
.045

.690

.005

(17.526

.127)

SQ.

.610

.020

(15.494

.508)

.031

.005

(.787

.127)

.653

.004

(16.586

.102)

SQ.

.017

.004

(.432

.102)

.015 ± .002

(.381

.051)

.009
.011

.039

.005

(.990

.127)

TYP.

.100

.007

(2.540

.178)

.200

(5.080) MAX.

2 1 44 43

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