HI-8584

Enhanced ARINC 429

Serial Transmitter and Dual Receiver

PIN CONFIGURATION

(Top View)

52 - Pin Plastic Quad Flat Pack (PQFP)

(See page 13 for additional pin configuration)

HI-8584PQI

HI-8584PQT

RIN2B

RIN2A

RIN1B

RIN1A

VDD

N/C

TXCLK

CLK

N/C

D/R1

RSR

39 - N/C
38 -
37 - ENTX
36 - N/C
35 -
34 - 429DO
33 - N/C
32 -
31 -
30 - TX/R
29 -
28 -
27 - BD00

CWSTR

FFT
HFT

PL2
PL1

429DO

BD10

BD09

BD08

-1

BD07

-1

BD06

-1

N/C

-1

VSS

-2

BD05

-2

BD04

-2

BD03

BD02

-2

BD01

-2

NFD

FF1

HF1

D/R2

FF2

HF2

EN1
EN2

- 1
- 2
- 3
- 4
- 5

SEL - 6

- 7
- 8

BD15 - 9
BD14 - 10

BD13 - 11

BD12 - 12

BD11 - 13

GENERAL DESCRIPTION

The HI-8584 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-8584 design offers many
enhancements to the industry standard HI-8282
architecture. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-8584's status
register.

Other new features include a programmable option of data
or parity in the 32nd bit, and the ability to unscramble the 32
bit word. Also, versions are available with different values
of input resistance to allow users to more easily add
external lightning protection circuitry. The device can be
used at nonstandard data rates when an option pin,

, is

invoked.

The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.

The HI-8584 applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.

NFD

Additional interface circuitry such as the Holt HI-8585,
HI-8586 or HI-3182 is required to translate the transmit-
ter's 5 volt logic outputs to ARINC 429 drive levels.

APPLICATIONS

Avionics data communication

Serial to parallel conversion

Parallel to serial conversion

FEATURES

!
!

!
!
!
!
!
!

ARINC specification 429 compatible

Dual receiver and transmitter interface

Programmable label recognition

32 x 32 FIFOs each receiver and transmitter

Status register

Data scramble control

32nd transmit bit can be data or parity

Self test mode

Low power

Industrial & full military temperature ranges

Analog line receivers connect directly to

ARINC bus

On-chip 16 label memory for each receiver

Independent data rate selection for
transmitter and each receiver

HOLT INTEGRATED CIRCUITS

www.holtic.com

(DS8584 Rev. A)

02/03

February 2003

SIGNAL

FUNCTION

DESCRIPTION

VDD

POWER

+5V � %

BD05

I/O

Data Bus

BD04

I/O

Data Bus

BD03

I/O

Data Bus

BD02

I/O

Data Bus

RIN1A

INPUT

ARINC receiver 1 positive input

RIN1B

INPUT

ARINC receiver 1 negative input

RIN2A

INPUT

ARINC receiver 2 positive input

RIN2B

INPUT

ARINC receiver 2 negative input

OUTPUT

Receiver 1 data ready flag

OUTPUT

FIFO full Receiver 1

OUTPUT

FIFO Half full, Receiver 1

OUTPUT

Receiver 2 data ready flag

OUTPUT

FIFO full Receiver 2

OUTPUT

FIFO Half full, Receiver 2

SEL

INPUT

Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)

INPUT

Data Bus control, enables receiver 1 data to outputs

INPUT

Data Bus control, enables receiver 2 data to outputs if

is high

BD15

I/O

Data Bus

BD14

I/O

Data Bus

BD13

I/O

Data Bus

BD12

I/O

Data Bus

BD11

I/O

Data Bus

BD10

I/O

Data Bus

BD09

I/O

Data Bus

BD08

I/O

Data Bus

BD07

I/O

Data Bus

BD06

I/O

Data Bus

GND

POWER

0 V

BD01

I/O

Data Bus

BD00

I/O

Data Bus

INPUT

Latch enable for byte 1 entered from data bus to transmitter FIFO.

INPUT

Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow

TX/R

OUTPUT

Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high

after transmission and FIFO empty.

OUTPUT

Transmitter FIFO Half Full

OUTPUT

Transmitter FIFO Full

429DO

OUTPUT

"ONES" data output from transmitter

OUTPUT

"ZEROS" data output from transmitter

ENTX

INPUT

Enable Transmission

INPUT

Clock for control word register

INPUT

Read Status Register if SEL=0, read Control Register if SEL=1

INPUT

No frequency discrimination if low (pull-up)

CLK

INPUT

Master Clock input

TX CLK

OUTPUT

Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.

INPUT

Master Reset, active low

D/R1

FF1

HF1

D/R2

FF2

HF2

EN1
EN2

EN1

PL1
PL2

PL1.

HFT

FFT

429DO

CWSTR

RSR
NFD

PIN DESCRIPTIONS

HOLT INTEGRATED CIRCUITS

HI-8584

Bit

FUNCTION

STATE

DESCRIPTION

SR0

Data ready

Receiver 1 FIFO empty

Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read.

pin is the inverse of

this bit

(Receiver 1)

SR1

FIFO half full

Receiver 1 FIFO holds less than 16

(Receiver 1)

words

Receiver 1 FIFO holds at least 16
words.

pin is the inverse of

this bit.

SR2

FIFO full

Receiver 1 FIFO not full

(Receiver 1)

Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period.

pin is

the inverse of this bit

SR3

Data ready

Receiver 2 FIFO empty

(Receiver 2)

Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read.

pin is the inverse of

this bit

SR4

FIFO half full

Receiver 2 FIFO holds less than 16

(Receiver 2)

words

Receiver 2 FIFO holds at least 16
words.

pin is the inverse of

this bit.

SR5

FIFO full

Receiver 2 FIFO not full

(Receiver 2)

Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period.

pin is

the inverse of this bit

SR6

Transmitter FIFO

Transmitter FIFO not empty

empty

Transmitter FIFO empty.

SR7

Transmitter FIFO

Transmitter FIFO not full

full

Transmitter FIFO full.

pin is the

inverse of this bit.

SR8

Transmitter FIFO

Transmitter FIFO contains less than

half full

16 words

Transmitter FIFO contains at least
16 words.

pin is the

inverse of this bit.

D/R1

HF1

FF1

D/R2

HF2

FF2

FFT

HFT

FUNCTIONAL DESCRIPTION

CONTROL WORD REGISTER

The HI-8584 contains a 16-bit control register which is used to con-
figure the device. The control register bits CR0 - CR15 are loaded
from BD00 - BD15 when

is pulsed low. The control regis-

ter contents are output on the databus when SEL = 1 and

pulsed low. Each bit of the control register has the following func-
tion:

CWSTR

RSR

STATUS REGISTER

The HI-8584 contains a 9-bit status register which can be interro-
gated to determine the status of the ARINC receivers, data FIFOs
and transmitter. The contents of the status register are output on
BD00 - BD08 when the

pin is taken low and SEL = 0. Unused

bits are output as zeros. The following table defines the status reg-
ister bits.

RSR

HOLT INTEGRATED CIRCUITS

HI-8584

Bit

FUNCTION

STATE

DESCRIPTION

CR0

Receiver 1

Data rate = CLK/10

Select

Data rate = CLK/80

Data clock

CR1

Label Memory

Normal operation

Read / Write

Load 16 labels using

Read 16 labels using

CR2

Enable Label

Disable label recognition

Recognition

(Receiver 1)

Enable label recognition

CR3

Enable Label

Disable Label Recognition

Recognition

(Receiver 2)

Enable Label recognition

CR4

Enable

Transmitter 32nd bit is data

32nd bit

as parity

Transmitter 32nd bit is parity

CR5

Self Test

The 429DO and

digital

outputs are internally connected

to the receiver logic inputs

Normal operation

CR6

Receiver 1

Receiver 1 decoder disabled

decoder

ARINC bits 9 and 10 must match

CR7 and CR8

CR7

If receiver 1 decoder is enabled,

the ARINC bit 9 must match this bit

CR8

If receiver 1 decoder is enabled,

the ARINC bit 10 must match this bit

CR9

Receiver 2

Receiver 2 decoder disabled

Decoder

ARINC bits 9 and 10 must match

CR10 and CR11

CR10

If receiver 2 decoder is enabled,

the ARINC bit 9 must match this bit

CR11

If receiver 2 decoder is enabled,

the ARINC bit 10 must match this bit

CR12

Invert

Transmitter 32nd bit is Odd parity

Transmitter

parity

Transmitter 32nd bit is Even parity

CR13

Transmitter

Data rate=CLK/10, O/P slope=1.5us

data clock

select

Data rate=CLK/80, O/P slope=10us

CR14

Receiver 2

Data rate=CLK/10

data clock

select

Data rate=CLK/80

CR15

Data

Scramble ARINC data

format

Unscramble ARINC data

PL1 PL2

EN1 EN2

429DO

GND

RIN1B

RIN2B

RIN1A

RIN2A

DIFFERENTIAL

AMPLIFIERS

ONES

COMPARATORS

NULL

ZEROES

FIGURE 1. ARINC RECEIVER INPUT

The HI-8584 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than �4 for the worst case
condition (4.75V supply and 13V signal level).

The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.

RECEIVER LOGIC OPERATION

BIT TIMING

BIT RATE

PULSE RISE TIME

PULSE FALL TIME

PULSE WIDTH

Figure 2 shows a block diagram of the logic section of each receiver.

The ARINC 429 specification contains the following timing specifi-
cation for the received data:

100K BPS � 1% 12K -14.5K BPS

1.5 � 0.5 �sec

10 � 5 �sec

1.5 � 0.5 �sec

10 � 5 �sec

5 �sec � 5%

34.5 to 41.7 �sec

If the

pin is high, the HI-8584 accepts signals that meet these

specifications and rejects outside the tolerances.

The way the

logic operation achieves this is described below:

HIGH SPEED

LOW SPEED

NFD

3. Each data bit must follow its predecessor by not less than

8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:

83K BPS

10.4K BPS

125K BPS

15.6K BPS

4. The Word Gap timer samples the Null shift register every

10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.

is held low, frequency discrimination is disabled and any

data stream totaling 32 bits is accepted even with gaps between
bits. The protocol still requires a word gap as defined in 4. above.

HIGH SPEED

LOW SPEED

DATA BIT RATE MIN

DATA BIT RATE MAX

NFD

FUNCTIONAL DESCRIPTION (cont.)

THE RECEIVERS

ARINC BUS INTERFACE

Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:

ONE

+6.5 Volts to +13 Volts

NULL

+2.5 Volts to -2.5 Volts

ZERO

-6.5 Volts to -13 Volts

STATE

DIFFERENTIAL VOLTAGE

1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.

2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
by a Null in the lower bits within the data bit time. For a Null in
the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register.

In this

manner the minimum pulse width is guaranteed.

HOLT INTEGRATED CIRCUITS

HI-8584

ARINC 429 DATA FORMAT

Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-8584
data bus during data read or write operations. The following table
describes this mapping:

DATA

BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD

BUS

ARINC

BIT

CR15=0

BYTE 1

ARINC

BIT

CR15=1

BYTE 2

DATA

BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD

BUS

ARINC

BIT

CR15=0

ARINC

BIT

CR15=1

Parity

SDI

Label

SDI

Label

Parity

FIFO

LOAD

CONTROL

SEL

CONTROL

BIT

R/W

CONTROL

32 TO 16 DRIVER

32 BIT SHIFT REGISTER

TO PINS

CONTROLBITS

CR0, CR14

CLOCK

OPTION

CLOCK

CLK

BIT

COUNTER

AND

END OF

SEQUENCE

PARITY

CHECK

32ND

BIT

DATA

BIT CLOCK

WORD GAP

WORD GAP

TIMER

BIT CLOCK

END

START

SEQUENCE

CONTROL

ERROR

CLOCK

ERROR

DETECTION

SHIFT REGISTER

NULL

ZEROS

SHIFT REGISTER

ONES

EOS

FIGURE 2.

RECEIVER BLOCK DIAGRAM

LABEL /

DECODE

COMPARE

16 x 8

LABEL

MEMORY

32 X 32

FIFO

D/R

MUX

CONTRO

CONTROL

BITS

FUNCTIONAL DESCRIPTION (cont.)

Load FIFO

Ignore data

Yes

Load FIFO

Ignore data

Yes

Load FIFO

Yes

Ignore data

Yes

Ignore data

Yes

Load FIFO

CR2(3) ARINC word CR6(9) ARINC word

FIFO

matches

bits 9,10

label

match

CR7,8 (10,11)

RECEIVER PARITY

The receiver parity circuit counts Ones received, including the
parity bit. If the result is odd, then "0" will appear in the 32nd bit.

RETRIEVING DATA

Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.

HOLT INTEGRATED CIRCUITS

HI-8584

FUNCTIONAL DESCRIPTION (cont.)

READING LABELS

After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (

taken low) are labels.

used to read labels for receiver 1, and

to read labels for

receiver 2. Label data is presented on BD00 - BD07.

When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.

EN1

EN2

TRANSMITTER

FIFO OPERATION

The FIFO is loaded sequentially by first pulsing

to load byte 1

and then

to load byte 2. The control logic automatically loads

the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
be loaded. If TX/R is low, then only the available positions may be
loaded. If all 32 positions are full, the

flag is asserted and the

FIFO ignores further attempts to load data.

A transmitter FIFO half-full flag

is provided. When the

transmit FIFO contains less than 16 words,

is high,

indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.

In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If CR4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are treated
as data and are transmitted.

PL1

PL2

FFT

HFT

CR4,12

FIGURE 3.

TRANSMITTER BLOCK DIAGRAM

DATA

CLOCK

CR13

PL1
PL2

CLK

TX CLK

PARITY

GENERATOR

DATA AND

NULL TIMER

SEQUENCER

BIT

AND

WORD GAP

COUNTER

START

SEQUENCE

WORD COUNTER

AND

FIFO CONTROL

INCREMENT

WORD COUNT

DATA CLOCK

DIVIDER

FIFO

LOADING

SEQUENCER

429DO
429DO

32 x 32 FIFO

32 BIT PARALLEL

LOAD SHIFT REGISTER

BIT CLOCK

WORD CLOCK

ADDRESS

LOAD

DATA BUS

TX/R

ENTX

The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00-BD07 are
always compared to received ARINC bits 1 -8 respectively.

After a write that takes CR1 from 0 to 1, the next 16 writes of data

(

pulsed low) load label data into each location of the label

memory from the BD00 - BD07 pins. The

pin is used to write

label data for receiver 1 and

for receiver 2.

LOADING LABELS

PL1

PL2

Note that ARINC

word reception is suspended during the label memory write
sequence.

Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1",

(or both)

will go low. The data flag for a receiver will remain low until
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating

with SEL, the

byte selector, low to retrieve the first byte and then activating
with SEL high to retrieve the second byte.

retrieves data

from receiver 1 and

retrieves data from receiver 2.

Up to 32 ARINC words may be loaded into each receiver's FIFO.
The

(

) pin will go low when the receiver 1 (2) FIFO is full.

Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag

(

) goes low if the FIFO

contains 16 or more received ARINC words. The

(

) pin is

intended to act as an interrupt flag to the system's external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the HI-
8584's status register bits.

D/R1

D/R2

EN1

EN2

FF1 FF2

HF1 HF2

both

LABEL RECOGNITION

HOLT INTEGRATED CIRCUITS

HI-8584

HFT
FFT

The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, TX/R, high.

TRANSMITTER PARITY

SELF TEST

SYSTEM OPERATION

The parity generator counts the Ones in the 31-bit word.

control register bit CR12 is set low, the 32nd bit transmitted will
make parity odd. If the control bit is, high the parity is even.
Setting CR4 to a Zero bypasses the parity generator, and allows
32 bits of data to be transmitted.

If control register bit CR5 is set low, the transmitter serial output
data are internally connected to each of the two receivers,
bypassing the analog interface circuitry. Data is passed
unmodified to receiver 1 and inverted to receiver 2. The serial
data from the transmitter is always present on the 429DO and

outputs regardless of the state of CR5.

The two receivers are independent of the transmitter. There-
fore, control of data exchanges is strictly at the option of the
user. The only restrictions are:

1. The received data will be overwritten if the receiver
FIFO is full and at least one location is not retrieved before
the next complete ARINC word is received.

2. The transmitter FIFO can store 32 words maximum and

ignores attempts to load additional data if full.

429DO

REPEATER OPERATION

Repeater mode of operation allows a data word that has been
received by the HI-8584 to be placed directly into the transmitter
FIFO. Repeater operation is similar to normal receiver operation.
In normal operation, either byte of a received data word may be
read from the receiver latches first by use of SEL input. During
repeater operation however, the lower byte of the data word must
be read first. This is necessary because, as the data is being read,
it is also being loaded into transmitter FIFO which is always loaded
with the lower byte of the data word first. Signal flow for repeater
operation is shown in the Timing Diagrams section.

Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.

HI-8584-10

The HI-8584-10 option is similar to the HI-8584 with the exception
that it allows an external 10 Kohm resistor to be added in series
with each ARINC input without affecting the ARINC input thresh-
olds. This option is especially useful in applications where light-
ning protection circuitry is also required.

Each side of the ARINC bus must be connected through a 10 Kohm
series resistor in order for the chip to detect the correct ARINC
levels. The typical 10 volt differential signal is translated and input
to a window comparator and latch. The comparator levels are set
so that with the external 10 Kohm resistors, they are just below the
standard 6.5 volt minimum ARINC data threshold and just above
the standard 2.5 volt maximum ARINC null threshold.

The HI-8584 may be operated at clock frequencies beyond that re-
quired for ARINC compliant operation. For operation at Master
Clock (CLK) frequencies up to 5MHz, please contact Holt applica-
tions engineering.

HIGH SPEED OPERATION

FUNCTIONAL DESCRIPTION (cont.)

DATA TRANSMISSION

When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at 429DO and

. The 31 or 32 bits in the

data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:

429DO

ARINC DATA BIT TIME

10 Clocks

80 Clocks

DATA BIT TIME

5 Clocks

40 Clocks

NULL BIT TIME

5 Clocks

40 Clocks

WORD GAP TIME

40 Clocks

320 Clocks

HIGH SPEED

LOW SPEED

HOLT INTEGRATED CIRCUITS

HI-8584

DATA RATE - EXAMPLE PATTERN

429 DATA

ARINC BIT

429 DATA

NULL

DATA

NULL

WORD GAP

BIT 1

NEXT WORD

BIT 32

BIT 31

BIT 30

TRANSMITTER OPERATION

PL2

DWSET

DWHLD

TX/R

DWHLD

PL12

DATA BUS

PL1

TX/R,

HFT FFT

BYTE 2 VALID

PL12

DWSET

BYTE 1 VALID

SELEN

ENSEL

SELEN

BYTE 1

DATAEN

ENDATA

READEN

RECEIVER OPERATION

D/R HF FF

ARINC DATA

SEL

DATA BUS

BIT 31

BIT 32

SELEN

D/R

DATAEN

D/REN

END/R

ENSEL

ENDATA

ENEN

DON'T CARE

BYTE 1 VALID

BYTE 2 VALID

LOADING CONTROL WORD

CWHLD

CWSET

CWSTR

DATA BUS

CWSTR

VALID

TIMING DIAGRAMS

HOLT INTEGRATED CIRCUITS

HI-8584

LIMITS

PARAMETER

CONDITIONS

UNIT

SYMBOL

Differential Input Voltage:

ONE

Common mode voltage

6.5

10.0

13.0

(RIN1A to RIN1B, RIN2A to RIN2B)

ZERO

less than �4V with

-13.0

-10.0

-6.5

NULL

with respect to GND

-2.5

2.5

Input Resistance:

Differential

To GND

To V

Input Current:

Input Sink

200

�A

Input Source

-450

�A

Input Capacitance:

Differential

(Guaranteed but not tested)

To GND

To V

Input Voltage:

Input Voltage HI

2.0

Input Voltage LO

0.8

Input Current:

Input Sink

1.5

�A

Input Source

-1.5

�A

Input Voltage:

Input Voltage HI

2.0

Input Voltage LO

0.8

Input Current:

Input Sink

1.5

�A

Input Source

-1.5

Pull-up current (

Pin)

-150

-50

MIN

TYP

MAX

ARINC INPUTS

Pins RIN1A, RIN1B, RIN2A, RIN2B

BI-DIRECTIONAL INPUTS - Pins BD00 - BD15

OTHER INPUTS

NUL

NFD

(RIN1A to RIN1B, RIN2A to RIN2B)

�
�A

Output Voltage:

Logic "1" Output Voltage

= -1.0mA

2.7

Logic "0" Output Voltage

= 1.6mA

0.4

Output Current:

Output Sink

= 0.4V

1.6

(Bi-directional Pins)

Output Source

= V

- 0.4V

-1.0

Output Current:

Output Sink

= 0.4V

1.6

(All Other Outputs)

Output Source

= V

- 0.4V

-1.0

Output Capacitance:

VDD

OUTPUTS

Operating Supply Current

OUT

Supply Voltages V

........................................... -0.3V to +7V

Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ..... -29V to +29V

Voltage at any other pin ............................... -0.3V to V

+0.3V

Solder temperature (Leads) .................... 280

for 10 seconds

(Package) .......................................... 220

�C

Power Dissipation at 25�C .......................................... 500 mW

DC Current Drain per pin .............................................. �10mA

Operating Temperature Range (Industrial): .... -40�C to +85�C

(Military): ..... -55�C to +125�C

Storage Temperature Range ........................ -65�C to +150�C

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

= 5V , GND = 0V, TA = Operating Temperature Range (unless otherwise specified).

HOLT INTEGRATED CIRCUITS

HI-8584

AC ELECTRICAL CHARACTERISTICS

VDD = 5V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz 0.1% with 60/40 duty cycle

LIMITS

PARAMETER

SYMBOL

UNITS

MIN

TYP

MAX

CONTROL WORD TIMING

RECEIVER FIFO AND LABEL READ TIMING

TRANSMITTER FIFO AND LABEL WRITE TIMING

TRANSMISSION TIMING

Pulse Width -

Setup - DATA BUS Valid to

HIGH

Hold -

HIGH to DATA BUS Hi-Z

Delay - Start ARINC 32nd Bit to

LOW: High Speed

�s

Low Speed

128

�s

Delay -

LOW to

LOW

Delay -

LOW to

HIGH

250

350

Setup - SEL to

LOW

Hold - SEL to

HIGH

Delay -

LOW to DATA BUS Valid

100

Delay -

HIGH to DATA BUS Hi-Z

Pulse Width -

Spacing -

HIGH to next

LOW (Same ARINC Word)

Spacing -

HIGH to next

LOW (Next ARINC Word)

200

Pulse Width -

Setup - DATA BUS Valid to

HIGH

Hold -

HIGH to DATA BUS Hi-Z

Spacing -

Spacing between Label Write pulses

200

Delay -

HIGH to TX/R LOW

300

Spacing -

HIGH to ENTX HIGH

�s

Delay - 32nd ARINC Bit to TX/R HIGH

Spacing - TX/R HIGH to ENTX LOW

CWSTR

D/R

EN1

EN2

PL1

PL2

PL1

PL2

CWSTR

CWSET

CWHLD

D/R

D/REN

END/R

SELEN

ENSEL

ENDATA

DATAEN

ENEN

READEN

DWSET

DWHLD

PL12

LABEL

TX/R

PL2EN

DTX/R

ENTX/R

HOLT INTEGRATED CIRCUITS

HI-8584

REPEATER OPERATION TIMING

Hold -

HIGH to

HIGH

Delay - TX/R LOW to ENTX HIGH

� 1%

PLEN

TX/REN

MASTER RESET PULSE WIDTH

ARINC DATA RATE AND BIT TIMING

Delay -

LOW to

LOW

ENPL

ORDERING INFORMATION

HI-8584

ADDITIONAL HI-8584 PIN CONFIGURATION

HOLT INTEGRATED CIRCUITS

PACKAGE
DESCRIPTION

TEMPERATURE
RANGE

LEAD

FINISH

SOLDER

52 PIN PLASTIC QUAD FLAT PACK (PQFP)

52 PIN CERQUAD J LEAD

FLOW

BURN

-40�C TO +85�C

-55�C TO +125�C

HI - 8584 xx x - xx

INPUT SERIES RESISTANCE

BUILT-IN

REQUIRED EXTERNALLY

PART
NUMBER

25 Kohm

10 Kohm

-10

35 Kohm

No dash number

PART
NUMBER

RIN2B

RIN2A

RIN1B

RIN1A

VDD

N/C

TXCLK

CLK

N/C

D/R1

RSR

46 - N/C
45 -
44 - ENTX
43 - N/C
42 -
41 - 429DO
40 - N/C
39 -
38 -
37 - TX/R
36 -
35 -
34 - BD00

CWSTR

FFT
HFT

PL2
PL1

429DO

BD10

-2

BD09

-2

BD08

-2

BD07

-2

BD06

N/C

-2

VSS

-2

BD05

-2

BD04

BD03

-3

BD02

-3

BD01

-3

NFD

FF1

HF1

D/R2

FF2

HF2

EN1
EN2

- 8
- 9

- 10

- 11

- 12

SEL - 13

- 14

-15

BD15 - 16
BD14 - 17
BD13 - 18
BD12 - 19

BD11 - 20

HI-8584CJI

HI-8584CJT

52 - Pin Cerquad J-lead

(See page 1 for additional pin configuration)

Электронный компонент: HI-8584PQI