HI-8588
ARINC 429 LINE RECEIVER
DESCRIPTION
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Direct ARINC 429 line receiver interface
in a small outline package
Receiver input hystersis at least 2 volts
Test inputs that bypass analog input and
can power down and tri-state outputs
Plastic and ceramic package options -
surface mount and DIP
Mil processing available
FEATURES
PIN CONFIGURATION
SUPPLY VOLTAGES
FUNCTION TABLE
RECEIVER
-1.25V to 1.25V
-1.25V to 1.25V
0
0
0
0
-3.25V to -6.5V
3.25V to 6.5V
0
0
0
1
3.25V to 6.5V
-3.25V to -6.5V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
HI-Z
HI-Z
RINA
RINB
TESTA TESTB ROUTA ROUTB
vcc
= 5.0V 5%
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
VCC
SUPPLY
5 VOLT SUPPLY
2
TESTA
LOGIC INPUT
CMOS
3
RINB
ARINC INPUT
RECEIVER B INPUT
4
RINA
ARINC INPUT
RECEIVER A INPUT
5
GND
POWER
GROUND
6
ROUTA
LOGIC OUTPUT
RECEIVER CMOS OUTPUT A
7
ROUTB
LOGIC OUTPUT
RECEIVER CMOS OUTPUT B
8
TESTB
LOGIC INPUT
CMOS
PIN DESCRIPTION TABLE
The HI-8588 is an ARINC 429 bus interface receiver and is
available in a SO 8 pin package.
The technology is
analog/digital CMOS. The circuitry requires only a 5 volt
supply.
The ARINC bus can be connected directly to the chip. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are
just below the standard 6.5 volt minimum ARINC data
threshold and just above the standard 2.5 volt maximum
ARINC null threshold.
The TESTA and TESTB inputs bypass the analog for
testing purposes. Also if TESTA and TESTB are both taken
high, the analog powers down and the digital outputs tri-
state allowing wire-or possibilities.
Please refer to the HI-8588-10 for applications where an
external resistance in series with the ARINC inputs is
required for lightning protection or when the digital outputs
need to be a logic zero rather than open circuit when
TESTA and TESTB are both high.
See Holt Application Note AN-300 for more information on
lightning protection.
February 2003
www.holtic.com
(DS8588 Rev. B)
02/03
RINA - 4
TESTA - 2
VCC - 1
RINB - 3
5 - GND
7 - ROUTB
8 - TESTB
6 - ROUTA
8 - PIN PLASTIC NARROW BODY SOIC
8588PS
HOLT INTEGRATED CIRCUITS
HI-8588
FUNCTIONAL DESCRIPTION
RINA
RINB
NULL
ZERO
NULL
ONE
TEST
TESTA
TEST
TEST
TESTB
TESTA ' TESTB
ROUTB
TESTA ' TESTB
ROUTA
FIGURE 1 - RECEIVER BLOCK DIAGRAM
TEST
R
S
Q
R
LATCH
S
Q
LATCH
ESD
PROTECTION
AND
TRANSLATION
TXBOUT
TXAOUT
TX0IN
TX1IN
ARINC
Channel
RINB
RINA
TESTA
TESTB
{
HARDWIRE
OR
DRIVE FROM LOGIC
ROUTB
ROUTA
5V
VCC
V-
-15V
GND
TXD1
TXD0
RXD0
RXD1
HI-6010
8 BIT BUS
ARINC
Channel
1
2
8
6
7
4
3
4
5
6
7
3
2
HI-8588
FIGURE 2 - APPLICATION DIAGRAM
APPLICATION INFORMATION
15V
V+
8
5
HI-8586
SLP1.5
1
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider be-
tween VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resis-
tors at the ARINC input.
Figure 2 shows a possible application
of the HI-8588 interfacing an ARINC re-
ceive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
HOLT INTEGRATED CIRCUITS
2
HI-8588
Voltages referenced to Ground
Supply voltages
VCC...................................................7V
ARINC input - pins 3 & 4
Voltage at either pin......+29V to -29V
DC current per input pin................ 10mA
Power dissipation at 25C
plastic DIP............0.7W
ceramic DIP..........0.5W
Solder Temperature ........275C for 10 sec
Storage Temperature........-65C to +150C
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltages
VCC...........................................5V 5%
Temperature Range
Industrial Screening........-40C to +85C
Hi-Temp Screening.......-55C to +125C
Military Screening.........-55C to +125C
DC ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
ARINC input voltage
one or zero
VDIN
VNIN
differential voltage, pins 3 & 4
volts
6.5
10
13
2.5
logic input voltage
high
low
V
V
ARINC input resistance
RINA to RINB
R DIFF
RINA or RINB to Gnd or VCC
R SUP
logic input current
source
sink
I
I IH
IL
null
IH
IL
logic output drive current
one
zero
I
I
OH
OL
Current drain
operating
powerdown
common mode
VCOM
"
"
"
with respect to Ground
-
-
-
-
5.0
3.5
-
-
-
-
1.5
volts
volts
volts
volts
supplies floating
30
19
75
40
-
-
Kohm
Kohm
"
"
V
VIN
IN = 5 V
= 0 V
0.1
-
-
-
-
0.1
A
A
V
= 4.6V
OH
V
= 0.4V
OL
-0.8
-
-1.6
5.6
-
3.6
mA
mA
2.3
-
-
0.36
6.3
0.6
mA
mA
VCC = 5.0V UNLESS OTHERWISE STATED
OPERATING TEMPERATURE RANGE,
I
I
CC1
CC2
pins 2, 8 = 0V; pins 3, 4 open
pins 2, 8 = 5V; pins 3, 4 open
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating con-
ditions may cause permanent damage to the
device. These are stress ratings only. Opera-
tion at the limits is not recommended.
HOLT INTEGRATED CIRCUITS
3
VCC = 5.0V UNLESS OTHERWISE STATED
OPERATING TEMPERATURE RANGE,
HI-8588
AC ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
Receiver propagation delay
Output high to low
t phlr
-
Receiver output transition times
Output high to low
Output low to high
Output low to high
plhr
t
t fr
rr
t
-
-
-
80
80
600
600
50
50
ns
ns
ns
ns
Input capacitance (1)
ARINC differential
CAD
CAS
pF
-
5
10
10
ARINC single ended to Ground
Logic
CIN
-
-
-
-
10
pF
pF
defined in Figure 3, C = 50pF
-
-
L
V
pin 4 - pin 3
DIFF
0V
0V
1
-10V
5V
0V
t rr
t rr
t fr
t
10%
90%
t phlr
t
t plhr
t
5V
0V
t plhr
t
t phlr
t
pin 6
pin 7
FIGURE 3 - RECEIVER TIMING
1. Guaranteed but not tested
Notes:
ORDERING INFORMATION
PART
PACKAGE
TEMPERATURE
BURN
LEAD
NUMBER
DESCRIPTION
RANGE
FLOW
IN
FINISH
HI-8588PDI
8 PIN PLASTIC DIP
-40C TO +85C
I
NO
SOLDER
HI-8588PDT
8 PIN PLASTIC DIP
-55C TO +125C
T
NO
SOLDER
HI-8588PDM
8 PIN PLASTIC DIP
-55C TO +125C
M
YES
SOLDER
HI-8588PSI
8 PIN PLASTIC NARROW BODY SOIC
-40C TO +85C
I
NO
SOLDER
HI-8588PST
8 PIN PLASTIC NARROW BODY SOIC
-55C TO +125C
T
NO
SOLDER
HI-8588PSM
8 PIN PLASTIC NARROW BODY SOIC
-55C TO +125C
M
YES
SOLDER
HI-8588CRI
8 PIN CERDIP
-40C TO +85C
I
NO
SOLDER
HI-8588CRT
8 PIN CERDIP
-55C TO +125C
T
NO
SOLDER
HI-8588CRM
8 PIN CERDIP
-55C TO +125C
M
YES
SOLDER
HOLT INTEGRATED CIRCUITS
4
Package Type:
8-PIN PLASTIC DIP
8P
.385 .015
(4.699 .381)
7 TYP.
.025 .010
(.635 .254)
.335 .035
(8.509 .889)
.250 .010
(6.350 .254)
.100 .010
(3.540 .254)
.135 .015
(3.429 .381)
.055 .010
(1.397 .254)
.1375 .0125
(3.493 .318)
.019 .002
(.483 .102)
.0115 .0035
(.292 .089)
.300 .010
(7.620 .254)
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
HOLT INTEGRATED CIRCUITS
5
Package Type:
Detail A
0
to 8
Detail A
8HN
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
P 1
IN
.236 .008
(5.994 .203)
.1535 .0035
(3.90 .09)
.1935 .0035
(4.915 .085)
.0086 .0012
(.2184 .0305)
.050 .010
(1.27 .254)
.033 .017
(.8382 .4318)
.055 .005
(1.397 .127)
.0069 .0029
(.1753 .0737)
.0165 .0035
(.4191 .0889)
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
Package Type: 8D
8-PIN CERDIP
.380 .004
(9.652 .102)
.005 MIN.
(.127 MIN.)
.314 .003
(7.976 .076)
.200 MAX.
(5.080 MAX.)
.248 .003
(6.299 .076)
.100 .008
(2.540 .203)
.039 .006
(.991 .154)
.163 .037
(4.140 .940)
.018 .006
(.457 .152)
.056 .006
(1.422 .152)
.015 MIN.
(.381 MIN.)
.350 .030
(8.890 .762)
.010 .006
(.254 .152`)
Base Plane
Seating Plane
HOLT INTEGRATED CIRCUITS
6
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