HI-8683, HI-8684
ARINC INTERFACE DEVICE
ARINC 429 & 561 Serial Data to 8-Bit Parallel Data
DESCRIPTION
The HI-8683 and HI-8684 are system components for
interfacing incoming ARINC 429 signals to 8-bit parallel
data using proven +5V analog/digital CMOS technology.
The HI-8683 is a digital device that requires an external
analog line receiver such as the HI-8482 or HI-8588
between the ARINC bus and the device inputs. The HI-8684
incorporates the digital logic and analog line receiver
circuitry in a single device.
The HI-8683 is also available as a second source to the
DLS-112
18 pin DIP and 28 pin PLCC
package pinouts.
The receivers on the HI-8684 connect directly to the ARINC
429 Bus and translate the incoming signals to normal CMOS
levels.
Internal comparator levels are set just below the
standard 6.5 volt minimum data threshold and just above the
standard 2.5 volt maximum null threshold. The -10 version
of the HI-8684 allows the incorporation of an external 10K
resistance in series with each ARINC input for lightning
protection without affecting ARINC level detection.
Both products offer high speed 8-bit parallel bus interface, a
32-bit buffer, and error detection for word length and parity.
A reset pin is also provided for power-on initialization.
with the original
!
!
Automatic conversion of serial ARINC 429, 575 &
561 data to 8-bit parallel data
High speed parallel 8-bit data bus
Error detection -
and
On-chip line receiver option (HI-8684)
Input hysteresis of at least 2 volts (HI-8684)
Test inputs bypass analog inputs (HI-8684)
Simplified lightning protection with the ability to add
10 Kohm external series resistors (HI-8684-10)
Plastic package options - surface mount (SOIC),
PLCC and DIP
Military processing available
!
!
!
!
!
!
!
!
word length
parity
Reset input for power-on initialization
FEATURES
PIN CONFIGURATIONS
(Top View)
January 2001
DATARDY
D7
D6
D5
D4
D3
D2
D1
D0
HI-8684PSI
HI-8684PST
&
HI-8684PSI-10
HI-8684PST-10
1
2
3
4
5
6
7
8
9
10
(See page 8 for additional pin configurations)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
HI-8683
18-Pin Plastic SOIC - WB Package
HI-8684
20-Pin Plastic SOIC - WB Package
HI-8683PSI
HI-8683PST
Vcc
GAPCLK
INB
INA
ERROR
PARITY ENB
GND
RESET
READ
GAPCLK
TESTA
TESTB
RINB (-10)
RINA (-10)
ERROR
PARITY ENB
GND
RESET
READ
Vcc
DATARDY
D7
D6
D5
D4
D3
D2
D1
D0
HOLT INTEGRATED CIRCUITS
1
(DS8683 Rev. D)
01/01
HI-8683, HI-8684
PIN DESCRIPTIONS
DATA RDY
OUTPUT
Receiver data ready flag. A high level indicates data is available in the receive
buffer. Flag goes low when the first 8-bit byte is read.
D1 to D7
OUTPUT
8-bit parallel data bus (tri-state)
GND
POWER
0V
INPUT
Read strobe. A low level transfers receive buffer data to the data bus
PARITY ENB
INPUT
Parity Enable - A high level activates odd parity checking which replaces the
32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged
ERROR
OUTPUT
Error Flag. A high level indicates a bit count error (number of ARINC bits was
less than or greater than 32) and/or a parity error if parity detection was enabled
(PARITY ENB high)
INA
INPUT
Positive digital serial data input (HI-8683 only)
INB
INPUT
Negative digital serial data input (HI-8683 only)
RINA/RINA-10
INPUT
Positive direct ARINC serial data input
RINB/RINB-10
INPUT
Negative direct ARINC serial data input (HI-8684 & HI-8684-10 only)
INPUT
Internal logic states are initialized with a low level
TESTA
INPUT
Used in conjunction with the TESTB input to bypass the built-in analog line
receiver circuitry
TESTB
INPUT
U
GAPCLK
INPUT
Gap Clock. Determines the minimum time required between ARINC words for
detection. The minimum word gap time is between 16 and 17 clock cycles of
this signal.
Vcc
POWER
+5V 10% supply
SIGNAL
FUNCTION
DESCRIPTION
READ
RESET
(HI-8684 & HI-8684-10 only)
(HI-8684 & HI-8684-10 only)
sed in conjunction with the TESTA input to bypass the built-in analog line
receiver circuitry (HI-8684 & HI-8684-10 only)
HOLT INTEGRATED CIRCUITS
2
FUNCTIONAL DESCRIPTION
The HI-8683 and HI-8684 are serial to 8-bit parallel convert-
ers. The incoming data stream is serially shifted into an input
register, checked for errors, and then transferred in parallel to
a 32-bit receive buffer. The receive data can be accessed us-
ing four 8-bit parallel read operations while the next serial
data steam is being received.
Figure 1 is a block diagram of both the HI-8683 and HI-8684.
The difference between the two products is the HI-8684 has
a built-in line receiver whereas the HI-8683 is strictly a digital
device and requires an external ARINC line receiver such as
the Holt HI-8482, HI-8588 or HI-8590 to interface to the
ARINC 429 bus.
RECEIVER INPUTS
HI-8684 Line Receiver
Typically 35K
resistors are in series with both the RINA and
RINB ARINC 429 inputs. They connect to level translators
whose resistance to GND is typically 10K
After level trans-
lation, the buffered inputs drive a differential amplifier. The
differential signal is compared to levels derived from a divider
between VCC and GND. The nominal settings correspond to
a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A
valid ARINC One/Zero input sets a latch and a Null input re-
sets the latch.
Since any added external series resistance will affect the volt-
age translation, the HI-8684-10 is available with 25K
of the
35K
series resistance required for proper ARINC 429 level
detection. The remaining 10K
required that must be added
can be incorporated in other external circuitry such as light-
ning protection. Except for the different input series resis-
tance, the HI-8684 and HI-8684-10 are identical.
.
HI-8683, HI-8684
HOLT INTEGRATED CIRCUITS
3
PROTOCOL DETECTION
ARINC clock and data in the HI-8683 are derived from the
two streams of digital data at the INA and INB inputs and the
resulting One/Zero data is shifted into a 32-bit input register
as illustrated in Figure 3.
In the HI-8684, the One/Zero data shifted into the input reg-
ister is created from either the two digital outputs of the built-
in line receiver (Figure 3) or the TESTA and TESTB inputs
(Figure 4).
For ARINC 561 operation, the INA and INB data streams in-
puts must be derived from the ARINC 561 data, clock and
sync with external logic.
GAP DETECTION
The end of a data word is detected by an internal counter
that times out when a data One or Zero is not received for a
period equal to 16 cycles of the GAPCLK signal. The gap
detection time may vary between 16 and 17 cycles of the
GAPCLK signal since the incoming data and GAPCLK are
not usually synchronous inputs. The required frequency of
GAPCLK is a function of the mininum gap time specified for
the type of ARINC data being received. Table 1 indicates
typical frequencies that may be used for the various data
rates normally encountered.
BIT
COUNT
PARITY
DETECT
GAP
DETECT
32-BIT
SHIFT
REG.
32-BIT
RECEIVE
BUFFER
32-BIT
TO
8-BIT
MUX
ERROR
DETECT
CLOCK
&
DATA
DETECT
HI-8683 ONLY
HI-8684 ONLY
INA
PARITY
ENB
INB
RINB
TESTA
TESTB
GAPCLK
RESET
BYTE
COUNT
READ
DATA RDY
ERROR
32
8
32
Figure 1. Block Diagram
ESD
PROTECTION
&
LINE
RECEIVER
ESD
PROTECTION
DATABUS
BIT PERIOD
MINIMUM GAP
GAP CLOCK
GAP DETECTION
TYPE
( s)
( s)
MHz
TIME ( s)
429
10
45
0.75
21.3 - 22.7
1.0
16 - 17
1.5
10.7 - 11.3
429
69 - 133
310 - 599
0.1
160 - 170
575
69 - 133
310 - 599
0.1
160 - 170
561
69 - 133
103 - 200
0.2
80 - 85
Table 1 - Typical Gap Detection Times
FUNCTIONAL DESCRIPTION (cont.)
RXA
RXB
10K
BIT 32
BIT 32
RINA
D0 - D7
DATA
CLK
RINB-10
RINA-10
10K
25K
25K
HI-8683, HI-8684
HOLT INTEGRATED CIRCUITS
4
ERROR CHECKING
READING RECEIVE BUFFER
Once a word gap is detected, the data word in the input reg-
ister is transferred to the receive buffer and checked for er-
rors.
When parity detection is enabled (PARITY ENB high), the
received word is checked for odd parity. If there is a parity
error, the 32nd bit of the received data word is set high.
If parity checking is disabled (PARITY ENB low) the 32nd
bit of the data word is always the 32nd ARINC bit received.
The ERROR flag output is set high upon receipt of a word
gap and the number of bits received since the previous
word gap is less than or greater than 32. The ERROR flag
is reset low when the next valid ARINC word is written into
the receive buffer or when
is pulsed low.
When the data word is transferred to the receive buffer, the
DATA RDY pin goes high. The data word can then be read
in four 8-bit bytes by pulsing the
input low as indi-
cated in Figure 5. The first read cycle resets DATA RDY
low and increments an internal counter to the next 8-bit
byte. The counter continues to increment on each read cy-
cle until all four bytes are read. The relationship between
each bit of an ARINC word received and each bit of the four
8-bit data bus bytes is specified in Figure 2.
When a new ARINC word is received it always overwrites
the receive buffer. If the first byte of the previous word has
not been read, then previous data is lost and the receive
buffer will contain the new ARINC word. However, if the
DATA RDY pin goes high between the reading of the first
and fourth bytes, the previous read bytes are no longer
valid because the unread bytes have been overwritten by
the new ARINC word. Also, the next read will be of the first
byte of the new ARINC word since the internal byte counter
is always reset to the first byte when new data is trans-
ferred to the receive buffer.
RESET
READ
FUNCTIONAL DESCRIPTION (cont.)
TRUTH TABLE 1.
RINA
RINB
TESTA
TESTB
RXA
RXB
-1.50 to +1.50V
-1.50V to +1.50V
0
0
0
0
-3.25V to -6.50V
+3.25V to +6.50V
0
0
0
1
+3.25V to +6.50V
-3.25V to -6.50V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
0
0
X = don't care
Read
Byte
Data Bus Bits
ARINC Bits
1st
Byte 1
D0 - D7
ARINC 1 - ARINC 8
2nd
Byte 2
D0 - D7
ARINC 9 - ARINC 16
3rd
Byte 3
D0 - D7
ARINC 17 - ARINC 24
4th
Byte 4
D0 - D7
ARINC 25 - ARINC 32
FIGURE 2. ORDER OF RECEIVED DATA
RESET
TEST MODE (HI-8684 only)
A low on the
input sets a flip-flop which initializes
the internal logic. When
goes high, the internal
logic remains in the initialized state until the first word gap is
detected preventing reception of a partial word.
The built-in differential line receiver on the HI-8684 can be
disabled allowing the data and clock detection circuitry to
be driven directly with digital signals. The logical OR func-
tion of the TESTA and TESTB is defined in Truth Table 1.
The two inputs can be used for testing the receiver logic and
for inputting ARINC 429 type data derived from another
source/ protocol. See Figure 4 for typical test input timing.
The device should always be initialized with
imme-
diately after entering the test mode to clear a partial word
that may have been received since the last word gap. Oth-
erwise, an ERROR condition may occur and the first 32
bits of data on the test inputs may not be properly re-
ceived.
Also, when entering the test mode, both TESTA and
TESTB should be set high and held in that state for at
least one word gap period (17 gap clocks) after
goes high.
When exiting the test mode, both test inputs should be held
low and the device initialized with
RESET
RESET
RESET
RESET
RESET.
HOLT INTEGRATED CIRCUITS
5
HI-8683, HI-8684
ARINC Data Bits
Word Gap
28
29
30
31
32
1
2
4 Bit Periods Min.
INA (HI-8683 only)
INB (HI-8683 only)
VDIFF
RINA - RINB
(HI-8684 only)
DERIVED DATA
DERIVED CLOCK
0V
0V
+5V
0V
+10V
+5V
-10V
TIMING DIAGRAMS
FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429
FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING
DATA RDY
READ
D0 - D7
VALID
t
RDYCLR
t
RDPW
t
RR
t
FD
t
RD
VALID
VALID
VALID
1st 8-bits
2nd 8-bits
3rd 8-bits
4th 8-bits
t
DRDY
DERIVED DATA
32nd
ARINC Bit
FIGURE 4 - TEST INPUT TIMING FOR ARINC 429
ARINC Data Bits
Word Gap
28
29
30
31
32
1
2
4 Bit Periods Min.
TESTA
+5V
0V
TESTB
0V
+5V
DERIVED CLOCK
DERIVED DATA
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
ARINC Bus Inputs (RINA & RINB, HI-8684 only)
Differential input voltage
one or zero
V
differential voltage
6.5
10.0
13.0
volts
null
V
"
"
"
"
-
-
2.75
volts
common mode
V
with respect to GND
-
-
5.0
volts
Input resistance
RINA (-10) to RINB (-10)
R
supplies floating
30
75
-
Kohm
RINA (-10) or RINB (-10) to GND or V
R
"
"
"
'
19
40
-
Kohm
Input capacitance (Guaranteed but not tested)
differential
C
RINA to RINB
-
-
20
pF
to GND
C
-
-
20
pF
to V
C
-
-
20
pF
DIN
NIN
COM
DIFF
CC
SUP
DIFF
G
CC
H
Supply Voltages
V
.................................................+5V
Temperature Range
Industrial Screening .............. -40C to +85C
Hi-Temp Screening .............. -55C to +125C
Military Screening..................-55C to +125C
Junction Temperature, Tj ....................
175C
CC
10%
+
All voltages referenced to GND
Supply voltages
V
....................................................... +7.0V
Voltage on inputs
RINA (-10) to RINB (-10) ......... +29V to - 29V
All other input pins..................-0.3 to Vcc +0.3
DC current per input pin ....................... +10mA
Power dissipation at 25C
plastic 18-pin SO..... 1.9W, derate 15.4mW/C
plastic 18-pin DIP .....1.6
plastic 20-pin SO......1.4
plastic 20-pin PLCC .2.0
Solder Temperature
Leads ................................ +280C for 10 sec
Package body .....................................+220C
Storage Temperature ............. -65C to +150C
CC
W, derate 13.3mW/C
W, derate 11.5mW/C
W, derate 17.2mW/C
NOTE: Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to
the device.
These are stress ratings only.
Operation at the limits is not recommended.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
DC ELECTRICAL CHARACTERISTICS
HI-8683, HI-8684
HOLT INTEGRATED CIRCUITS
6
Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
HI-8683, HI-8684
HOLT INTEGRATED CIRCUITS
7
DC ELECTRICAL CHARACTERISTICS (cont.)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Digital Inputs
Outputs
Operating Supply Current
(INA, INB,
, GAPCLK,
, PARITY ENA, TESTA & TESTB)
Input voltage
high
V
2.0
-
V
low
V
0.0
-
0.8
volts
Input current
source
-
-
1.0
sink
-1.0
-
-
Input capacitance
C
-
-
8.0
pF
(D0 to D7, ERROR & DATA RDY)
Output voltage
high
low
I
= 1.6 mA
-
-
0.4
volts
Output tri-state current (D0 - D7 only)
V
= 5.0V
-
-
1.0
A
V
= 0.0V
-1.0
-
-
Output capacitance
-
-
15
pF
V
(HI-8683 only)
I
V
= 0.0V, outputs open
-
-
0.2
m
V
(HI-8684 only)
I
V
= 0.0V, outputs open
-
-
6.5
m
RESET
READ
IH
CC
IL
I
OL
OH
OL
CC
CC1
IN
CC
CC2
IN
volts
I
V
= 5.0V
A
I
V
= 0.0V
A
V
I
= -1.0 mA
2.7
-
-
volts
V
I
I
A
C
A
A
IH
IN
IL
IN
OH
OH
OL
IH
IL
O
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
pulse width
t
50
ns
Data delay from
t
20
ns
to data floating
t
20
ns
to DATA RDY clear
t
25
ns
pulse to next
pulse
t
25
ns
GAPCLK frequency
f
1
MHz
32 ARINC bit to DATA RDY
t
16
17
clocks
READ
READ
READ
READ
READ
READ
RDPW
RD
FD
RDYCLR
RR
GC
DRDY
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
HI-8683 & HI-8684 PIN CONFIGURATIONS
(See page 1 for additional pin configurations)
HI-8683, HI-8684
HOLT INTEGRATED CIRCUITS
8
HI-8683PJI
HI-8683PJT
18 - N/A
17 -
16 - INB
15 - INA
14 - ERROR
RESET
D6 - 4
D5 - 5
D4 - 6
D3 - 7
D2 - 8
V
GAPCLK
INB
INA
ERROR
PARITY
ENB
D0
CC
RESET
READ
DATA
RDY
D6
D7
D5
D4
D3
D2
D1
GND
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
HI-8683PDI
HI-8683PDT
HI-8684PJI
HI-8684PJT
&
HI-8684PJI-10
HI-8684PJT-10
18 - TESTB
17 -
16 - RINB (-10)
15 - RINA (-10)
14 - ERROR
RESET
D6 - 4
D5 - 5
D4 - 6
D3 - 7
D2 - 8
HI-8683
20-Pin Plastic PLCC
HI-8684
20-Pin Plastic PLCC
HI-8683
18-Pin Plastic DIP
ORDERING INFORMATION
HI-8683PDI
18 PIN PLASTIC DIP
NO
NO
-40C TO +85C
I
NO
SOLDER
HI-8683PDT
18 PIN PLASTIC DIP
NO
-55C TO +125C
T
NO
SOLDER
HI-8683PJI
20 PIN PLASTIC PLCC
NO
BUILT-IN
PART
PACKAGE
LINE
10K
RES. TEMPERATURE
BURN
LEAD
NUMBER
DESCRIPTION
RECV'R
REQUIRED RANGE
FLOW
IN
FINISH
NO
NO
-40C TO +85C
I
NO
SOLDER
HI-8683PJT
20 PIN PLASTIC PLCC
NO
NO
-55C TO +125C
T
NO
SOLDER
HI-8683PSI
18 PIN PLASTIC SOIC - WB
NO
NO
-40C TO +85C
I
NO
SOLDER
HI-8683PST
18 PIN PLASTIC SOIC - WB
NO
NO
-55C TO +125C
T
NO
SOLDER
HI-8684PJI
20 PIN PLASTIC PLCC
YES
NO
-40C TO +85C
I
NO
SOLDER
HI-8684PJT
20 PIN PLASTIC PLCC
YES
NO
-55C TO +125C
T
NO
SOLDER
HI-8684PSI
20 PIN PLASTIC SOIC - WB
YES
NO
-40C TO +85C
I
NO
SOLDER
HI-8684PST
20 PIN PLASTIC SOIC - WB
YES
NO
-55C TO +125C
T
NO
SOLDER
HI-8684PJI-10
20 PIN PLASTIC PLCC
YES
YES
-40C TO +85C
I
NO
SOLDER
HI-8684PJT-10 20 PIN PLASTIC PLCC
YES
YES
-55C TO +125C
T
NO
SOLDER
HI-8684PSI-10
20 PIN PLASTIC SOIC - WB
YES
YES
-40C TO +85C
I
NO
SOLDER
HI-8684PST-10 20 PIN PLASTIC SOIC - WB
YES
YES
-55C TO +125C
T
NO
SOLDER
Legend:
WB
- Wide Body
.454 .008
(11.531 .203)
.4065 .0125
(10.325 .318)
.293 .006
(7.442 .152)
.050
(1.27)
0 to 8
.033 .017
(.838 .432)
.090 .010
(2.286 .254)
.0075 .0035
(.191 .089)
TYP
.018
(.457)
TYP
SEE DETAIL A
DETAIL A
Package Type:
18-PIN PLASTIC SMALL OUTLINE (SOIC) - WB
(Wide Body)
18HW
.0105 .0015
(.2667 .0381)
.905
.015
(22.99
.381)
.300
.010
(7.62
.254)
.335 .035
(8.509
.889)
0
~ 15
.135
.015
(3.429
.381)
.100
.010
(2.540
.254)
.055
.010
(1.397
.254)
.019
.004
(.483
.102)
.130
.020
(3.302
.508)
.160
.025
(4.064
.635)
.250
.010
(6.350
.254)
7
TYP.
.0115 .0035
(.2921 .0889)
HI-8683, HI-8684 PACKAGE DIMENSIONS
inches (millimeters)
HOLT INTEGRATED CIRCUITS
9
Package Type:
18-PIN PLASTIC DIP
18P
.5035 .0075
(12.789 .191)
.4065 .0125
(10.325 .318)
.296 .003
(7.518 .076)
0 to 8
.090 .010
(2.286 .254)
.0075 .0035
(.191 .089)
.050
(1.27)
TYP
.018
(.457)
TYP
SEE DETAIL A
DETAIL A
.033 .017
(.838 .432)
Package Type:
20-PIN PLASTIC SMALL OUTLINE (SOIC) - WB
(Wide Body)
20HW
.0105 .0015
(.2667 .0381)
.152 .002
(.3.861 .051)
PIN NO. 1 IDENT
.045 x 45
.354
.002
(8.991
.051)
.390
.005
(9.906
.127)
SQ.
SQ.
SEE DETAIL
A
.017
.004
(.432
.102)
DETAIL A
.020 MIN
(.508
.015
.002
(.381
.051)
.050
.003
(1.27
.075)
)
.026 .003 x 30
(.660 .076 x 30)
.035 R
(.889 R)
TYP
.010 .0003
(.256 .0076)
.020 MIN
(.508 MIN)
.320 .010
(8.128 .254)
inches (millimeters)
Package Type:
20-PIN PLASTIC PLCC
20J
HI-8683, HI-8684 PACKAGE DIMENSIONS
HOLT INTEGRATED CIRCUITS
10
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